Bidirectional FIFO Buffer Having Reread and Rewrite Means

1. Field of the Invention

The present invention relates to integrated circuit type devices generally and more particularly to a bidirectional FIFO buffer having means for eight-bit-to-sixteen-bit and sixteen-bit-to-eight-bit conversion.

2. Description of the Related Art

A FIFO (first-in-first-out) buffer functions as a shift register having an additional control section that permits input data to "fall through" to the first vacant stage. In other words, if there is data stored in the FIFO buffer, it is available at the output even though all of the stages are not filled. Thus, in effect, a FIFO buffer functions as a "variable-length" shift register, the length of which is always the same as the data stored therein. (Although shift registers may be used, of late, many FIFO buffers are implemented with random access memories (RAMs) and counters.) For additional information regarding FIFO buffers, the reader is referred to my U.S. Pat. No. 4,750,149.

As such, FIFO buffers are particularly suited for use in applications in which there is a need to compensate for differences in the rate of flow of data. For example, FIFO buffers are particularly suited for use in storing data which is to be written onto a disk and/or which has been read off of a disk; for use in storing data which is to be transmitted to a local area network (LAN) and/or which has been received from a LAN; and for use in storing data which is to be printed.

Heretofore, no doubt due to the predominance of eight-bit microprocessors and/or eight-bit peripherals, most FIFO buffers have been designed with an eight-bit word length (to store eight bits of data at a time.) Of late, however, sixteen-bit and thirty-two-bit microprocessors have been gaining in popularity. Although many sixteen-bit and thirty-two-bit microprocessors have means for communicating with eight-bit peripherals (and FIFO buffers), such communication is, usually, less efficient than communication with sixteen-bit and/or thirty-two-bit peripherals. Thus, a need exists for FIFO buffers which have means for eight-bit-to-sixteen-bit and sixteen-bit-to-eight-bit conversion.

Also, since data may be corrupted when transmitted over a LAN, a need exists for FIFO buffers which have means for re-reading (for re-transmission) data stored in the buffer and/or re-writing (over-writing) data stored in the buffer (with re-transmitted data).

In addition, a need exists for FIFO buffers suitable for interfacing sixteen-bit and thirty-two-bit microprocessors with eight-bit microprocessors, non-direct memory access (DMA) type peripheral devices, and DMA-type peripheral devices.

Further, a need exists for FIFO buffers having means for direct (by-pass) communication with peripheral devices.

It is therefore the primary object of the present invention to provide a FIFO buffer having means for eight-bit-to-sixteen-bit and sixteen-bit-to-eight-bit conversion.

Another object of the present invention is to provide a FIFO buffer having means for re-reading and re-writing data.

Another object of the present invention is to provide a FIFO buffer suitable for interfacing sixteen-bit and thirty-two-bit microprocessors with eight-bit microprocessors, non-DMA type peripheral devices, and DMA-type peripheral devices.

Yet another object of the present invention is to provide a FIFO buffer having means for direct (by-pass) communication with peripheral devices.

Briefly, the presently preferred embodiment of a bidirectional FIFO buffer in accordance with the present invention employs a 1 K by eighteen FIFO (A.fwdarw.B) buffer portion to store eighteen-bit words; an eighteen-bit-to-nine-bit multiplexer portion to convert (fold) stored eighteen-bit words into two, nine-bit words; a nine-bit-to-sixteen-bit multiplexer portion to convert (assemble) pairs of nine-bit words into one, eighteen-bit word; a 1 K by eighteen FIFO (B.fwdarw.A) buffer portion to store (eighteen-bit) words; eighteen, tri-state, buffers to permit direct communication; a parity generator portion; a parity checking portion; the combination of an A-port access control portion and a programmable flag logic portion to permit connection to a sixteen-bit or a thirty-two-bit microprocessor; and the combination of a B-port access control portion and a hand shake interface control portion to permit connection to an eight-bit microprocessor, a non-direct memory access (DMA) type peripheral device, or a DMA-type peripheral device.

These and other objects of the present invention will no doubt become apparent to those skilled in the art after having read the detailed description of the presently preferred embodiment of the present invention which is illustrated in the figures of the drawing.

FIG. 1 is a simplified block diagram of a bidirectional FIFO buffer having means for eight-bit-to-sixteen-bit sixteen-bit-to-eight-bit conversion in accordance with the present invention;

FIG. 2 is a block diagram of the FIFO buffer shown in FIG. 1 connected between a sixteen-bit microprocessor and an eight-bit microprocessor;

FIG. 3 is a block diagram of the FIFO buffer shown in FIG. 1 connected between the sixteen-bit microprocessor shown in FIG. 2 and a DMA-type peripheral device;

FIG. 4 is a schematic diagram of (a re-read) part of the FIFO (A.fwdarw.B) buffer portion shown in FIG. 1;

FIG. 5 is a schematic diagram of (a re-write) part of the FIFO (B.fwdarw.A) b portion shown in FIG. 1;

FIG. 6 is a schematic diagram of (a RAM array) part of the FIFO (A.fwdarw.B) buffer portion and the eighteen-bit-to-nine-bit multiplexer the shown in FIG. 1;

FIG. 7 is a schematic diagram of (a RAM array) part of the FIFO (B ->A) buffer portion and a part of the nine-bit-to-eighteen-bit converter portion, both shown in FIG. 1;

FIG. 8 is a schematic diagram of (a read latch) part of the nine-bit-to-eighteen-bit converter portion shown in FIG. 1;

FIG. 9 is a schematic diagram of (a latch re-write part of the nine-bit-to-eighteen-bit converter portion shown in FIG. 1;

FIG. 10 is a schematic diagram further illustrating the bidirectional FIFO buffer shown in FIG. 1;

FIG. 11 is a schematic diagram of a part of the A-port access control portion shown in FIG. 1;

FIG. 12 is a diagram illustrating another part of the A-port access control ion shown in FIG. 1;

FIG. 13 is a diagram illustrating a command register of the A-port access control portion shown in FIG. 1;

FIG. 14 is a diagram illustrating a status register of the port access control portion shown in FIG. 1;

FIGS. 15-18 are diagrams illustrating a number of configuration registers of the A-port access control portion shown in FIG. 1;

FIG. 19 is schematic diagram of a portion of the programmable flag logic portion shown in FIG. 1; and

FIG. 20 is a schematic diagram of the hand shake interface control portion shown in FIG. 1.

Illustrated in FIG. 1 of the drawing generally designated by the number 100 is a simplified block diagram of the presently preferred embodiment of a bidirectional FIFO buffer having means for eight-bit-to-sixteen-bit and sixteen-bit-to-eight-bit conversion in accordance with the present invention. FIFO buffer 100 is shown to employ a 1 K by eighteen FIFO (A.fwdarw.B) buffer portion, which is designated 110; an eighteen-bit-to-nine-bit multiplexer portion, which is designated 112; a 1 K by eighteen FIFO (B.fwdarw.A) buffer portion, which is designated 114; a nine-bit-to-sixteen-bit multiplexer portion, which is designated 116; nine, tri-state, buffers, which are represented by a buffer 118; nine more, tri-state, buffers, which are represented by a buffer 120; a parity generator portion, which is designated 122; a parity checking portion, which is designated 124; an A-port access control portion, which is designated 126; a programmable flag logic portion, which is designated 128; a B-port access control portion, which is designated 130; and a hand shake interface control portion, which is designated 132.

FIFO (A.fwdarw.B) buffer portion 110 is configured to store words represented by signals externally developed on an eighteen-line data (A) bus 140. Stored are eighteen-bit words, each of which includes sixteen-bits of data and two, optional, bits of parity. Further, portion 110 is configured to develop on an eighteen line bus 142 signals representing stored (eighteen-bit) words.

Eighteen-bit-to-nine-bit multiplexer portion 112 is configured to receive each of the (eighteen-bit) words represented by signals developed on bus 142. Further, portion 112 is configured to convert {fold) each of the eighteen-bit words into two, nine-bit words. The eighteen-bit words are converted with the eight lower-order bits of the sixteen data bits and the corresponding parity bit forming one of the two nine-bit words and with the eight higher-order bits of the sixteen data bits and the corresponding parity bit forming the other one of the two nine-bit words. Finally, portion 112 is configured to (with a pair of multiplexers, not shown) develop on a nine-line data (B) bus 144 signals representing each of the nine-bit words.

Conversely, Nine-bit-to-sixteen-bit converter portion 116 is configured to receive words represented by signals externally developed on data (B) bus 144. Received are nine-bit words, each of which includes eight-bits of data and one, optional, bit of parity. Further, portion 116 is configured to convert (assemble) each pair of the nine-bit words into one, eighteen-bit word. Finally, portion 116 is configured to develop on an eighteen-line bus 148 signals representing each of the eighteen-bit words.

FIFO (B.fwdarw.A) buffer portion 114 is configured to store (eighteen-bit) words represented by signals developed on the eighteen lines of bus 148 and to develop on the eighteen lines of data (A) bus 140 signals representing stored (eighteen-bit) words.

The nine, tri-state, buffers represented by buffer 118 with a multiplexer and nine buffers, not shown) are configured to, selectively, couple signals externally developed on nine of the eighteen lines of data (A) bus 140 to the nine lines of data (B) bus 144. The lower-order eight data bit signals developed on data (A) bus 140 are coupled to the eight data bit lines of data (B) bus 144; and, the associated bus 140 parity bit signal is coupled to the parity bit line of data (B) bus 144. Conversely, the nine, tri-state, buffers represented by buffer 120 (with nine buffers, not shown) are configured to, selectively, couple signals externally developed on the nine lines of data (B) bus 144 to nine of the eighteen lines of data (A) bus 140. The eight data bit signals developed on data (B) bus 144 are coupled to the eight lower-order data bit lines of bus 140; and, the data (B) bus 144 parity bit signal is coupled to the corresponding parity bit line of bus 140.

Parity generator portion 122 is configured to receive the eight data bit signals developed on eight of the nine data (B) bus 144 lines and to generate, therefrom, a corresponding parity bit signal. Portion 122, selectively, couples the parity bit to the parity bit line of data (B) bus 144. Parity checking portion 124 is configured to compare the parity bit signal developed by parity generator portion 122 with the parity bit signal developed on the parity bit line of data (B) bus 144 and to develop a signal which indicates whether the signals have similar or different logic states.

A-port access control portion 126 includes circuitry which, with data (A) bus 140, is for interfacing FIFO buffer 100 to a (sixteen-bit or thirty-two-bit) microprocessor. Portion 126 is configured to receive five externally developed signals, including an (active low) chip selecting (A) signal on a line 150, an (active low) data strobe (A) signal on a line 152, a read/write signal on a line 154, and a pair of addressing (A(0) and A(1)) signals on a pair of lines 156 and 158.

Programmable flag logic portion 128 develops four, programmable, flags, including a FIFO buffer 100 (A.fwdarw.B) (nearly) empty flag (A) on a line 160, a FIFO buffer 100 (A.fwdarw.B) (nearly) full flag (B) on a line 162, a FIFO buffer 100 (B.fwdarw.A) (nearly) empty flag (C) on a line 164, and a FIFO buffer 100 (B.fwdarw.A) (nearly) full flag (D) on a line 166.

B-port access control portion 130 and hand shake interface control portion 132 include circuitry which, with data (B) bus 144, is for interfacing FIFO buffer 100 to an (eight-bit) microprocessor, a direct memory access (DMA) type peripheral device, or a non-DMA-type peripheral device. In a non-DMA mode, B-port access control portion 130 is configured to receive an externally developed (active low) data strobe (B) signal on a line 170 and a read/write signal on a line 172. In a DMA mode, hand shake interface control portion 132 is configured to receive an externally developed request signal on a line 174 and a clocking signal on a line 176 and to develop an acknowledge signal on a line 178. In this (DMA) mode, B-port access control portion 130 is configured to develop the (active low) data strobe (B) signal on line 170 and the read/write signal on line 172. Further, B-port access control portion 130 is configured to receive an externally developed (active low) re-read (FIFO (A.fwdarw.B) buffer) signal on a line 180 and a re-write (over-write) (FIFO (B.fwdarw.A) buffer) signal on a line 182.

Finally, FIFO buffer 100 employs circuitry permitting buffer 100 to be cascaded with a similar buffer for use with thirty-two-bit microprocessors.

FIFO buffer 100 is shown connected between a sixteen-bit microprocessor 190 and an eight-bit microprocessor 192 in FIG. 2; and, in FIG. 3 the FIFO buffer shown connected between the sixteen-bit microprocessor (190) and a DMA-type peripheral device 196.

FIFO (A.fwdarw.b) buffer portion 110 is implemented with a dual-port, static, 1 K by eighteen, random access memory (RAM) array and counters. The counters, and associated (re-read pointer logic) circuitry are illustrated in FIG. 4. Shown is the combination of a write pointer register 200 and circuitry 202 for incrementing the register, the combination configured to form an eleven-bit counter 204 for developing (FIFO (A.fwdarw.B) buffer portion 110) RAM array addressing, write pointer signals on an eleven line bus 206. For reasons which will become apparent shortly, although the associated RAM array only uses a ten-bit address, counter 204 develops an eleven-bit address.

Also shown is the combination of a multiplexer 210, a read pointer register 212, and circuitry 214 for incrementing the register, the combination configured to form a presetable, twelve-bit counter 216 for loading a re-read address represented by signals developed on a bus 218 and for developing (FIFO (A.fwdarw.B) buffer portion 110) RAM array addressing, read pointer signals on a twelve line bus 220. For reasons which will become apparent shortly, although the associated RAM array only uses a ten-bit address, counter 216 develops a twelve-bit address.

Finally, another multiplexer 224, yet another multiplexer 226, and a re-read pointer latch 228 are shown. Multiplexer 224 is configured to be responsive to a configuration re-read enable signal externally developed on a line 230 and operative to couple either the (FIFO (A.fwdarw.B) buffer portion 110) RAM array addressing, read pointer signals developed on bus 220 or the re-read addressing signals developed on bus 218 to a bus 232 to, with the (FIFO (A.fwdarw.B) buffer portion 110) RAM array addressing, write pointer signals developed on bus 206, drive programmable flag logic portion 128. The combination of multiplexer 226 and re-read pointer latch 228 are configured to form a register 236. Multiplexer 226 is configured to be responsive to a load re-read pointer command signal externally developed on a line 237 and operative to load the (FIFO (A.fwdarw.B) buffer portion 110) RAM array addressing, read pointer signals developed on bus 220 to a bus 238 and into re-read latch 228. Re-read pointer latch 228 is configured to store the state of each of the the (FIFO (A.fwdarw.B) buffer portion 110) RAM array addressing, read pointer signals and to develop the re-read addressing signals on bus 218 so as to have the stored states.

FIFO (B.fwdarw.A) buffer portion 114, which is illustrated in FIG. 5, is similar to FIFO (A.fwdarw.B) buffer portion 110 (FIG. 4). Of course, a (portion 114) counter 254 (which corresponds to portion 110 counter 204) develops (FIFO (B.fwdarw.A) buffer portion 114) RAM array addressing, read pointer signals on a bus 256. Also, a (portion 114) counter 266 (which corresponds to portion 110 counter 216) develops (FIFO (B.fwdarw.A) buffer portion 114) RAM array addressing, write pointer signals on a bus 270. Further, a (portion 114) multiplexer 274 (which corresponds to portion 110 multiplexer 224) is responsive to a configuration re-write enable signal externally developed on a line 280 and operative to couple either the (FIFO (B.fwdarw.A) buffer portion 114) RAM array addressing, write pointer signals developed on bus 270 or re-write addressing signals developed on a bus 268 to a bus 282 to, with the (FIFO (B.fwdarw.A) buffer portion 110) RAM array addressing, read pointer signals developed on bus 256, drive programmable flag logic portion 128. Finally, a (portion 114) register 286 (which corresponds to portion 110 register 236) develops (FIFO (B.fwdarw.A) buffer portion 114) re-write addressing signals on bus 268.

The dual-port, static, 1 K by eighteen, random access memory (RAM) array part of FIFO (A.fwdarw.B) buffer portion 110 and eighteen-bit-to-nine-bit multiplexer portion 112 are illustrated in FIG. 6. The RAM array, which is designated 300, is configured with a set of eighteen, read data inputs connected, each input to a corresponding line of the eighteen lines of data (A) bus 140. Also, RAM array 300 is configured with a set of ten, write data addressing inputs each connected to a respective line of bus 206. The RAM array 300 write data addressing inputs are not connected to a line of bus 206 upon which the highest order addressing signal is developed. Rather, the ten RAM array 300 write data addressing inputs are connected each to respective one of the ten lines of bus 206 upon which the next lower order addressing signals are developed. Further, RAM array 300 is configured with a set of ten, read data addressing inputs each connected to a line of bus 220. The RAM array 300 read data addressing inputs are not connected to a line of bus 220 upon which the highest order addressing signal is developed nor to a line 304 of the bus (220) upon which the lowest order addressing signal is developed. Rather, the ten RAM array 300 read data addressing inputs are connected each to respective one of the other ten lines of bus 220. Finally, RAM array 300 is configured and with a set of eighteen, write data outputs each connected to a corresponding line of bus 142.

Eighteen-bit-to-nine-bit multiplexer portion 112 is configured with a first set of nine data inputs each connected to a respective one of the nine lines of bus 142 upon which the signals representing the eight lower-order bits of the sixteen data bits and the corresponding parity bit forming one of the two nine-bit words are developed. In addition, portion 112 is configured with a second set of nine data inputs each connected to a respective one of the nine lines of bus 142 upon which the signals representing the eight higher-order bits of the sixteen data bits and the corresponding parity bit forming the other one of the two nine-bit words are developed. Further, portion 112 is configured with a select input connected to line 304 (the line of bus 220 upon which the lowest order addressing signal is developed). Finally, portion 112 is configured with a set of nine data outputs each coupled by a pair of multiplexers (not shown) and nine buffers (also not shown) to a corresponding one of the nine lines of data (B) bus 144. Further, portion 112 is configured to be responsive to the state of the lowest order addressing signal developed on line 304 of bus 220 and operative to couple either the signals developed at the first portion 112 set of inputs (the bus 142 signals representing the eight lower-order bits of the sixteen data bits and the corresponding parity bit forming one of the two nine-bit words) or the signals developed at the second portion 112 set of data inputs (the bus 142 signals representing the eight higher-order bits of the sixteen data bits and the corresponding parity bit forming the other one of the two nine-bit words) each to the respective one of the nine lines of data (B) bus 144.

Illustrated in FIG. 7 is a dual-port, static 1 K by eighteen, random-access memory (RAM) array which forms a part of FIFO (B.fwdarw.A) buffer portion 114 and a part of nine-bit-to-eighteen-bit converter portion 116. The RAM array, which is designated 400, is configured with a set of eighteen, write data outputs connected, each output to a corresponding line of the eighteen lines of data (A) bus 140. Also, RAM array 400 is configured with a set of ten, read data addressing inputs each connected to a respective line of bus 256. The RAM array 400 read data addressing inputs are not connected to a line of bus 256 upon which the highest order addressing signal is developed. Rather, the ten RAM array 400 write data addressing inputs are connected each to respective one of the ten lines of bus 256 upon which the next lower order addressing signals are developed. Further, RAM array 400 is configured with a set of ten, write data addressing inputs each connected to a line of bus 270. The RAM array 400 write data addressing inputs are not connected to a line of bus 270 upon which the highest order addressing signal is developed nor to a line 406 of the bus (270) upon which the lowest order addressing signal is developed. Rather, the ten RAM array 400 read data addressing inputs are connected each to respective one of the other ten lines of bus 270. Finally, RAM array 400 is configured with a set of eighteen, read data outputs each connected to a corresponding line of bus 148.

Nine-bit-to-eighteen-bit converter portion 116 is shown to include a latch 420. Latch 420 is configured with a set of nine data outputs each connected to the corresponding line of a nine line bus 422, the lines of which are the nine lines of bus 148 upon which the signals representing the eight lower-order bits of the sixteen data bits and the corresponding parity bit forming one of the two nine-bit words are developed. Additionally, latch 420 is configured with a clock (enable) input connected to line 406 (the line of bus 270 upon which the lowest order addressing signal is developed) and with a set of nine data inputs each coupled by a multiplexer (not shown) and nine buffers (also not shown) to a corresponding one of the nine lines of data (B) bus 144. Further, portion 112 is configured to be responsive to the state of the lowest order addressing signal developed on line 406 of bus 270 and operative to store the state of each of the signals developed on bus 144 and to develop the re-read addressing signals on bus 218 so as to have the stored states.

So that words are written into FIFO (B.fwdarw.A) buffer portion 114 eighteen bits at a time, nine-bit-to-eighteen-bit converter portion 116 stores each even (nine-bit) word until the corresponding odd (nine-bit) word arrives. To permit access to the word (nine-bits) stored in portion 116 (latch 420), portion 116 additionally includes the (read latch) circuitry illustrated in FIG. 8. The read latch circuitry includes a ten-bit latch 430 and ten, tri-state, buffers, represented by a tri-state buffer 432. Latch 430 is configured with nine of a set of ten data inputs each connected to the corresponding line of bus 422 and with the remaining (tenth) data input of the set of (ten) data inputs connected to a line 440 to receive a valid bit signal derived from the line 406 (FIG. 7) write data addressing signal. Further, latch 430 is configured with a clock input connected to a line 444 to receive an (active low) read signal and with a set of ten data outputs each connected to the corresponding line of a ten line bus 448. The ten, tri-state, buffers, represented by tri-state buffer 432 are configured with the data input of each of the ten buffers connected to a respective one of the ten lines of bus 448 and with the enable input of each of the ten buffers connected to read line 444. The nine, tri-state, buffers which are connected to the lines of bus 448 that correspond to the lines of bus 422 are configured with the output of each of the buffers connected to a respective one of the eight lower-order data bit lines of data (A) bus 140 and the corresponding parity bit line of bus 140. The remaining, tenth, tri-state, buffer is configured with the buffer output connected to the lowest-order line of the eight higher-order data bit lines of data (A) bus 140.

To save (for re-writing) the word (nine-bits) stored in latch 420 (of nine-bit-to-eighteen-bit converter portion 116) when FIFO (B.fwdarw.A) buffer portion 114 re-write pointer register 286 (FIG. 5) is loaded (saved), portion 116 additionally includes the (latch re-write) circuitry illustrated in FIG. 9. The latch re-write circuitry includes a latch 460 and a multiplexer 462. Latch 460 is configured with a set of nine data inputs each connected to a corresponding line of the nine lines of bus 422 and with a set of nine data outputs each connected to a corresponding line of a nine line bus 470. Multiplexer 462 is configured with a set of nine data outputs each coupled by a corresponding line of a nine line bus 474 to a corresponding input of the set of nine data inputs of latch 420. In addition, multiplexer 462 is configured with a first set of nine data inputs each connected to a corresponding line of the nine lines of bus 470. Further, multiplexer 462 is configured with a second set of nine data inputs each coupled by a corresponding one of nine buffers (not shown) to a corresponding one of the nine lines of data (B) bus 144.

Turning now to FIG. 10, FIFO buffer 100 is shown to additionally employ a multiplexer 500; another multiplexer 502; nine, tri-state, buffers, one represented by a buffer 504 and the other eight represented by a buffer 506; and nine buffers, represented by a buffer 508. Multiplexer 500 is configured with a first set of nine data inputs each coupled by a corresponding line of a nine line bus 510 to the corresponding data output of the set of nine data outputs of eighteen-bit-to-nine-bit multiplexer portion 112. Further, multiplexer 500 is configured with a second set of nine data inputs each coupled by a corresponding line of a nine line bus 512 to the output of a corresponding one of the nine, tri-state, buffers, represented by buffer 118. Finally, multiplexer 500 is configured with a set of nine data outputs connected, the highest order (parity-bit) output to a line 514 and the eight lower order (data-bit) outputs each to a corresponding line of an eight line bus 516, which are each connected both to a corresponding one of the set of eight data inputs of parity generator portion 122 and to the data input of a corresponding one of the tri-state buffers represented by buffer 506.

Multiplexer 502 is configured with a first data input connected to line 514; with a second data input coupled by a line 520 to the data output of parity generator portion 122; and with a data output coupled by a line 522 to the data input of tri-state buffer 504. Tri-state buffer 504 is configured with the data input connected to line 522 and with the output connected to the highest order (parity-bit) line of data (B) bus 144. The nine, tri-state, buffers represented by buffer 506 are configured each with the data input connected to the corresponding line of the eight line bus 516 and each with the output connected to the respective line of the eight lower order (data-bit) lines of data (B) bus 144. The nine buffers represented by buffer 508 are configured each with the data input connected to the corresponding line of the nine line data (B) bus 144. Further, the nine buffers represented by buffer 508 are configured each with the output coupled by a corresponding line of a nine line bus 526 to the data input of the corresponding one of the nine, tri-state, buffers represented by buffer 120; to the corresponding data input of the set of nine data inputs of nine-bit-to-eighteen-bit converter portion 116; and to the corresponding data input of the set of nine data inputs of parity checking portion 124. The data output of parity checking portion 124 is connected to a line 528.

FIFO buffer 100 is additionally shown (in FIG. 10) to employ a pair of OR gates 540 and 542, a pair of multiplexers 544 and 546, a pair of D-type flip-flops (registers) 548 and 750, and another OR gate 552. OR gate 540 is configured with a first gate input connected to a line 560; with a second gate input connected to line 528; and with the gate output connected to a line 562. Similarly, OR gate 542 is configured with a first gate input connected to a line 570; with a second gate input connected to line 528; and with the gate output connected to a line 572. Multiplexer 544 is configured with a first data input connected to line 560; with a second data input connected to line 562; and with a data output connected to a line 580. Similarly, multiplexer 546 is configured with a first data input connected to line 570; with a second data input connected to line 572; and with a data output connected to a line 582. Flip-flop 548 is configured with a data input connected to line 580 and with a data output connected to a line 586, upon which the flip-flop develops a read parity error signal. Similarly, flip-flop 550 is configured with a data input connected to line 582 and with a data output connected to a line 588, upon which the flip-flop develops a write parity error signal. Finally, OR gate 552 is configured with a first gate input connected to line 586; with a second gate input connected to line 588; and with the gate output connected to a line 592, upon which the gate develops a parity error signal.

In FIG. 11, A-port access control portion 126 is shown to include a pair of NAND gates, respectively designated 600 and 602. Gate 600 is configured with a (negated) input connected to line 152, to receive the externally developed (active low) data strobe (A) signal, with a (true (non-negated)) input connected to line 154, to receive the externally developed read/write signal, a (negated) input connected to line 150, to receive the externally developed (active low) chip selecting (A) signal, and with an output connected to a line 604, upon which the gate develops an (active low) read signal. Gate 602 is configured with a (negated) input connected to line 152, to receive the externally developed (active low) data strobe (A) signal, with a (negated) input connected to line 154, to receive the externally developed read/write signal, a (negated) input connected to line 150, to receive the externally developed (active low) chip selecting (A) signal, and with an output connected to a line 606, upon which the gate develops an (active low) write signal.

In addition, A-port access control portion 126 includes a status register, a command register, eight configuration registers, and associated circuitry (all not shown). The status register is configured with a set of sixteen data outputs each connected to the corresponding one of the sixteen lines of the eighteen line data (A) bus 140 upon which the sixteen data bit signals are developed. The command register is configured with a set of sixteen data inputs each connected to the corresponding one of the sixteen data bit signal lines of data (A) bus 140. The configuration registers are each configured with a set of sixteen data inputs each connected to the corresponding one of the sixteen data bit signal lines of data (A) bus 140 and with a set of sixteen data outputs each connected to the corresponding one of the sixteen data bit signal lines of the data (A) bus.

A two-line-to-four-line selector/multiplexer (not shown) is configured with a set of two selector inputs each connected to a respective one of the lines 156 and 158 and with a set of four outputs connected to enable (select) the various components of FIFO buffer 100 as illustrated in FIG. 12. More specifically, responsive to signals developed on lines 156 and 158 the states of which represent an address of zero, FIFO (B.fwdarw.A) buffer portion 110 (FIG. 1) is selected to be read from and FIFO (A.fwdarw.B) buffer portion 110 (FIG. 1) is selected to be written to; responsive to signals which represent an address of one, the tri-state buffers represented by buffer 120 are selected to directly read from data (B) bus 144 and the tri-state buffers represented by buffer 118 are selected to directly write to data (B) bus 144; responsive to signals which represent an address of two, one of the configuration registers is selected to be read from and written to; and responsive to signals which represent an address of three, the status register is selected to be read from and the command register is selected to be written to. Circuitry connected to various outputs of a set of sixteen data outputs of the command register is configured to select one of two sets of signals to drive a set of sixteen data inputs of the status register and to enable (select) one of the configuration registers.

In addition, the various outputs of the set of data outputs of the command register are connected as illustrated in FIG. 13. The two sets of signals selectively coupled to drive the status register are illustrated in FIG. 14. Circuitry connected to a set of sixteen data outputs of each of the configuration registers is configured as illustrated in FIG. 15. The flag polarities selected responsive to the configuration register number four signals are illustrated in FIG. 16; the function assignments of the configuration register number five signals are illustrated in FIG. 17; and, the function assignments of the configuration register number seven signals are illustrated in FIG. 18.

Programmable flag logic portion 128 includes four similar portions, one of which is shown In FIG. 19, generally designated by the number 800. Portion 800 includes an adder 810, an equal to comparator 812, and a two-input, OR gate 814. Adder 810 is configured with a set of ten inputs each connected to bus 220. The set of ten adder 810 inputs are not connected to a line of bus 220 upon which the highest order addressing signal is developed nor to a line of the bus (220) upon which the lowest order addressing signal is developed. Also, adder 810 is configured with a set of eight inputs each connected to the corresponding line of an eight line bus 820 to receive signals representing an empty offset developed by configuration register zero (FIG. 15). Further, adder 810 is configured with a set of ten outputs each connected to the corresponding line of a ten line bus 822. Equal to comparator 812 is configured with a first set of ten (A) inputs each connected to the corresponding line of bus 822 and with a second set of ten (B) inputs each connected to bus 206. The second set of ten comparator 812 (B) inputs are not connected to a line of bus 206 upon which the highest order addressing signal is developed. Further, comparator 812 is configured with an (A=B) equal output connected to a line 826 and a (A<B) less than output connected to a line 828. Gate 814 is configured with one of the two gate inputs connected to line 826; with the other one of the two gate inputs connected to line 828; and with the gate output connected to line 160.

Further, programmable flag logic portion 128 includes two similar portions, one of which is shown In FIG. 19, generally designated by the number 880. Portion 850 includes an equal to comparator 860, an exclusive OR gate 862, an inverter 864, and a pair of two-input, AND gates, respectively designated 866 and 868. Equal to comparator 860 is configured with a first set of ten (A) inputs each connected to bus 220. Again, the (first) set of ten comparator 860 (A) inputs are not connected to a line of bus 220 upon which the highest order addressing signal is developed nor to a line of the bus (220) upon which the lowest order addressing signal is developed. Also, comparator 860 is configured with a second set of ten (B) inputs each connected to bus 206. Again, the second set of ten comparator 860 (B) inputs are not connected to a line of bus 206 upon which the highest order addressing signal is developed. Further, comparator 860 is configured with an (A=B) equal output connected to a line 872. It is important to note that when comparator 860 develops on line 872 a signal which indicates that the numbers represented by the ten bus 220 and ten bus 206 signals are equal, the (A.fwdarw.B) FIFO buffer (110) may be either empty or full. Gates 862, 866, and 868 and inverter 864 are configured to remove the ambiguity. More specifically, gate 862 is configured with one of the two gate inputs connected to the highest order line of bus 220, designated 876; with the other one of the two gate inputs connected to the highest order line of bus 206, designated 878; and with the gate output connected to a line 880. Inverter 864 is configured with the inverter input connected to line 880 and with the inverter output connected to a line 884. Gate 866 is configured with one of the two gate inputs connected to line 872; with the other one of the two gate inputs connected to line 880; and with the gate output connected to a line 888. Gate 868 is configured with one of the two gate inputs connected to line 872; with the other one of the two gate inputs connected to line 884; and with the gate output connected to a line 890.

In FIG. 20 hand shake interface control portion 132 is shown to include a pair of two-input AND gates, respectively designated 900 and 902. AND gate 900 is configured with one of the gate inputs connected to a line 904, to receive a flag signal; with the other one of the gate inputs connected to line 178, to receive the (DMA) acknowledge signal; and a gate output connected to a line 906. AND gate 902 is configured with one of the gate inputs coupled to the output of gate 900 by line 906; with the other one of the gate inputs connected to line 174, to receive the (DMA) request signal and a gate output connected to a line 906. In addition, portion 132 is shown to include a D-type flip-flop 912 and a multiplexer 914. Flip-flop 912 is configured with the flip-flop clock input connected to line 174 and both the flip-flop data input and the flip-flop inverting data output connected to a line 916, to develop on line 916, a signal the frequency of which is one half that of the the clocking signal developed on line 174. Multiplexer 914 is configured with a first data input coupled to the data output of flip-flop 902 by line 914; with a second data input connected to line 174; with a select input connected to a line 918; and with a data output connected to a line 920, to selectively couple to line 918, either the clocking signal developed on line 176 or the half-frequency clocking signal developed by flip-flop 912 on line 916.

Further, hand shake interface control portion 132 is shown to include three, D-type, flip-flops, respectively designated 924, 926, and 928 and an exclusive-OR gate 930. To synchronize and delay the gate 902 developed signal and to develop a pulse (signal) one clocking cycle wide, the three flip-flops (924, 926, and 928) are connected in cascade with the data input of the first flip-flop (924) connected to line 908 and with the clock input of each of the flip-flops connected to line 920. Gate 930 is configured with one of the gate inputs connected to the data input of the last flip-flop (928); with the other one of the gate inputs connected to the inverting output of the last flip-flop; and with the gate output connected to a line 934.

Also, hand shake interface control portion 132 includes a six-stage shift register 940, configured with the data input coupled to the output of gate 930 by line 934 to develop further delayed pulses (signals). To select four of the various delayed pulses, portion 132, also, includes four, four-line-to-one-line multiplexers, respectively designated 950, 952, 954, and 956; four, two-input, AND gates, respectively designated 960, 962, 964, and 966; and two set-reset flip-flops, respectively designated 970 and 972. The multiplexers (950, 952, 954, and 956) are configured to select the one of the delayed pulses which is designated by signals developed by configuration register number five (FIGS. 14 and 16) and the following three delayed pulses. The AND gates (960, 962, 964, and 966) are configured to synchronize the multiplexed pulses, each with the line 176 clocking signal. Finally, the set reset flip-flops are configured, one (970) to be set by the first synchronized pulse and reset by the next (second) synchronized pulse, to develop the line 178 acknowledge signal; and, the other one (of the set-reset flip-flops) (972) to be set by the third synchronized pulse and reset by the last (fourth) synchronized pulse, to develop the line 170 data strobe (B) signal.

In the presently preferred embodiment, the various components of FIFO buffer 100 are all integrated into a single device using CMOS technology.

It is contemplated that after having read the preceding disclosure, certain alterations and modifications of the present invention will no doubt become apparent to those skilled in the art. It is therefor intended that the following claims be interpreted to cover all such alterations and modifications as fall within the true spirit and scope of the invention.