US 5,067,076 AGrant
Circuit Arrangement for Serial Data Transfer
Issue Date:1991-11-19
•11 Claims
•5 Drawing Sheets
Abstract
A circut arrangement for serial data transfer has a transmitting device with several bit-parallel input information units, a serial data transfer line and a receiving device via which the transferred data are correspondingly converted into bit-parallel output information units to drive control elements or logic circuits. The data to be transferred forms on the data transfer line a data word composed of a start pulse, several information units corresponding to the number of bit-parallel input information units forming a data block, and a defined data pause. By cascading several transmitting and receiving devices of the same kind, the number of bit-parallel, input and output information units can be altered, whereby the data word on the data transfer line is also altered by sequential joining of a corresponding number of data blocks, each having the same number of information units.
Metadata
Assignees
- Bayerische Motoren Werke Aktiengesellschaft
- Telefunken Electronic GmbH
Inventors
- Hartmut Hantsch
- Peter Thoma
- Josef Mahalek
Application Information
Application Number:US 6851797
Filing Date:1991-04-15
Priority Date:1985-12-20
Art Unit:231
Classifications
IPC:
H04J 308
Field of Search:
364340200;900825.06
Patent Drawings (5 sheets)
Description
Background of the Invention
The invention relates to an electronic circuit arrangement for serial data transfer with a transmitting device with several bit-parallel input information units, a serial data transfer line and a receiving device via which the transferred data are correspondingly converted into bit-parallel output information units to drive control elements or logic circuits, with the data to be transferred forming on the data transfer line a data word composed of a start pulse, several information units corresponding to the number of bit-parallel input information units forming a data block, and a defined data pause.
The conversion of bit-parallel signals into bit-serial signals and the reverse of this procedure are necessities in teleprocessing and teleprinter communications. This conversion is, however, also used by local computer networks if, for example, a terminal is installed in a different wing of the building than the central processing unit.
With microprocessors, separate peripheral components, so-called Universal Synchronous/Asynchronous Receiver/Transmitter (USART) components, can be used for this conversion. Software solutions are, however, also known wherein standard I/O ports are used.
In the transmission of, for example, teleprinter signals, the data to be transferred are defined by the ASCII Code (American Standard Code for Information Interchange) and the levels on the transmission lines are specially standardized, as, for example, in the case of the voltage interface RS 232 (CCITT recommendation V24).
For certain applications such as, for example, in motor-vehicle electronics, a microprocessor solution for serial data transfer involves too much expenditure if, for example, switch positions for various consumers are to be converted as parallel input information units into a serial data word in order to drive bit-parallel relays as control elements corresponding to the switch positions on the receiver side.
With microprocessors, the bit-parallel input information units are extended via the I/O ports with corresponding addressing and software-related programming expenditure.
Summary of the Invention
The object underlying the present invention is, therefore, to provide a circuit arrangement for conversion of bit-parallel data into bit-serial data and vice-versa, which requires little circuitry expenditure and no software expenditure, and wherein the number of bit-parallel input and output information units is alterable, if required.
This object is attained in accordance with the invention in that the number of bit-parallel input and output information units is alterable by cascading several transmitting and receiving devices of the same kind, whereby the data word is correspondingly altered on the data transfer line, and by sequential joining of a corresponding number of data blocks, each having the same number of information units per data block.
The essential advantages of the inventive circuit arrangement are that without programming expenditure and by means of transmitting and receiving devices of the same kind, with reference to motor-vehicle electronics, many control lines of a cable harness can be saved, the data transfer reliability is increased by multiple comparison, and an interruption in the data transfer line can be diagnosed.
Further advantageous embodiments of the invention are apparent from the subclaims.
An embodiment of the invention is illustrated in the drawings and is described in detail hereinafter.
Brief Description of the Drawings
FIG. 1 is a block circuit diagram of several cascaded transmitting and receiving devices for serial data transfer;
FIG. 2 shows the time-oriented route of a data word;
FIG. 3 is a block circuit diagram of the transmitting device;
FIG. 4 is a block circuit diagram of the receiving device;
FIG. 5 shows a circuit arrangement for supplying the transmitting device with feed voltage via the data transfer line;
FIG. 6 shows a pulse diagram for the decoding circuits; and
FIG. 7 shows the wiring of the receiving device.
Description of the Preferred Embodiments
The block circuit diagram shown in FIG. 1 is comprised of several transmitting devices S.sub.o, S.sub.1, . . . S.sub.n, of the same kind, a data transfer line U and several receiving devices E.sub.o, E.sub.1, . . . E.sub.n.
Each transmitting device S.sub.n comprises the same number of parallel input information units I.sub.En ; in the example shown there are eight, which according to the arrangement of the n transmitting devices S.sub.n are sequentially joined on the data transfer line U to form a data word as shown in FIG. 2. On the receiver side, the input information units I.sub.En are converted in the associated receiving devices E.sub.n into the same number of corresponding parallel output information units I.sub.An to drive relays as control elements (St) or logic circuits directly.
The data word in FIG. 2 consists of a start pulse SI with a pulse duration of, for example, 312 .mu.s followed by several data blocks DB in accordance with the number of bit-parallel input information units, followed by a defined data pause DP.
A data block consists of a synchronization bit with, for example 156 .mu.s, a following information bit of the same time duration, followed by two zero bits of 156 .mu.s duration each.
To this end, each transmitting device S is set up as shown in FIG. 3: Via an internal timing means or oscillator OSZ which can be influenced in its basic frequency by external wiring to terminal 0, a clock frequency f.sub.o is generated and is fed via one input of a clock signal selecting means or first OR gate OR.sub.1 to a frequency divider stage T. An external clock generator can be connected to the other input of OR gate OR.sub.1 via the clock input terminal TE, in particular, if several transmitting devices S.sub.n of the same kind are cascaded and the clock pulse for all transmitting devices S.sub.n arranged downstream is derived from only one transmitting device, the master, for example, S.sub.o. To this end, the oscillator inputs O.sub.n of these transmitting devices arranged downstream are connected to low potential and they then operate as so-called slaves in cooperation with the master.
The following explanations relate to an embodiment of the invention with two transmitting and receiving devices of the same kind.
The frequency divider stage T consists of a chain of fedback bistable multivibrator stages, for example, D flip-flops, so that various frequency divider conditions prevail, and the divided down frequency levels are linked to one another to form the data word via inventive decoding circuits such as start pulse decoder SID, cascade reset decoder KD, pulse pause decoder PPD, release decoder FD and scan pulse decoder SCD. In addition, the frequency divider stage T drives a delay circuit VZ.
The pulse diagram shown in FIG. 6 shows the output signals of the individual decoding circuits.
From the clock frequency f.sub.o of the oscillator output signal according to FIG. 6a the following output signals are generated via the decoding circuits:
scan pulses for inquiry of the switch positions according to FIGS. 6b to 6i;
pulse pause decoder pulse according to FIG. 6l;
start pulse according to FIG. 6k;
the input information units according to FIG. 6m illustrated by an example;
release pulses according to FIG. 6n;
the temporarily stored input information units according to FIG. 6o;
the actual data word as transmitted on the data transfer line U according to FIG. 6p;
the output signal of the cascade reset decoder KD according to FIG. 6q.
The individual decoded pulses interact as follows:
Each scan pulse SCI.sub.n of the scan pulse decoder SCD is fed to the base of an associated transistor T.sub.n in FIG. 3 whose emitter is connected to the interface of the input information pickup circuit. The terminal pin for this input information I.sub.En is also connected to reference potential via a Zener diode Zn poled in the blocking direction. The collectors of all transistors T.sub.n are interconnected and connected to the inverting input of a comparator K.sub.7. This input is also connected via a resistor R.sub.1 to an operating voltage supply unit U.sub.stab /POR.
The same operating voltage supply unit U.sub.stab /POR supplies a voltage divider comprised of the two resistors R.sub.2, R.sub.3 whose connection point is connected to the non-inverting input of the comparator stage K.sub.7.
If the input information I.sub.En shows a logic high level of more than, for example, 2.5 V when the scan pulse SCI.sub.n is present, this state is interpreted as open switch and the output signal of comparator K.sub.1 is logic zero or low potential. Conversely, if the input information is logic zero or is on low level, i.e., the switch is closed, the output signal of comparator K.sub.1 is logic 1 or high level.
The output signals of comparator stage K.sub.7 and release decoder FD are linked via an AND gate AND.sub.1 whose output signal is fed to an input of a second OR gate OR.sub.2 with several inputs. The output signals of the start pulse decoder SID and the pulse pause decoder PPD are fed to the further inputs of this OR gate. Via an amplifier V.sub.1 with the data input slave terminal DES, the data of the transmitting device arranged downstream, for example, S.sub.1, operated as slave, are fed to a further input of the OR gate OR.sub.2 whose output drives a push-pull end stage GT whose output signal represents the data word on the data transfer line U.
To transmit a data word W, the push-pull end stage GT is blocked immediately after application of the supply voltage U.sub.s via the output of the delay circuit VZ for a defined time which is determined by counting out a certain frequency level of the divider stage T.
The output signal of the cascade reset decoder KD is fed via a second amplifier circuit V.sub.2 to the terminal for the cascade reset output KRA.
Via a third amplifier V.sub.3 the signal of the basic frequency f.sub.o is fed to the terminal of the clock output TA.
The feed voltage supply unit U.sub.stab /POR is fed a supply voltage U.sub.s from which the stabilized voltage U.sub.Stab is derived.
The data word W shown in FIG. 6p begins with a start pulse of, for example, 312 .mu.s duration and is followed by eight data blocks DB of 624 .mu.s duration each, with each data block beginning with a synchronization bit of 156 .mu.s duration. It is followed by the scanned input information units I.sub.En, with a logic zero 0 meaning that the respective switch is closed. In the example of FIG. 6p, every second switch is, therefore, closed. The information bit is followed by two zero bits of 156 .mu.s each.
Via the master-slave programming stage MS, the frequency divider stages T and the pulse pause decoder PPD can be blocked at logic zero level at their cascade reset input KRE and released at a high level. The switch-over of these levels is effected in cascading operation in the master-slave mode by the cascade reset signal which is generated in the cascade reset decoder KD, is available at the cascade reset output KRA of the master and is fed to the transmitting device arranged downstream which is operated as slave.
A galvanically coupled electric connecting lead may be used as data transfer line U. An optoelectronic transfer line which consists on the transmitter side, for example, of a light-emitting diode LED driven by the push-pull end stage GT with the DA terminal of the data output of the transmitting device is, however, also possible. This light-emitting diode pulses the data word W galvanically separated, for example, via a glass fiber onto a phototransistor which is arranged on the receiver side and drives the receiving device connected downstream.
As seen in FIG. 4, a data input DE of each receiving device E is connected to the inverting input of a comparator stage K.sub.6 and to the cathode of a Zener diode ZD poled in the blocking direction, whose anode is connected to reference potential. The non-inverting input of this comparator is connected via the center tap of a voltage divider consisting of the resistors R5, R6 to a reference voltage.
The received data word W is brought digitally to a defined voltage level by the comparator K.sub.6 for further processing in the receiving device E and is fed to a start pulse recognition circuit STE, a scanning pulse generator stage AP and an input of an AND gate AND.sub.2. The AND gate AND.sub.2 is released when the start pulse has been detected in the start pulse recognition circuit STE and the other input of the AND gate AND.sub.2 is driven with this signal. The start pulse recognition circuit STE is driven by a divided down frequency level of a frequency divider stage T.sub.E of the receiving device E, in which after termination of the data pause a counting-out test is made with the first negative edge as to whether a minimum pulse duration which can be interpreted as start pulse is present. For this purpose, the frequency divider stage T.sub.E is driven by an internal timing means or oscillator circuit OSZ.sub.E with the terminal O.sub.E of the receiving device E whose basic frequency level f.sub.oE is approximately four times greater than that of the transmitting device. The oscillator OSZ.sub.E can be blocked or released via the output of clock signal selecting means or operating mode storage BA by its terminal, the programming pin PP, being connected to high or low potential.
The basic frequency f.sub.oE of the oscillator OSZ.sub.E is fed in addition to a clock output stage TA with the terminal TA.sub.E whose function is likewise determined by a corresponding control signal of the operating mode storage BA.
The frequency divider stage T.sub.E drives further component groups of the receiving device E with differently divided down frequency levels. These include the scanning pulse generator stage AP, a data end decoder DED which recognizes the end of the transferred data and informs a sequential control A of this point in time. The sequential control A is likewise driven by various frequency levels of the divider stage T.sub.E. The received data word is further processed via a first counting device Z.sub.1 which is driven via a further output signal of the operating mode storage Ba and counts out the first eight bits as master receiver or the second eight bits as slave receiver accordingly. In addition, the counter Z.sub.1 is fed the output signal of the AND gate AND.sub.2.
The output of the counter Z.sub.1 and the output of the scanning pulse generator stage AP drive a data decoding circuit DD whose control lines assume a distributor function by being connected to the clock inputs of a cache SPA connected downstream which consists of clock-controlled D flip-flops. The output signal of the AND gate AND.sub.2 which is identical to the data word is present at all data inputs of these D flip-flops. In this way, only the input information units I.sub.En are read successively at the rate of the scanning pulse into the flip-flops of the cache SPA and are, therefore, available as bit-parallel information. An identical temporary storage SPZ is connected downstream from the cache SPA.
The information units read into the cache SPA are compared with the contents of the temporary storage SPZ by a comparing unit K1 after recognition of the end of the data. In the case of equivalence, a second counter Z.sub.2 which operates as three-bit counter is counted one stage further. The comparison of the data contents of cache SPA and temporary storage SPZ is made in the comparator stage K.sub.1 which in the case of equivalence delivers a control signal to the counter Z.sub.2 and the sequential control A.
In the case of nonequivalence, the counter Z.sub.2 is reset via the sequential control A. The sequential control A also drives the storages SPA, SPZ and SPO and the comparators K.sub.1 and K.sub.2. After each comparison, the data are transferred from the cache SPA to the temporary storage SPZ. After four instances of equivalence, the contents of the temporary storage SPZ are compared with the contents of the output storage SPO connected downstream therefrom via a comparator stage K.sub.2. In the case of equivalence, the counter Z.sub.2 is reset since the input information units I.sub.En have not changed. In the case of nonequivalence, the input information units have changed and the following procedure takes place: The information units are taken over from the temporary storage SPZ into the output storage SPO and transferred to the driver stages connected downstream from the output storage SPO where they are available as bit-parallel output information units I.sub.An to drive control elements or logic circuits.
An output of the comparator K.sub.2 and a control line of the sequential control A are connected to a short-circuit recognition circuit KS which, after approximately 35 ms, following output of the data from the output storage SPO to the driver stages DS, tests these for approximately 10 ms for short-circuit behavior. To this end, the collector-emitter voltages of the active driver stages which as open collector transistors are provided with the terminals TRA and I.sub.An, respectively, are successively inquired four times via a comparator stage to ensure that there is no disturbance pulse present. If a short-circuit signal lasts for approximately 10 ms, the corresponding transistor is blocked. The blocked state remains stored and can only be cancelled again by the feed voltage supply unit U.sub.stab /POR being switched off and switched on again by a so-called "Power On Reset" component designed in the same way as that of the transmitting device.
A further protective measure for the driver stages is carried out by a safety test device PR which is driven by a frequency level of the frequency divider stage T.sub.E. This ensures that in the event of a break in electrical continuity or a short-circuit of the data transfer line U, all driver outputs are blocked after a defined time of approximately 50 ms. The disturbance can be indicated optically or acoustically if an input information unit of the transmitting device is constantly set to reference potential on a logic low level and the corresponding output is wired in accordance with FIG. 7.
Further component groups of the receiving circuit are three comparators K.sub.3, K.sub.4, K.sub.5 whose output signals act upon the driver stages.
If, for example, relays are driven by the output stages, they can be statically driven for approximately 120 ms after switch-on. During this time, the short-circuit testing of the outputs also takes place. The outputs can then be driven in a clocked manner with the basic frequency of the oscillator of the receiving circuit f.sub.oE to reduce the power dissipation in the driver stages. The operating mode for static or clocked driving of the outputs can be determined by the terminal pin T.sub.Aus with the non-inverting input of the comparator K.sub.5, and the driving is carried out statically when T.sub.Aus is connected to the supply voltage U.sub.s. Connection with reference potential results in clocked driving.
The non-inverting inputs of the comparators K.sub.4 and K.sub.3 are interconnected and lead out to the terminal LD. The output of the comparator K.sub.4 is connected to the output of the comparator K.sub.5. The input LD senses the voltage of the board network.
If the voltage level of the board voltage available at the terminal LD via a voltage divider is below a set reference voltage U.sub.Ref1 present at the inverting input of the comparator K.sub.4, the clocked driving of the relays is stopped via the comparator output of K.sub.4.
In the case of positive voltage peaks and high disturbance pulses, the driver transistors of the driver stages DS are brought into the conducting state via the output of the comparator K.sub.3 at whose inverting input the reference voltage U.sub.Ref2 is present. Also, in the case of positive over-voltages, each short-circuit inquiry is stopped.
Cascading (master-slave-operation) of the receiving device is discussed hereunder.
Master or slave is determined by wiring of the programming pin PP:
Master: PP to Us
Alone: PP open
Slave: PP to ground.
In the master operating mode, the oscillator OSZ.sub.E is wired at the pin O.sub.E to an RC element and the clock output TA.sub.E is active. If the receiver is operated alone, TA.sub.E is blocked.
In the slave operating mode, the oscillator is blocked and must be driven by the clock output of the master; the clock output of the slave is blocked.
Data recognition: The master recognizes the start bit and decodes the first 8 information bits. The slave likewise recognizes the start bit, but decodes the second 8 information bits.
With the exception of the synchronous clock control, the functions in master and slave are performed independently of one another.
FIG. 5 shows a way in which the transmitting device S.sub.o can be wired. The transmitting device is supplied with feed voltage via the data transfer line U. To this end, the resistor R.sub.p in FIG. 1 is replaced by the diode D.sub.p, and the cathode is connected with the terminal pin U.sub.S of the transmitting device S.sub.o and the anode directly with the data transfer line U.
The circuit blocks illustrated in FIGS. 3 and 4 are completely monolithically integratable.
Claims
What is claimed is:
1. Circuit arrangement for parallel-serial-parallel data transfer, comprising: a cascaded plurality of transmitting means, which are similar, coupled to a plurality of cascaded receiving means, which are similar, by a serial data transfer line, each of said transmitting means receiving a respective plurality of bit-parallel input information units and converting them into serial data in the form of a corresponding data block, and each of said receiving means correspondingly converting serial data into a plurality of bit-parallel output information units; said cascaded plurality of transmitting means being sequentially connected and producing serial data which is transferred on said serial data transfer line, said serial data being composed of data words, each data word having a start pulse, a plurality of information units corresponding to a predetermined number of bit-parallel input information units which together form a data block, and a defined data pause, wherein said predetermined number of bit-parallel input information units, which can be assembled into a data block, is determined by the number of cascaded transmitting and receiving means; each of said transmitting means having internal clock means for producing an internal timing signal, a clock input terminal for receiving an external timing signal, and first master-slave-programming means, responsive to a control signal, for causing said transmitting means to operate as either a transmitting means master stage or a transmitting means slave stage such that each data word on said data transfer line is formed by sequential joining of a corresponding number of data blocks each having the same number of information units, said first master-slave-programming means including first means for selecting one of said internal timing signal and said external timing signal, wherein each of said transmitting means operating as a transmitting means slave stage is responsive to said external timing signal, only one of said cascaded plurality of transmitting means being said transmitting means master stage and producing said control signal and said external timing signal for each said transmitting means slave stage, and said transmitting means master stage being responsive to said internal timing signal; each of said receiving means having internal clock means for producing an internal timing signal, a clock input terminal for receiving an external timing signal, and second master-slave-programming means for causing said second master-slave-programming means to operate as either a receiving means master stage or a receiving means slave stage, said second master-slave-programming means including second means for selecting as said timing signal one of said internal timing signal and said external timing signal, only one of said cascaded plurality of receiving means being said receiving means master stage and producing said external timing signal for each said receiving means slave stage each of said transmitting means further comprising first cascading circuit means operable in conjunction with said first master-slave-programming means for sequentially joining its corresponding data block to the ones of said data blocks on said data transfer line, said ones of said data blocks being respectively joined corresponding to the sequence in which said transmitting means are connected, said first cascading circuit means including an externally programmable storage means; and each of said receiving means further comprising second cascading circuit means operable in conjunction with said second master-slave-programming means for causing said data blocks to be respectively decoded by corresponding ones of said receiving means, said second cascading circuit means including a programmable storage device.
2. Circuit arrangement according to claim 1, wherein each said transmitting means further comprises a push-pull end stage means for causing data output from each said transmitting means to said data transfer line, each said push-pull stage means having current limitation.
3. Circuit arrangement according to claim 1, wherein each said receiving means further comprises a cache means for receiving and storing input information units having a received bit pattern, a temporary storage means connected to receive an output from said cache means for receiving and storing input information units having a received bit pattern, an output storage means for receiving and storing input information units having a received bit pattern, said output storage means being connected to receive output from said temporary storage means, a first comparator means for comparison of the contents of said cache means with the contents of said temporary storage means, a second comparator means for comparing the contents of said temporary storage means with the contents of said output storage means, and a counter means, whereby the transfer reliability of transmitted data on said data transfer line is increased with respect to disturbing influences by each of said receiving means inquiring the same input information units a plurality of times and subsequently comparing the received bit pattern in said first and second comparing means followed by (a) subsequent incrementing of said counter means in the case of determination of equivalence of the received bit pattern until a predetermined number is reached, and (b) resetting of said counter means and renewed inquiry of the input information units in the case of determination of non-equivalence of the received bit pattern.
4. Circuit arrangement according to claim 1, wherein each said receiving means further comprises a plurality of driver stages for producing bit-parallel output signals from input information units having a received bit pattern, and means for blocking each of said driver stages after a predetermined response time in event of a short-circuit as well as in event of a break in electrical continuity of said data transfer line.
5. Circuit arrangement according to claim 1, wherein said data transfer line includes an optoelectronic transmitting device on a transmitting side thereof for transmitting said serial data, and includes on a receiving side thereof a glass fiber and an optoelectronic receiving data for receiving said serial data.
6. Circuit arrangement according to claim 1, wherein an interruption in said serial data transfer line is indicated by acoustical means via an electroacoustic transducer unit, said interruption being indicated by one of the bit-parallel input information units which is constantly set to reference potential, and said electroacoustic transducer unit being connected in an associated bit-parallel driver stage.
7. Circuit arrangement according to claim 1, further comprising a feed voltage supply means connected to said data transfer line for supplying voltage to said transmitting means.
8. Circuit arrangement according to claim 1, further comprising a plurality of bit-parallel driving stages in each of said receiving means, and means for causing said driver stages to be in a conducting state in event of relatively high voltage peaks of a supply voltage which is supplied to said plurality of cascaded receiving means.
9. Circuit arrangement according to claim 1, further comprising a means for selectively driving said bit-parallel output information units in a clocked manner to minimize power dissipation.
10. Circuit arrangement according to claim 1, further comprising a plurality of bit-parallel driving stages in each said receiving means for driving said input information units having a received bit pattern, and a means for testing said bit-parallel driver stages for short-circuit behavior by successively inquiring the collector-emitter voltages of each of said bit-parallel driver stages a plurality of times within a predetermined time interval in which said bit-parallel driver stages are brought into a conducting state.
11. Circuit arrangement according to claim 1, wherein an interruption in said serial data transfer line is indicated by optical means via a light-emitting diode, said interruption being indicated by one of the bit-parallel input information units which is constantly set to reference potential, and said light-emitting diode being connected in an associated bit-parallel driver stage.