Voltage-Mode Quasi-Resonant Dc/Dc Converter

1. Field of the Invention

The present invention relates to a voltage-mode quasi-resonant dc/dc converter which performs frequency control and zero-voltage switching in a full-wave mode.

2. Description of the Related Art

The voltage-mode quasi-resonant dc/dc converter is expected to operate at high switching frequencies such as more than several megahertz, since switching stress and switching loss are relatively low in zero-voltage switching which the converter can perform.

The voltage-mode quasi-resonant converter comprises a resonant switch, in principle, consisting of a resonant inductor, a resonant capacitor, and an ideal switch which is parallel to the resonant capacitor. If the switch is implemented by a transistor and a reverse-parallel diode, the converter operates in a half-wave mode, where voltage oscillation across the resonant capacitor during off-time of the switch is unipolar. On the other hand, if the switch is implemented by a transistor with a series diode, the converter operates in a full-wave mode, where voltage oscillation across the resonant capacitor during off-time of the switch is bipolar.

It is known that a more desirable voltage-conversion ratio which is insensitive to load variations is obtained in the full-wave mode. However, in the full-wave mode implementation, the series diode is required to provide a reverse-voltage blocking capability. Consequently, energy stored in a parasitic capacitance of the transistor is trapped by the series diode during off-time and is dissipated internally after the switch turns on. Therefore, the full-wave mode has not been practical for high-frequency operation.

It is an object of the present invention to provide a voltage-mode quasi-resonant dc/dc converter which operates in full-wave mode at high switching frequencies.

In accordance with the present invention, there is provided a voltage-mode quasi-resonant converter comprising a resonant inductor, a resonant capacitance connected in series to the resonant inductor, a switching circuit connected in parallel to the resonant capacitor, a DC power source, an input inductor which stores current energy from the DC power source during on-time of the switching circuit and supplies stored current energy to the resonating resonant capacitor and the resonant inductor during off-time of the switching circuit, and a diode which supplies DC power from the resonating resonant capacitor and the resonant inductor to a load, wherein the switching circuit comprises a pair of MOSFET switches serially connected to each other so that their parasitic diodes are opposite to each other.

It is preferable that the pair of MOSFET switches are simultaneously turned on and turned off.

Alternatively, it is also preferable that the pair of MOSFET switches are controlled so that one of the MOSFET switches does not conduct during a period where voltage across the resonant capacitance is positive and another MOSFET switch does not conduct during a period where voltage across the resonant capacitance is negative.

FIG. 1 is a basic circuit diagram of a voltage-mode quasi-resonant boost converter;

FIG. 2 is a circuit diagram of a voltage-mode quasi-resonant boost converter wherein an ideal switch is implemented by a bipolar transistor;

FIG. 3 is a circuit diagram of a voltage-mode quasi-resonant boost converter wherein an ideal switch is implemented by a MOSFET;

FIGS. 4A, 4B and 4C are waveform diagrams showing waveforms in a conventional converter operating in full-wave mode;

FIG. 5 is a circuit diagram of a voltage-mode quasi-resonant boost converter, according to the first embodiment of the present invention;

FIGS. 6A, 6B, 6C, 6D and 6E showing waveforms in the converter shown in FIG. 5;

FIG. 7 is a circuit diagram of a voltage-mode quasi-resonant boost converter including a control circuit for an output voltage, according to the first embodiment of the present invention;

FIG. 8A, 8B, 8C and 8D are waveform diagrams showing waveforms in the converter shown in FIG. 7;

FIG. 9 is a circuit diagram of a voltage-mode quasi-resonant boost converter, according to the second embodiment of the present invention;

FIGS. 10A, 10B, 10C, 10D and 10E are waveform diagrams showing waveforms in the converter shown in FIG. 9;

FIG. 11 is a circuit diagram of a voltage-mode quasi-resonant boost converter, according to the third embodiment of the present invention;

FIG. 12 is a circuit diagram of a voltage-mode quasi-resonant buck converter, according to the present invention; and

FIG. 13 is a circuit diagram of a voltage-mode quasi-resonant buck/boost converter, according to the present invention.

Before describing the preferred embodiments according to the invention, examples of aforementioned related art are given with reference to the accompanying drawings.

FIG. 1 is a basic circuit diagram of a voltage-mode quasi-resonant boost converter.

An input inductor L.sub.i stores current energy from an input power source V.sub.in and an input capacitance C.sub.in during on-time of an ideal switch S. During off time of the ideal switch S, constant current from the input inductor L.sub.i is supplied to a resonant capacitor C.sub.r before a diode D.sub.1 turns on, and is supplied to resonating resonant capacitor C.sub.r and resonant inductor L.sub.r after the diode D.sub.1 turns on. Current flowing through the resonant inductor L.sub.r and the diode D.sub.1 is supplied to a load R.sub.L and a smoothing capacitor C.sub.F.

A duration of the off-time is settled to a constant value so as to perform zero voltage switching of the ideal switch. On the other hand, a duration of the on-time is controlled so that the output voltage V.sub.0 becomes equal to a desired value.

FIG. 2 is a circuit diagram of a voltage-mode quasi-resonant boost converter, wherein the ideal switch S is implemented by a bipolar transistor Q.sub.1 and a reverse blocking diode D.sub.2 in series with the transistor Q.sub.1. The reverse blocking diode D.sub.2 is provided to protect the transistor Q.sub.1 from breakdown by a reverse voltage applied in the off-time.

The converter shown in FIG. 2 can operate in full-wave mode owing to the reverse blocking diode D.sub.2.

FIG. 3 is a circuit diagram of another example of the voltage-mode quasi-resonant boost converter, wherein the ideal switch S is implemented by a MOSFET Q.sub.2 and a reverse blocking diode D.sub.3. The reverse blocking diode D.sub.3 is provided to prevent the MOSFET Q.sub.2 from conducting through a parasitic diode D.sub.s of the MOSFET Q.sub.2. If the reverse blocking diode D.sub.3 was absent, the converter could operate only in half-wave mode, because the voltage V.sub.cr across the resonant capacitor C.sub.r is clamped to a minimum value by the parasitic diode D.sub.s. In the half-wave mode, the voltage-conversion ratio V.sub.0 /V.sub.in becomes undesirably sensitive to variations in the load R.sub.L.

As mentioned above, the converter shown in FIG. 3 can also operate in full-wave mode owing to the reverse blocking diode D.sub.3. However, the converters shown in FIGS. 2 and 3 cannot operate at high switching frequencies in the full-wave mode because of large internal heat loss due to a parasitic capacitance in the transistor and the reverse blocking diode as explained below.

FIGS. 4A, 4B and 4C show waveforms of a driving signal q of the MOSFET Q.sub.2, voltage V.sub.cr across the resonant capacitor C.sub.r, and voltage V.sub.ds between drain and source terminals of the MOSFET Q.sub.2 of FIG. 3, respectively.

As shown in FIG. 4B, voltage V.sub.cr across the resonant capacitance C.sub.r becomes positive and then becomes negative. The parasitic capacitance C.sub.oss of the MOSFET Q.sub.2 is charged up to a positive peak value of the V.sub.cr, and a discharge of the parasitic capacitance is prevented by the diode D.sub.3. When the MOSFET Q.sub.2 turns on, energy corresponding to V.sub.DS denoted by A in FIG. 4C is internally dissipated and this leads to heat loss.

The amount of heat loss is increased as the switching frequency becomes higher. This situation also occurs in the converter shown in FIG. 2 due to a parasitic capacitance in the transistor Q.sub.1 and the diode D.sub.2. Therefore, the full-wave mode has not been practical for high-frequency operation, hitherto.

The preferred embodiment of the present invention will now be described with reference to the accompanying drawings.

FIG. 5 is a circuit diagram of a voltage-mode quasi-resonant boost converter according to a first embodiment of the present invention.

The ideal switch S is implemented by a pair of MOSFETs Q.sub.3 and Q.sub.4 serially connected to each other so that their parasitic diodes D.sub.3s and D.sub.4s are opposite to each other. The MOSFETs Q.sub.3 and Q.sub.4 are simultaneously turned on and off at an on-time and off-time of the converter, respectively, according to drive signals q.sub.3 and q.sub.4.

FIGS. 6A, 6B, 6C, 6D, and 6E show waveforms of the drive signals q.sub.3 and q.sub.4, voltage V.sub.cr across the resonant capacitance C.sub.r, drain-source voltage V.sub.DS of the MOSFET Q.sub.3, and drain-source voltage V.sub.DS of the MOSFET Q.sub.4, respectively.

While the voltage V.sub.cr is positive, the parasitic diode D.sub.4s of the MOSFET Q.sub.4 conducts, so that the parasitic capacitance C.sub.04 of the MOSFET Q.sub.4 is not charged and energy stored in the parasitic capacitance C.sub.03 of the MOSFET Q.sub.3 does not remain until the end of a period where the V.sub.cr is positive. While the voltage V.sub.cr is negative, the parasitic diode D.sub.3s of the MOSFET Q.sub.3 conducts, so that the parasitic capacitance C.sub.03 of the MOSFET Q.sub.3 is not charged and energy stored in the parasitic capacitance C.sub.04 of the MOSFET Q.sub.4 does not remain until the end of a period where the voltage V.sub.cr is negative.

Consequently, when the MOSFETs Q.sub.3 and Q.sub.4 turn on, energy remains in neither capacitance C.sub.03 nor C.sub.04. Therefore, internal dissipation of energy is avoided.

FIG. 7 is a circuit diagram of the voltage-mode quasi-resonant boost converter as shown in FIG. 5, but including a control circuit of the MOSFETs Q.sub.3 and Q.sub.4.

An amplifier circuit 1 amplifies an error voltage between the output voltage V.sub.0 or its division and reference voltage V.sub.ref. An output of the amplifier circuit 1 is applied to a Voltage to Frequency (V/F) converter circuit 2 which outputs a clock signal having a frequency proportional to an input voltage. A driving circuit 3 generates a driving signal having a cycle period equal to that of the clock signal. A driving transformer T generates voltages in response to the driving signal to simultaneously turn on and off the MOSFETs Q.sub.3 and Q.sub.4, and insulates the MOSFETs Q.sub.3 and Q.sub.4 from the driving circuit 3. A photo-coupler can be used instead of the driving transformer T.

FIGS. 8A, 8B, 8C, and 8D show waveforms of the clock signal, the driving signal, gate-source voltage of the MOSFET Q.sub.3 or Q.sub.4, and the voltage V.sub.cr across the resonant capacitance C.sub.r, respectively. A duration of an interval of the driving signal where the MOSFET switches Q.sub.3 and Q.sub.4 are opened (FIGS. 8B and 8C) is constant. On the other hand, a duration of another interval of the driving signal where the MOSFET switches Q.sub.3 and Q.sub.4 are closed is varied with the cycle period of the clock signal (FIG. 8A), i.e., is varied depending on the difference between the output voltage V.sub.0 and the reference voltage V.sub.ref. Consequently, zero-voltage switching in full-wave mode is performed as shown in FIG. 8D, and the output voltage V.sub.0 is controlled so as to be equal to V.sub.ref, by controlling the length of the on-time.

FIG. 9 is a circuit diagram of a voltage-mode quasi-resonant boost converter, according to a second embodiment of the present invention. The driving transformer T shown in FIG. 7 is replaced by two driving transformers T.sub.1 and T.sub.2, which are individually controlled by a driving circuit 4. Also, two photo-couplers can be used instead of the two driving transformers T.sub.1 and T.sub.2.

FIGS. 10A, 10B, 10C, 10D, and 10E show waveforms of the clock signal generated in the V/F converter circuit 2, one driving signal generated in the driving circuit 4, another driving signal generated in the driving circuit 4, gate-source voltage of the MOSFET Q.sub.3, and gate-source voltage of the MOSFET Q.sub.4, respectively. As shown in FIGS. 10B and 10C, the driving circuit 4 generates the driving signals at different timing from each other in response to the clock signal (FIG. 10A), and thus the MOSFETs Q.sub.3 and Q.sub.4 are controlled at different timing from each other. Only the MOSFET Q.sub.3 stops conducting during the period where the V.sub.cr becomes positive and only the MOSFET Q.sub.4 stops conducting during the period where the V.sub.cr becomes negative. Therefore, energy stored in the parasitic capacitance C.sub.03 and C.sub.04 is discharged through the other conducting MOSFET Q.sub.4 and Q.sub.3, respectively, and the parasitic capacitance of conducting MOSFET is not charged. Thus, in the converter shown in FIG. 9 energy stored in parasitic capacitances is easily released.

FIG. 11 is a circuit diagram of a voltage-mode quasi-resonant boost converter according to a third embodiment of the present invention. The resonant capacitance C.sub.r is implemented by two series capacitances C.sub.r1 and C.sub.r2 which are parasitic capacitances of the MOSFETs Q.sub.3 and Q.sub.4, respectively. This circuit construction is applicable if the resonance frequency is sufficiently high to utilize the parasitic capacitances as the resonance capacitance.

Though the above description is focused on a boost converter, the present invention may also be applied to a buck converter and a buck/boost converter. FIG. 12 is a circuit diagram of a voltage-mode quasi-resonant buck converter according to the present invention. FIG. 13 is a circuit diagram of a voltage-mode quasi-resonant buck/boost converter according to the present invention. The converters shown in FIGS. 12 and 13 can of course be modified according to the description with reference to FIGS. 7, 9 and 11.