Semiconductor Device With Reduced Crosstalk Between Lines

This invention relates to a semiconductor device and more particularly to a semiconductor IC device with reduced crosstalks between adjacent lines.

With the recent development in the manufacturing technologies of semiconductor devices, various components of integrated circuits are becoming miniaturized. As substrates become more densely populated with components, the distance between adjacent signal lines on the substrate is becoming smaller than ever. In a circuit with lines separated only by a small distance, the inter-line coupling capacitance becomes significantly large with respect to the ground capacitance of each line with respect to the substrate. Crosstalks between neighboring lines can cause variations in signal voltages, adversely affecting the safety margin of operation and causing errors in the operation. In circuits like semiconductor memory devices which are required to read and write extremely weak signals, in particular, the problem of crosstalks can seriously affect the reliability of the device.

It is therefore an object of the present invention to provide a semiconductor device which eliminates the aforementioned disadvantages by reducing the crosstalks between the lines of highly integrated semiconductor circuits.

The above and other objects of the present invention are achieved by providing a semiconductor IC device with a plurality of pairs of signal lines next to one another such that the lines having opposite phases during an active period are crossed in the middle. With the lines thus crossed, coupling capacitances may occur between lines but if the lines are considered as a whole, the two ends are at opposite phases because the lines are crossed in the middle. In other words, the effects of inter-line coupling capacitances are essentially offset and crosstalks can be eliminated from the circuit operations.

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings:

FIG. 1 is a wiring diagram showing the conventional arrangement of data input-output lines in a semiconductor device, and

FIG. 2 is a wiring diagram of a portion of data input-output lines of a semiconductor device embodying the present invention.

FIG. 3 is a wiring diagram of which FIG. 2 is a part.

Data input-output lines of a semiconductor memory device may be considered as an example which can be most easily affected by crosstalks between signal lines. With reference first to FIG. 1, lines D.sub.0 and D.sub.0 and lines D.sub.1 and D.sub.1 are mutually complementary data input-output lines of a semiconductor device of a conventional type. During an inactive period, they are all precharged to the level of V.sub.CC /2. Let us now suppose that the data lines D.sub.1 and D.sub.1 are selected in a write cycle and further that the line D.sub.1 is controlled to the logical "1" (such as V.sub.CC) while the line D.sub.1 is to the logical "0" (such as the ground potential). In this situation, the potentials of the lines D.sub.0 and D.sub.0 are affected through the coupling capacitances C.sub.1 and C.sub.2 respectively between the lines D.sub.0 and D.sub.1 and between the lines D.sub.1 and D.sub.0 as shown in FIG. 1. Regarding the lines D.sub.0 and D.sub.0 which were not selected, on the other hand, the very weak voltage obtained from a memory cell through bit lines must be differentially amplified. As stated above, however, the potentials of the lines D.sub.0 and D.sub.0 are influenced by the lines D.sub.1 and D.sub.1. If this influence becomes of the order of magnitude of the weak voltage received through the bit lines, differential amplification may fail and incorrect data may be rewritten in memory cells.

According to the present invention, the lines D.sub.1 and D.sub.1 are crossed with each other as shown in FIGS. 2 and 3 nearly at the center P of their lengths such that their adjacent relationships with the neighboring lines D.sub.0 and D.sub.0 are interchanged and that the coupling capacitance C.sub.1 between the lines D.sub.0 and D.sub.1, the capacitance C.sub.2 between the lines D.sub.0 and D.sub.1, the capacitance C.sub.3 between the lines D.sub.0 and D.sub.1 and the capacitance C.sub.4 between the lines D.sub.0 and D.sub.1 as shown in FIG. 2 are nearly equal. In other words, the lines D.sub.0 and D.sub.1 are next to each other on the left-hand side of the center position P but the line D.sub.0 is close to the line D.sub.1, for example, such that the capacitances C.sub.1 and C.sub.3 are nearly equal to each other. FIG. 3 shows how data input-output lines having a plurality of sets of complementary lines, each of the sets being structured as shown in FIG. 2, may be arranged.

Let us assume again that the lines D.sub.1 and D.sub.1 are selected in a write cycle and further that the line D.sub.1 is controlled to the logical ".sub.1 " (such as V.sub.CC) while the line D.sub.1 is to the logical "0" (such as the ground potential). As explained for the case of FIG. 1, the lines D.sub.0 and D.sub.0 are again affected by these controls of the lines D.sub.1 and D.sub.1 when a differential application becomes necessary for a weak voltage obtained from a memory cell through bit lines. With the lines crossed as shown in FIG. 2, however, the overall potentials of the lines D.sub.0 and D.sub.0 are substantially unaffected from the neighboring lines D.sub.1 and D.sub.1 because the effects of the coupling capacitances C.sub.1 (or C.sub.2) and C.sub.3 (or C.sub.4) are opposite in phase and nearly of the same magnitude. In other words, there is no error to be caused when data are rewritten through the lines D.sub.0 and D.sub.0. In summary, the present invention teaches a simple structural change by which crosstalks among the lines in an IC can be reduced. More highly integrated circuits can thus be realized and semiconductor devices with increased densities can be obtained without adversely affecting their reliability.