Measuring Device With Variable Color Display

In the drawings in which are shown the preferred embodiments of the invention,

FIG. 1 is a block diagram of a digital voltmeter with a variable color display.

FIG. 2 is a block diagram of a variable color digital voltmeter with an analog comparator.

FIG. 3 is a block diagram of a variable color digital voltmeter with a digital comparator.

FIG. 4 is a simplified schematic diagram of a digital voltmeter of the invention.

FIG. 5 is an exemplary detail of the display on which measured result is displayed in yellow color on green background.

FIG. 6 is a similar detail of the display on which measured result is displayed in yellow color on blue background.

FIG. 7 is a similar detail of the display on which measured result is displayed in yellow color on red background.

FIG. 8 is a simplified schematic diagram of one element of a variable color display device.

FIG. 9 is a cross-sectional view, taken along the line A--A in FIG. 6, revealing internal structure of a portion of a variable color display device.

FIG. 10 is a schematic diagram of an analog comparator for developing color control signals.

FIG. 11 is a schematic diagram of a digital comparator for developing color control signals.

FIG. 12 is a detail of 13-bit digital comparator in FIG. 11.

Throughout the drawings, like characters indicate like parts.

Referring now, more particularly, to the drawings, in FIG. 1 is shown a block diagram of a digital voltmeter utilizing a variable color display surrounded by a variable color background area. The digital voltmeter includes an A/D (analog to digital) converter 51, for converting an analog signal Vin applied to its input to digital data, and a display decoder 23 for causing the digital data to be displayed in a character format on a variable color display 11, in a manner well known to those skilled in the art. As will be more specifically pointed out subsequently, the display 11 includes variable color display areas arranged in a pattern and surrounded by an integral variable color background area. The invention resides in the addition of a segment color control 21 and a background color control 22 for illuminating display 11 in a color related to the measured value. The digital voltmeter of this invention can thus simultaneously indicate the measured value, in a character format, and its significance, in a color of the display. By way of an example, measured value that is considered to be normal may be indicated in green color, measured value that is slightly abnormal may be indicated in blue color, and measured value that is critical may be indicated in red color.

In FIG. 2 is shown a block diagram of a like digital voltmeter characterized by an analog comparator 81. The input of analog comparator 81 is coupled to the input of A/D converter 51 for comparing an input signal with predetermined limits and for developing comparison signals accordingly. The background color control 22 illuminates the background area of display 11 in accordance with the comparison signals.

In FIG. 3 is shown a block diagram of a like digital voltmeter characterized by a digital comparator 84. The input of digital comparator 84 is coupled to the output of A/D converter 51 for comparing the output digital data with predetermined limits and for developing comparison signals accordingly. The background color control 22 illuminates the background area of display 11 in accordance with the comparison signals.

In FIG. 4 is shown a schematic diagram of a digital voltmeter of this invention which includes a DVM (digital voltmeter) chip 53 for measuring input signal Vin applied, via a resistor 90a and decoupling capacitor 93a, to its HI (high) and LO (low) inputs, and for developing segment drive signals a, b, c, d, e, f, g, and DP (decimal point) for a 3 1/2 digit variable color display 41 on which measured values of the input signal may be indicated in a character format. Resistor 90b and capacitor 93b, coupled to input OSCILLATORS, are provided for selecting a suitable frequency of internal oscillators. An auto zero capacitor 93c tends to decrease noise. Integrating capacitor 93d and buffer resistor 90c provide desired voltage swing and linearity.

The first display element of the display 41 consists of a figure `1` and a minus sign. The second, third, and fourth display elements consist of seven segments arranged in a well known 7-segment font on which selected characters may be exhibited in variable color. In the second display element, the segments are designated as 31a, 31b, 31c, 31d, 31e, 31f, and 31g. Each display element has three color control inputs R (red), G (green), and B (blue) designated DISPL. Each display element is surrounded by a variable color background area, as will be more clearly pointed out subsequently. The background area of each display element also has three color control inputs R, G, and B designated as BACK. It is obvious from the illustration that the color control inputs of the display elements and background areas are respectively interconnected to form DISPLAY BUSES R, G, and B, for uniformly controlling color of all display elements, and BACKGROUND BUSES R, G, and B, for uniformly controlling color of the entire background area 32.

FIGS. 5 to 7 are examples of displayed measured values which consider exemplary low limit -1.5 and high limit 1.5 (in Volts or in any other suitable units). The invention resides in controlling the color of background area 32 to indicate whether the measured value lies within the bounds of the low and high limits, below the low limit, or above the high limit. FIG. 5 shows display 41 on which a measured value 1.234 is displayed on green background, to indicate that it lies within the bounds of the low and high limits. FIG. 6 shows display 41 on which a measured value -1.789 is displayed on blue background, to indicate that it lies below the low limit. FIG. 7 shows display 41 on which a measured value 1.956 is displayed on red background, to indicate that it lies above the high limit. To render the illustration less complex, all measured values are displayed in yellow color. It will be appreciated that the color of the display areas may be also varied, to enhance the presentation, as will be pointed out subsequently.

It is readily apparent that the method of displaying measured values shown in FIGS. 5 to 7 is extremely advantageous. Being completely surrounded by background area 32, all display elements in display 41 are effectively associated therewith. It is perfectly clear that the color of background area 32 relates to the values exhibited on the display elements within its boundaries, and not to values exhibited on display elements which may be located outside the boundaries.

Proceeding now to the detailed description, in FIG. 8 is shown a simplified schematic diagram of a one-character 7-segment variable color display element with variable color background. Each display segment of the display element includes a triad of closely adjacent LEDs: a red LED 1, green LED 2, and blue LED 3 which are adapted for producing a composite light signal of a variable color. To facilitate the illustration, the LEDs are designated by segment letters, e. g., red LED in the segment b is shown at 1b, green LED in the segment d is shown at 2d, and blue LED in the segment f is shown at 3f. The background area is comprised of background regions adjacent the display segments. Each background region includes a triad of closely adjacent LEDs: a red LED 4, green LED 5, and blue LED 6 which are adapted for producing a composite light signal of a variable color. As much as possible, the LEDs in the background regions are designated by letters of adjacent display segments.

The cathodes of all red, green, and blue display LED triads are interconnected in each display segment and electrically connected to respective inputs a, b, c, d, e, f, g, and DP (decimal point) which may be coupled to the outputs of DVM chip 53 viewed in FIG. 4. The anodes of all display red LEDs 1a, 1b, 1c, 1d, 1e, 1f, 1g, and 1i are commonly coupled to an electric path referred to as a display red bus 12. The anodes of all display green LEDs 2a, 2b, 2c, 2d, 2e, 2f, 2g, and 2i are commonly coupled to a like electric path referred to as a display green bus 13. The anodes of all display blue LEDs 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3i are commonly coupled to a like electric path referred to as a display blue bus 14.

In a similar fashion, the anodes of all background red LEDs 4a, 4b, 4c, 4d, 4e, 4f, 4g, and 4h are commonly coupled to an electric path referred to as a background red bus 16. The anodes of all background green LEDs 5a, 5b, 5c, 5d, 5e, 5f, 5g, and 5h are commonly coupled to a like electric path referred to as a background green bus 17. The anodes of all background blue LEDs 6a, 6b, 6c, 6d, 6e, 6f, 6g, and 6h are commonly coupled to a like electric path referred to as a background blue bus 18. The cathodes of all red, green, and blue LED triads in each background region are grounded.

The display red bus 12 is connected to the output of a non-inverting buffer 25a capable of sourcing sufficient current to illuminate all display red LEDs. The display green bus 13 is connected to the output of a like buffer 25b. The display blue bus 14 is connected to the output of a like buffer 25c. The background red bus 16 is connected to the output of a like buffer 25d. The background green bus 17 is connected to the output of a like buffer 25e. The background blue bus 18 is connected to the output of a like buffer 25f. It would be obvious to those skilled in the art that current limiting resistors may be connected in series with all LEDs in the circuit to constrain current flow. The operation of the display element shown in FIG. 4 will be now explained by the example of illuminating digit `1` in yellow color. To exhibit decimal number `1`, low voltage levels are applied to the inputs b and c, to illuminate equally designated segments, and high voltage levels are applied to all remaining inputs a, d, e, f, g, and DP, to extinguish all remaining segments.

To illuminate the display element in yellow color, the color control inputs R and G of the display buses are raised to a high logic level, while color control input B is maintained at a low logic level. As a result, the outputs of buffers 25a and 25b rise to a high logic level. The current flows from the output of buffer 25a, via display red bus 12 and red LED 1b, to the input b, and, via red LED 1c, to the input c. The current also flows from the output of buffer 25b, via display green bus 13 and green LED 2b, to the input b, and, via green LED 2c, to the input c. As a result of blending light signals of red and green colors in the segments b and c, the segments illuminate in substantially yellow color, creating a visual impression of a character `1`.

To illuminate the background area in green color, the color control input G of the background buses is raised to a high logic level, while the remaining color control inputs R and B are low. As a result, the output of buffer 25e rises to a high logic level. The current flows therefrom, via background green bus 17 and green LEDs 5a, 5b, 5c, 5d, 5e, 5f, 5g, and 5h in all background regions, to ground. The entire background area illuminates in green color.

To illuminate the background area in blue color, the color control input B of the background buses is raised to a high logic level, while the remaining color control inputs R and G are low. As a result, the output of buffer 25f rises to a high logic level. The current flows therefrom, via background blue bus 18 and blue LEDs 6a, 6b, 6c, 6d, 6e, 6f, 6g, and 6h in all background regions, to ground. The entire background area illuminates in blue color. To illuminate the background area in red color, the color control input R of the background buses is raised to a high logic level, while the remaining color control inputs G and B are low. As a result, the output of buffer 25d rises to a high logic level. The current flows therefrom, via background red bus 16 and red LEDs 4a, 4b, 4c, 4d, 4e, 4f, 4g, and 4h in all background regions, to ground. The entire background area illuminates in red color. An important consideration has been given to physical arrangement of the LEDs in the display areas and background regions, as illustrated in FIG. 9. Display red LED 1f, green LED 2f, and blue LED 3f are disposed on a support 10 in a display light blending cavity 8f and completely surrounded by a transparent light scattering material 34. When forwardly biased, LEDs 1f, 2f, and 3f emit light signals of red, green, and blue colors, respectively, which are blended by passing through light scattering material 34, acting to disperse the light signals, to form a composite light signal that emerges at the upper surface 35f. The color of the composite light signal may be controlled by varying the portions of red, green, and blue light signals. Display red LED 1b, green LED 2b, and blue LED 3b are similarly disposed in a display light blending cavity 8b and may be similarly activated.

In a similar fashion, background red LED 4g, green LED 5g, and blue LED 6g are disposed on support 10 in a background light blending cavity 9g and surrounded by transparent light scattering material 34. When forwardly biased, LEDs 4g, 5g, and 6g emit light signals of red, green, and blue colors, respectively, which are blended by passing through light scattering material 34 to form a composite light signal of a composite color that emerges at the upper surface 36g.

The display light blending cavities are optically separated from adjacent background light blending cavities by opaque walls. The display light blending cavity 8f is defined by walls 7a and 7b which have generally smooth inclined surfaces defining an obtuse angle with support 10. The walls 7b and 7c similarly define a background light blending cavity 9g therebetween. In a similar fashion, display light blending cavity 8b is defined by the 7c and 7d. The width of the top surfaces of the opaque walls is uniform and distinctly less than the width of the display areas or background regions so as to minimize the boundaries therebetween. The top surfaces of the opaque walls and top surfaces of the display areas and background regions are in the same plane to allow wide angle observation of the display device. Although the walls and light blending cavities are shown to be of certain shapes and dimensions, it is envisioned that they may be modified and rearranged.

In FIG. 10, the input signal Vin is applied to the interconnected inputs of two analog comparators 82a, 82b in a classic `window` comparator configuration. When the input voltage is lower than the low voltage limit Vlo, set by a potentiometer 92a, the output of analog comparator 82a drops to a low logic level, thereby forcing the output of an inverter 65a to rise to a high logic level to develop active color control signal B.

When the input voltage is higher than the high voltage limit Vhi, set by a potentiometer 92b, the output of analog comparator 82b drops to a low logic level, thereby forcing the output of an inverter 65b to rise to a high logic level to develop active color control signal R.

When the input voltage is between the low voltage limit Vlo and the high voltage limit Vhi, the outputs of analog comparators 82a, 82b rise to a high logic level (pull-up resistors 91a, 91b ensure correct high and low levels), thereby causing the output of AND gate 66 to rise to a high logic level to develop active color control signal G.

The outputs B, G, and R may be respectively coupled to like inputs B, G, and R of the background buses in FIG. 4 for illuminating background area 32 in a color in accordance with the range in which the measured voltage lies. Alternatively, the outputs B, G, and R may be respectively coupled to like inputs B, G, and R of the display buses in FIG. 4 for illuminating display areas 31a to 31f of all display elements in display 41 in a color in accordance with the range in which the measured voltage lies.

In FIG. 11 is shown a schematic diagram of a digital voltmeter with a digital comparator for developing color control signals. A DVM chip 54 measures an input signal Vin applied via a resistor 90f to its input IN and develops at its outputs A, B, C, and D of Units, Tens, Hundreds, and Thousand digital data corresponding to the value of the measured input signal. The input INIT CONV (initiate conversion) is tied to a high logic level for causing DVM chip 54 to measure continuously. The output digital data are simultaneously applied to the inputs A0 to A12 of a 13-bit digital comparator 85a and to the inputs A0 to A12 of a like digital comparator 85b. Two 8-bit latches 63a, having its outputs Q0 to Q7 respectively coupled to the inputs B0 to B7 of digital comparator 85a, and 63b, having its outputs QO to Q4 respectively coupled to the inputs B8 to B12 of digital comparator 85a, are provided for storing a digital representation of a low limit. Two like latches 63c, having its outputs QO to Q7 respectively coupled to the inputs BO to B7 of digital comparator 85b, and 63 d, having its outputs QO to Q4 respectively coupled to the inputs B8 to B12 of digital comparator 85b, are provided for storing a digital representation of a high limit. The digital comparator 85a compares the output digital data with the low limit and develops comparison signals accordingly. The digital comparator 85b compares the output digital data with the high limit and develops comparison signals accordingly. It would be obvious that measurement limits may be readily changed by clocking new data, representing new low limit and new high limit, into latches 63a to 63d (not shown).

When the output digital data of DVM chip 54 are less than the low limit, the output `<` of digital comparator 85a rises to a high logic level to generate an active color control signal B. When the output digital data are greater than the high limit, the output `>` of digital comparator 85b rises to a high logic level to generate an active color control signal R. When the output digital data are within the bounds of the low and high limits, one of the outputs `=` and `>` of digital comparator 85a, which are gated by an OR gate 60a, and one of the outputs `<` and `=` of digital comparator 85b, which are gated by an OR gate 60b, rise to a high logic level to force both inputs of an AND gate 66b to rise to a high logic level. As a consequence, the output of AND gate 66b rises to a high logic level to generate active color control signal G.

The comparison outputs B, G, and R may be respectively coupled to like inputs of the background buses in FIG. 4 for causing background area 32 of display 41 to illuminate either in blue color when the measured value is less than the low limit, in red color when the measured value is greater than the high limit, or in green color when the measured value is within the bounds of the low and high limits. Alternatively, the comparison outputs B, G, and R may be respectively coupled to like inputs B, G, and R of the display buses in FIG. 4 for causing display areas 31a to 31f of the display elements in display 41 to illuminate in a color in accordance with the relation of the measured value to the low limit and the high limit. It would be obvious that the color sequences could be readily changed by differently interconnecting the comparison outputs with the color control inputs.

FIG. 12 is a detail of one of 13-bit digital comparators 85a, 85b in FIG. 11. It will be appreciated that both digital comparators 85a, 85b may be substantially same. The comparison inputs `<`, `=`, and `>` of four 4-bit digital comparators 86a, 86b, 86c, and 86d are respectively coupled to like preceding outputs, in a manner well understood by those skilled in the art, to extend the comparison range to 13 bits.

The invention may be now briefly summarized. A measuring device was disclosed that comprises a device for measuring an input signal and a variable color display for indicating a measured value of the input signal in a character format. A comparator compares the measured value of the input signal with predetermined limits and develops comparison signals accordingly. Color control is provided for illuminating the display in a color in accordance with the comparison signals.

It would be obvious that that persons skilled in the art may resort to modifications in the construction of the preferred embodiments shown herein, without departing from the scope, as defined in the appended claims, and the spirit of the invention. It is contemplated that the principles of the invention may be also applied to numerous diverse types of display devices, such as liquid crystal devices, plasma devices, luminescent devices, cathode ray tube devices, and the like.