Gain Control Circuit for Amplifier Having Stepwise Variable Gain

The present invention relates to a gain-controlled amplifier circuit and, more particularly, to a gain control circuit for an amplifier having a stepwise variable gain.

A gain-controlled amplifier ciruit is basically constructed by an amplifier amplifying an input voltage with a variable gain, a detector detecting an amplitude of an output voltage produced by the amplifier and a control circuit comparing the detected amplitude of the output voltage with a reference voltage for controlling the gain of the amplifier in response to the comparison result such that the detected amplitude becomes equal to the reference voltage.

When an amplifier having a linearly variable gain is employed, the above-mentioned basic construction can control the amplifier such that the amplitude of the amplified output voltage becomes stably equal to a voltage corresponding to the reference voltage. However, if an amplifier varying its gain stepwise is employed, the amplified output voltage changes stepwise with a predetermined voltage step. Therefore, unless the detected amplitude of the output voltage is equal to the reference voltage, the gain continues to be changed. That is, the gain of the amplifier is controlled such that the detected amplitude of the output voltage repeats to become larger or smaller than the reference voltage. The amplitude of the amplified output voltage thereby does not become constant.

Therefore, an object of the present invention is to provide an improved gain control circuit for an amplifier having a stepwise variable gain.

Another object of the present invention is to provide a gain-controlled amplifier circuit in which an output amplitude of an amplifier having a stepwise variable gain is controlled to become stably constant.

A gain-controlled amplifier circuit according to the present invention comprises an amplifier having a stepwise variable gain and amplifying an input voltage with a gain designated by gain control data, a peak value holding circuit holding a peak value of an output voltage from the amplifier, a reference voltage generator generating first and second voltages having values different from each other, a comparator circuit comparing the peak value with the first and second reference voltages, and a control circuit producing the gain control data in accordance with the output from the comparator circuit to control the gain of the amplifier such that the peak value intervenes between the first and second reference voltages.

It is favorable that the difference voltage between the first and second reference voltages is larger than a voltage change of the peak value of the amplifier output voltage of when the gain of the amplifier is varied by one step but smaller than that when the gain is varied by two step. Thus, the gain of the amplifier is controlled such that the peak value of the output voltage thereof intervenes between the first and second reference voltages, so that the amplitude of the output voltage of the amplfier becomes substantially constant.

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawing, in which:

FIG. 1 is a block diagram representative of an embodiment of the present invention;

FIG. 2 is a timing chart representative of an operation of a circuit shown in FIG. 1;

FIG. 3 is a circuit diagram representative of an example of a variable gain amplifier shown in FIG. 1;

FIG. 4 is a circuit diagram representative of an example of a gain control circuit shown in FIG. 1;

FIG. 5 is a circuit diagram representative of an example of a peak value holding circuit shown in FIG. 1;

FIG. 6 is a block diagram representative of another embodiment of the present invention; and

FIG. 7 is a circuit diagram representative of a gain control circuit and a switch circuit shown in FIG. 6.

Referring to FIG. 1, an amplifier 2 has a plurality of gains, one of which is designated by gain control data 61 supplied from a gain control circuit 6. An input voltage V.sub.s is supplied to the amplifier 2 via an input terminal 1. The amplifier 2 amplifies the input voltage V.sub.s with the designated gain and produces an output voltage V.sub.o which is derived from an output terminal 8. The gain control circuit 6 responds to outputs of comparators 41 and 42, which are described later in detail, and changes the gain control data 61 such that the gain of the amplifier 2 is varied one step by one step. When the gain of the amplifier 2 is varied by one step, the amplitude of the output voltage V.sub.o thereof is changed by a predetermined voltage value, this predetermined value being represented by "V.sub.c " in the following description.

The output voltage V.sub.o of the amplifier 2 is further supplied to a peak value holding circuit 3 which detects and holds the peak value V.sub.p of the output voltage V.sub.o. The peak value V.sub.p is applied in common to the non-inverting input terminals (+) of first and second comparators 41 and 42, the inverting input terminals (-) of which are applied respectively with first and second reference voltages V.sub.RN and V.sub.RP from a reference voltage generator 5. These reference voltages V.sub.RN and V.sub.RP have values different from each other, and in this embodiment, the first reference voltage V.sub.RN is smaller than the second reference voltage V.sub.RP. Moreover, the voltage difference between the first and second reference voltages V.sub.RN and V.sub.RP is designed to be larger than the voltage value V.sub.c and be smaller than the twice value of V.sub.c. The peak value V.sub.p is thus compared with the first and second reference voltage V.sub.RN and V.sub.RP by the comparators 41 and 42. The gain control circuit 6 are supplied with the comparison result from the comparators 41 and 42 and controls the content of the gain control data 61. More specifically, when both of the outputs of the comparators 41 and 42 are at a low level, this means that the peak value V.sub.p is lower than the first reference voltage V.sub.RN, and therefore the control circuit 6 changes the gain control data 61 such that the gain of the amplifier 2 is incremented one step by one step in synchronism with a first clock signal .phi..sub.1. The output voltage V.sub.o of the amplifier 2 is thus increased stepwise by the value of V.sub.c. On the other hand, the fact that the comparator 41 produces a high level and the comparator 42 produces the low level, means that the peak value V.sub.p exists between the first and second reference voltages V.sub.RN and V.sub.RP, so that the gain control circuit 6 holds the current content of the gain control data 61. The amplified 2 thereby amplifies the input voltage V.sub.o with the fixed gain. Finally, when both of the outputs of the comparators 41 and 42 are at the high level, this means that the peak value V.sub.p is higher than the reference second reference voltage V.sub.RP, and hence the control circuit 6 changes the gain control data 61 such that the gain of the amplifier 2 is decremented one step by one step in synchronism with the clock signal .phi..sub.1. The output voltage V.sub.o is thus decreased stepwise by the value of V.sub.c.

Assuming now that, as shown in FIG. 2, the peak value V.sub.p is at a level of V.sub.P0 that is smaller than the first reference voltage V.sub.RN, the comparators 41 and 42 both produce the low level. Accordingly, the gain of the amplifier 2 is incremented by one step in response to the changed control data 61 in synchronism with the clock signal .phi..sub.1. The output voltage V.sub.o is thereby increased and the peak value V.sub.P takes a level V.sub.P01 that is higher than the level V.sub.P0 by the value V.sub.c. Since the level V.sub.P1 is smaller than the first reference voltage V.sub.RN, the gain control data 61 is further changed by the control circuit 3 to increment the gain of the amplifier 2 by one step. The peak value is thereby changed to a level V.sub.P02 that is higher than the level V.sub.P01 by the value of V.sub.c. Since this level V.sub.P02 intervenes between the first and second reference voltages V.sub.RN and V.sub.RP, as shown in FIG. 2, the first comparator 41 produces the high level, the second comparator 42 continues to produce the low level. Therefore, the gain control circuit 6 steps to change the gain control data 61 and holds the current content thereof. So long as the amplitude of the input voltage V.sub.S does not change, the amplifier 2 has the gain designated the hold content of the gain control data 61.

When the amplitude of the input voltage V.sub.S becomes large so that the peak value V.sub.P of the output voltage V.sub.0 responsive thereto takes a value V.sub.P1 that is higher than the second reference voltage V.sub.RP, as shown in FIG. 2, both of the comparators 41 and 42 produce the high level. Accordingly, the gain control circuit 6 changes the gain control data 61 such that the gain of the amplifier 2 is decremented by one step in synchronism with the clock signal .phi..sub.1. The peak value V.sub.P is thereby decreased to a level V.sub.P11 that is lower than the level V.sub.P1 by the value of V.sub.c. Since this level V.sub.P11 is still higher than the second reference voltage V.sub.RP, the gain of the amplifier 2 is further decremented by one step. As a result, the peak value V.sub.P is changed to a level V.sub.P12 existing between the first and second reference voltages V.sub.RN and V.sub.RP. The current content of the gain control data 61 is thereby held.

Thus, the gain of the amplifier 2 is controlled such that the peak value V.sub.P of the amplified output voltage V.sub.0 intervenes between the first and second reference voltages V.sub.RN and V.sub.RP, so that the amplitude of the output voltage V.sub.0 becomes substantially constant.

Turning to FIG. 3, the stepwise variable gain amplifier 2 shown in FIG. 1 is constructed by a switched capacitor circuit. More specifically, the input terminal 1 is connected via two switch circuits 202 and 203 to the inverting input terminal (-) of an operational amplifier 201 whose non-inverting input terminal (+) is connected to a ground terminal. Inserted in parallel between the switch circuits 202 and 203 are eight series-connection circuits of a pair of a switch and a capacitor, SW.sub.0 and C.sub.0, SW.sub.1 and C.sub.1, SW.sub.2 and C.sub.2, SW.sub.3 and C.sub.3, SW.sub.4 and C.sub.4, SW.sub.5 and C.sub.5, SW.sub.6 and C.sub.6, SW.sub.7 and C.sub.7. The gain control data 61 from the control circuit 6 consists of eight bits SC0 to SC7, and one or more of the switches SW.sub.0 to SW.sub.7 are turned ON in response to the contents SC0 to SC7 of the gain control data 61. The output of the operational amplifier 201 is connected to the terminal 8 and to the peak value holding circuit 3. Connected between the inverting input and output terminals of the operational amplifier 201 are a capacitor C.sub.9 and a series connection of two switch circuits 204 and 205 and a capacitor C.sub.8. Each of the switch circuits 202 to 205 has first and second contact nodes a and b and a reference node c connected to the ground and is controlled by a sampling clock signal .phi..sub.0. When the sampling clock signal .phi..sub.0 is at the high level, the second contact node b and the reference node c in the switch circuits 202 and 204 are connected to each other and the first contact node a and the reference node c in the switch circuits 203 and 205 are connected to each other. On the other hand, the first contact node a and the second contact note b in each of the switch circuits 202 to 205 are connected to each other when the clock .phi..sub.0 is at the low level. Assume that the total capacitance value of one or more capacitors C.sub.0 to C.sub.7 which are connected in parallel via the turned-ON switch or switches SW.sub.0 to SW.sub.7 is represented by "C.sub.IN " and the capacitance values of the capacitors C.sub.8 and C.sub.9 are represented by "C.sub.F1 " and "C.sub.F2 ", respectively. Further assume that the clock rate of the sampling clock signal .phi..sub.0 is represented by f.sub.s. The transfer function G(S) of the amplifier 2 shown in FIG. 3 is thereby represented by the following equation (1). ##EQU1##

Therefore, the gain of the amplifier 2 can be controlled stepwise by the content of the gain control data 61 and the capacitance value of each of the capacitors C.sub.0 to C.sub.8. The clock rate of the sampling clock .phi..sub.0 is designed to be extremely higher than that of the first clock signal .phi..sub.1.

Referring to FIG. 4, the gain control circuit 6 includes a five-bits up/down counter 604 which operates as a up counter when the low level is supplied to its a up/down control terminal U/D and increments the content thereof by one in synchronism with the clock pulse applied to a clock terminal CL. The counter 604 operates as a down counter when the high level is supplied to the terminal U/D and decrements the content by one in synchronism with the pulse applied to the terminal CL. The logic level at the terminal U/D is controlled by an OR gate 602 supplied with the outputs of the comparators 41 and 42. The supply of the pulse to the terminal CL is controlled by an AND gate 603 receiving the clock signal .phi..sub.1 and an output of an exclusive NOR gate (EX-NOR gate) 601 supplied with the outputs of the comparators 41 and 42. Therefore, when the peak value V.sub.P is smaller than the first reference value V.sub.RN, the counter 604 increments the content there of whenever the clock signal .phi..sub.1 is supplied. When the peak value V.sub.P is higher than the second reference value V.sub.RP , the counter 604 decrements the content thereof in response to the clock signal .phi..sub.1. When the peak value V.sub.P intervenes between the first and second reference voltages V.sub.RN and V.sub.RP, the clock signal .phi..sub.1 is inhibited to be applied to the terminal CL by the AND gate, so that the counter 604 holds the current content. In response to the content of the counter 604, i.e. five bits output data, a five-to-eight decoder 605 produces the gain control data 61 consisting of eight bits SC0 to SC7. In an initial state such as a power switching-on, a reset signal .phi..sub.R is supplied to a reset terminal R of the counter 604, so that the content of the counter 604 takes a value of "00000". This value is supplied to the decoder 605, and hence the gain control data 61 take such a content that the amplifier 2 has a center gain. In this state, if the counter 604 operates as the up counter, the content thereof is changed to be "00001".fwdarw."00010".fwdarw."00011".fwdarw."00100".fwdarw. . . . , every when the clock .phi..sub.1 is applied. On the other hand, when the counter operates as the down counter, the content thereof is changed to be "11111".fwdarw."11110".fwdarw."11101".fwdarw."11100".fwdarw. . . . , in response to the clock .phi..sub.1. As a result, the control circuit 6 changes the gain control data 61 such that the peak value V.sub.P becomes to intervene between the first and second reference voltages V.sub.RN and V.sub.RP and holds the current content of the gain control data 61 when the peak value V.sub.P exists between therebetween.

Turning to FIG. 5, the peak value holding circuit 3 includes an operational amplifier 303 having a non-inverting input terminal (+) supplied with the output voltage V.sub.0 via a switch 301. The output of the operational amplifier 303 is derived as the peak value V.sub.P and is directly fed back to its inverted input terminal (-) to operates as a voltage-follower. A capacitor 302 is connected between the terminal (+) and the ground and operates as a voltage holding capacitor. The voltage V.sub.0 is compared by a comparator 305 with the voltage across the capacitor 302, and the comparison result is supplied to a NOR gate 304 receiving the sampling clock signal .phi..sub.0 indicated in FIG. 3. The output of the NOR gate 304 controls the switch 301. Accordingly, the switch 301 is turned ON when the sampling clock signal is at the low level and when the output voltage V.sub.0 is higher than the previously sampled and held peak value V.sub.P. Thus, the circuit 3 detects and holds the peak value of the output voltage V.sub.0 from the amplifier 2. The reference voltage generator 5 can be constituted by a resistor-divided circuit, for example.

Since the gain control circuit 3 requires only the outputs of the comparators 41 and 42 just before the supply of the first clock signal .phi..sub.1, the comparator 41 and 42 can be replaced by one comparator. This circuit construction is shown in FIG. 6 as another embodiment of the present invention, in which the same constituents as those shown in FIG. 1 are denoted by like reference numerals to omit further description thereof. In FIG. 6, a comparator 4 is used for the first and second comparators 41 and 42 of FIG. 1. The non-inverting input terminal (+) of the comparator 4 is supplied with the peak value V.sub.P and the inverting input terminal (-) thereof is supplied alternately with the first and second reference voltages V.sub.RN and V.sub.RP through a switch circuit 51. The control circuit 6' at first latches the comparison output of the peak value V.sub.P and the first reference voltage V.sub.RN. The switch circuit 51 is thereafter changed over. The control circuit 6' thereby latches the comparison output of the peak value V.sub.P and the second reference voltage V.sub.RP. Therefore, the circuit as shown in FIG. 6 performs the same operation and effect as the circuit shown in FIG. 1.

Turning to FIG. 6, the control circuit 6' shown in FIG. 7 further includes two D-type flip-flops 606 and 607 in addition to the gates 601 to 603, counter 604 and decoder 605. The first flip-flop 606 latches the output of the comparator 4 in synchronism with a second clock signal .phi..sub.2, and the second flip-flop 607 latches the output of the comparator 4 in synchronism with a third clock signal .phi..sub.3. The switch circuit 51 is constituted of two switches 511 and 512 controlled by the second and third clock signals .phi..sub.2 and .phi..sub.3, respectively. As shown in FIG. 7, the second and third clock signals .phi..sub.2 and .phi..sub.3 are supplied just before the first clock signal .phi..sub.1 with the different phases from each other. Thus, one comparator 4, two flip-flops 606 and 607 and two switches 511 and 512 attains the same result as two comparators 41 and 42 shown in FIG. 1.

The present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. For example, the amplifier 2 can be constitute of a static-type amplifier, in which the capacitors C.sub.0 to C.sub.8 are replaced by the corresponding resistors. In this case, the switch circuits 202 to 205 and the capacitor C.sub.9 are not required.