Loop Communication System

This invention relates to a data communication network and more particularly to a multinode data communication network in which each node is coupled into two loops to ensure reliability of the network.

Loop or ring data communication networks are well known in the art. It is also well known to provide a double loop for such networks to ensure the availability of a communication path if failure in a node or in a portion of a path should occur. Such systems usually require constant checking of the system to detect for the occurrence of a fault and means for reconfiguring the two loops to form a single loop including a bypass around the fault, should one occur. Thus, under no fault operation, a double data path is provided. But when a fault occurs a local bypass about the fault is provided at the expense of throughput.

U.S. Pat. No. 4,553,233 issued Nov. 12, 1985, and assigned to International Standard Electric Corporation discloses one such system which requires no central processor but a relatively sophisticated node configuration. U.S. Pat. No. 4,542,496 issued Sept. 17, 1985, and assigned to Fujitzu Limited discloses a system of the type which does employ a central processor. In this latter system, the central processor is operative to check for the occurrence of a fault and to switch transmission to the alternative loop if such is available. If a fault occurs in both loops at once, the central processor connects the two loops at the nodes to either side of the fault in order to provide a transmission path.

Prior art systems of this type require fairly expensive node configurations, critical timing, and expensive wiring configurations which limit the use of such systems.

In accordance with the principle of this invention, a data communication network includes first and second loops with a plurality of nodes and a central processor. Local electrical closure between the two loops or communication continuity is provided at each node as a normal occurrence when no faults are detected. Thus, the nodes are connected to the two loops and operated in a manner different from the prior art teachings. A less expensive system which is relatively easy to install is provided.

In one illustrative system, a network includes nodes A, B, C - - - N and a central processor. The network is connected such that commands issued by the processor are sent to a designated node via the string of nodes between the central processor and the receiving node. Thus, a command to node C goes to node A, then to node B and then to node C which transmits the response in a reverse direction about the loop back to the central processor, If the path is broken, say between node A and node B, no node from B on can receive commands. On the other hand, each node includes two separate and independent I/O ports. Consequently, the network is adapted to provide an alternative forward path for both command and response under the control of the central processor. Specifically, the central processor is adapted to direct signals alternatively in a first and then a second direction around the loop, the response to each command being transmitted in a direction opposite to the initiating command.

The network may be adapted to permit polling of all nodes in one direction before reversal of the command direction.

FIG. 1 is a block diagram of a representative prior art loop communication system;

FIGS. 2 and 5 are block diagrams of a loop communication system in accordance with the principle of the invention;

FIGS. 3 and 4 are block diagrams of a node and a central processor in the network of FIG. 2; and

FIG. 6 is a block diagram of a loop communication system of FIG. 2 in which a fault occurs.

FIG. 1 is a block diagram of a prior art loop transmission system 10. The system 10 includes a central processor 11 operative as a supervisory station. The system 10 also includes a plurality of node stations. The number of node stations may vary. FIG. 1 illustrates two terminals represented by blocks 13 and 14. The stations are interconnected by first and second transmission lines 16 and 17.

The transmission lines interconnect the node stations and the central processor in first and second loop configurations. Transmissions moving counterclockwise and clockwise, respectively, are indicated by the arrows in the loops. Host computers 18 and 19 and end terminals 20 and 21 are connected to node stations 13 and 14, respectively, for initiating data or command inputs. The presence of more than two node stations is indicated by the broken portions of transmission lines between node 14 and central processor 11.

The prior art system 10 is operative under normal conditions such that one of the transmission lines, say 16, is used as an active route, i.e., a "0" route, and the other transmission line is used as a standby route, i.e., a "1" route, If only one of the transmission lines, say 16, becomes faulty at any point, the supervisory station 11 is adapted to detect the fault and switch the transmission line so that line 17 is used as the active route and communication between node stations can be maintained.

If a fault occurs in both transmission lines at once, the supervisory station 11 detects the faults from the condition of the signals on the line. In response to those signals, the supervisory station 11 sends loop commands on both lines. The commands are received by each node still reachable over the active portions of the two transmission lines. Each of such node stations responds to the loop back commands to establish a loop back route utilizing portions of the two transmission lines.

The supervisory station 11 also is adapted to send follow up commands to release the loop back routes and return the loop to normal operation. These follow up commands occur after a predetermined time. Each node for which the receiving condition on each transmission line is normal responds to release the loop back route. In each node station at which a fault is detected in one line, the loop back route is retained, Further operation utilizes portions of the two lines until the fault is repaired.

FIG. 2 shows a block diagram of a loop transmission system 22 in accordance with the present invention. As was the case with the system 10 of FIG. 1, the system 22 includes a central processor 23 and a plurality of node stations.

A plurality of representative node stations are represented by blocks 24A, 24B - - - 24N in FIG. 2. The presence of additional stations is indicated in FIG. 2 by broken lines 26 and 27, and lines 28 and 29. The broken line 26 through 29 are segments of transmission lines (with like designations) which link the node stations and the central processor 23. It is to be understood that the central processor 23 communicates receives as well as transmits, to the node stations in two directions (clockwise and counterclockwise) as is indicated by the arrows in lines 26-29. Each transmission line includes a twisted pair of lines to permit such operation.

In accordance with the principles of the present invention, the central processor 23 is adapted to alternate the direction in which commands are transmitted. All commands, once initiated, proceed from one node to the next consecutive node in the direction in which the transmission was initiated. But the response to the command is transmitted from the node which was the intended destination of the command back to the source in the direction opposite to the original direction of the command transmission.

If a transmission line is broken (i.e., a fault occurs between say node station 24A and node station 24B), no node stations beyond 24A can receive transmissions. But the system 22 provides for two independent directions of transmission from the central processor 23. Thus, another line is provided for both commands and responses. That is to say, if a command is retransmitted in the opposite direction during the next cycle of operation. During the following cycle, a path exists, free of faults, for a response the be communicated to the central processor. The system thus compensates for the occurrence of a fault by providing alternative communication paths in alternative communication directions. The occurrence of a fault thus results in the recommunication of a command and a response, both delayed one cycle of operation.

A cycle of operation need not be limited to including a single command and response. It may be defined as including two, three, or more commands and responses. For systems with relatively few nodes, a cycle of operation may include a period in which all nodes are polled. Reversal of the direction of command flow about the loop in this case occurs after all nodes are polled.

FIGS. 3 and 4 show circuit diagrams of an illustrative micronode and central processor organization, respectively. FIG. 3 shows a block 40 representing an illustrative micronode. The micronode has input/output ports 41-I and 41-O to the right of the block as viewed and 42-I and 42-O to the left. Any command sent by the central processor and received by a micronode at an input port (41-I or 42-I) is retransmitted by the micronode via the opposite output port (42-O or 41-O). This operation continues until the target micronode is reached.

The targeted micronode operates differently. When that micronode receives a message intended for it, it responds on the output port corresponding to the input port at which the message was received. In this manner, the response is returned, micronode by micronode in a direction around thee loop opposite to that in which the original command was directed. The response is ultimately applied to the output port associated with the input port of the central processor at which the command originated.

FIG. 4 shows a block 50 representing a central processor. Any comparable based computer, the IBM-XT or compatible computer is suitable as, for example, the Epson Equity II. Such a computer operating under MS-DOS defines an I-O pair commonly called a COM-port. The loop configuration of FIG. 4 requires two such COM-ports. Consequently, a central processor in accordance with the present invention also includes a means for defining such a second COM-port. An Intel 82C51 chip is suitable for this purpose. The COM ports are designated 51-I and 51-O and 52-I and 52-O in FIG. 4. The means for defining the second COM-port is designated 53.

The central processor also includes RAM memory 54 for storing data and transactions as well as an EPROM 55 for storing firmware for the operative system. The micronode 40 of FIG. 3 and the central processor 50 of FIG. 4 are interconnected into the loop network of FIG. 2 in a straightforward manner which becomes clear once it is understood that each arrow (i.e. 51-O of FIG. 5) represents a connection to a pair of wires (i.e., 28 and 29 exiting central processor 23 of FIG. 2.)

A reader 60 of FIG. 3, shown also in FIG. 2 connected to Node station N, is adapted to read magnetic stripe cards. The data on the card identifying the use is entered into the transaction buffer of that Node Station. A keyboard (not separately shown) is present at each node station and may be included as part of reader 60 for entering a personal identification number which is also stored in the transaction buffer of the node station. The node station includes sufficient intelligence to respond locally to inputs from a reader and keyboard independently of the control of the central processor. That is to say, a micronode, for example, is adapted to permit entry of a card bearer when proper identification is entered according to stored criteria which are familiar in the art. The central processor is adapted to update its database, interrogate the micronodes for an update on transaction and for changing entry criteria.

A communication protocol description for various commands and responses in a loop communication network in accordance with the principles of this invention is included herein below. A communication protocol also is included below. Several sample commands and responses consistent with that protocol are as follows:

The network can be seen to be operative to accept entry requests at a reader controlled independently by a micronode, consecutive transactions being stored in a micronode transaction buffer. The central processor transfers transaction information periodically. If a new transaction occurs before space is provided for it in a transaction buffer, the buffer is adapted to accept the new data and destroy the oldest data in the buffer.

It is to be remembered, that the central processor sends commands to a designated micronode in one direction about the loop. The response returns in the opposite direction. It is also to be remembered that the direction of command transmission reverses every cycle as does the direction of the response. It is clear that a command is transmitted from node to node to the target node via an input port and opposite output port of each node between the central processor and the target node. That is to say, during one cycle a command proceeds around the loop via input port 41-I and output port 42-O as shown in FIG. 3 of each micronode between the central processor and the target micronode. The response from the target micronode proceeds via input Port 42-I and output port 41-O of each micronode between the target micronode and the central processor.

During a next cycle of operation a command from the central processor is sent in the opposite direction about the loop from output port 52-O of FIG. 4. The command during this cycle is transmitted via input port 42-I and output port 41-O or each micronode between the central processor and the target micronode. The response returns via input port 41-I and 42-O of each micronode between the target micronode and the central processor, being applied to input port 52-I of the central processor as shown in FIG. 4. Central processor 50 is adapted to reverse the direction of commands and responses in consecutive cycles. EPROM 55 of FIG. 4 is coded to require such operation. FIG. 5 shows how the node and central processor ports are interconnected in the network of FIG. 2.

FIG. 6 illustrates a loop network with a fault in the loop between micronode Ba a d micronode C as indicated with and C designated 70. A command sent to micronode C via micronodes A and B during a given cycle will not arrive at C and an expected response from micronode C during that cycle will not be received. Instead, the central processor receives, for example, a string of zeroes which may be adapted to produce a "fault" report. During a next cycle, the same command is sent to micronode C via output port 52-O as shown in FIG. 4. No fault exists in the loop in this direction. Consequently, an acceptable response is received at input port 52-I of the central processor during the response phase of that next cycle. The presence of a fault in the line has merely delayed communication to the micronode at most by one cycle of operation.

On the average, any micronode will receive commands fifty percent of the time from one direction around the loop and fifty percent of the time in the other direction. If a fault occurs, still fifty percent of the time, no delay will be encountered. In only the other fifty percent will a one cycle delay occur. Thus, on the average, less than one cycle delay occurs when a fault is encountered.

Although, the present system is designed for access control where independent micronodes are adapted to control access even when communication with a central processor is interrupted, communication is sufficiently fast for the system to be adapted for alarm control as well. Each cycle of operation has a duration of at most, 33 milliseconds of only 330 milliseconds even if a cycle of operation is defined to include the polling of say ten nodes. Thus, the occurrence of a fault causes an average delay of less than 160 milliseconds which is sufficiently fast to be adapted for alarm control.

The communication protocol for computer-to-microNODE is structured for a system that consists of a number of interconnected intelligent microNODES operating in real time. It is based on a command/response mode, where a microNODE will not transmit a message unless it first receives one from the computer.

Up to 32 microNODEs may be connected to a computer in a 4-wire, 20-milliamp current loop ring arrangement, as links in a chain. Each end of the chain may be connected to a separate input/output port in the computer to provide a redundant communication path. A message may be initiated from either port and sent in either direction around the ring; however, communications must be only in one direction at a time. All messages arriving at one of the two microNODE input ports is moved to the opposite output and forwarded on to the next microNODE. In this manner, a message sent by the computer will travel the entire loop and return to the computer at its opposite input/output port.

A microNODE always initiates a response message to any incoming message that contains its address. A microNODE returns its response message to the computer on the output port associated with the input port receiving the computer message. This response is received by the next microNODE in the loop and is passed on until it is received by the computer. Therefore, the computer receives an answer to its message only at the initiating input/output port.

A message to and from the microNODE has the same structure of three sections: --HEADER, DATA, and CHECK SUM CHARACTERS.

The HEADER consists of the following six characters:

Start of text character--STX (02 Hex)

Destination address--two-characters

The encoder address is always 00.

The microNODE address is set by DIP switches in the microNODE. These are ODD numbers only; 1, 3, . . . 63.

Reader addresses are 01 to 64. Two readers may be connected to a microNODE. The first reader address is the same as the microNODE; the second reader address is the next higher EVEN address.

All microNODEs and readers also respond to the global address 99.

Source address--two characters

An encoder, reader and microNODE will only respond to messages from a source address of 99, the computer address.

Number of DATA characters to follow--one character

This character is N+20 (Hex)

where: N (Hex)=number of DATA characters to follow

If there are 15 DATA characters, N=F (Hex) the character is 2F (Hex) and prints as /(ASCII)

The DATA section of the message varies in length from a minimum of 2 characters to a maximum of 94 characters. The first two characters are always identifying command/response characters which indicate the meaning of the rest of the data to the receiving unit.

The CHECK SUM CHARACTERS are the last two characters of a message. The check sum is a single byte two's complement binary sum (ignoring carries) of all of the preceding message characters. This eight-bit check sum is read as two hexadecimal characters that are converted to two printable ASCII Check Sum Characters (0 through 9, A through F).

The message to unlock door (reader) number 3 should contain the following ASCII characters: (STX)0399"UD6E

Data is transmitted or received in 10-bits-per-ASCII-character asynchronous strings, at 1200 or 9600 Baud (selected by a jumper in the microNODE).

Each character has:

one start bit

eight data bits (8th bit, parity bit=0)

one stop bit.

All characters in the string, except the STX character, are printable ASCII characters.

A microNODE stores and operates on its own access control data base that has been down-loaded to it by the computer. All card transactions performed by the microNODE and all changes-of-state of monitored contacts are stored in a transaction buffer in the microNODE. The microNODE transmits these buffered transactions, one-per-command, in response to the following computer commands:

send microNODE ALARMS (MA)

READER TRANSACTIONS (RT)

or microNODE TRANSACTIONS (MT).

If the microNODE's transaction buffer is empty when it receives any of the above commands it responds with a "NO ACTIVITY TO REPORT" (ZZ) message.

Another way for the computer to check if the microNODE has anything to report is to send a "microNODE STATUS" (MS) request. One of the data characters in the microNODE response indicates the status of the transaction buffer (EMPTY, <75% full, >75% full, and FULL) and another character indicates whether an ALARM message is pending. ##SPC1##