Biphase Modulaton Circuit Having Continuous Phase Changes

The present invention relates to an automatic vehicle location system for use in data communication, and more particulary, in a data communication system using a biphase shift keying (hereinafter, referred to as "BPSK"), to a BPSK modulation circuit supplying a higher output power with band limitation.

Referring to FIGS. 1A and 1B, in a known BPSK modulation system, data from a data generator 10, as shown by a waveform A, and a carrier wave from a local oscillator 12, as shown by a waveform B, are mixed together at a mixer 14 to produce a modulation signal for transmission.

Such signal can not have a wide transmission bandwidth because the frequency band is allotted to many other data transmissions. In order to improve such a drawback, a BPSK modulation method to limit the bandwidth of a transmission signal as shown by a waveform A of FIG. 2B is to filter data produced from the data generator 10 through a waveform shaping filter 11 to obtain the waveform B of the data as shown in FIG. 2B. The output of the waveform shaping filter 11 and a carrier wave produced from the local oscillator 12, as shown by a waveform C of FIG. 2B are mixed together through the mixer 14 to produce a signal D modulated as shown in FIG. 2B. Though this modulated signal has a limited bandwith according to the waveform shaping characteristics, there occur damped amplitude portions. Hence, in order to transmit the modulated signal, it must be highly increased in output power. Furthermore, when the modulated signal passes a power amplifier, the damped amplitude portions are not amplified because they are below the minimum input power, so that the waveform is distorted and does not accurately transmit the data.

It is therefore an object of the present invention to provide a BPSK modulation circuit capable of achieving a higher transmission power and band limitation upon transmission, whereby a phase difference in such a BPSK modulation of a digital transmit data is changed in a short time interval by a continuous phase shift.

According to the present invention, a BPSK modulation circuit for a digital communication transmitter comprises a data generator, a timing circuit, a logic circuit, a phase shifter, a first double balanced mixer and a second double balanced mixer. The data generator generates data being supplied to the timing circuit and the logic circuit. The timing circuit delays the data from the data generator by timing the data in synchronism with a given pulse. The logic circuit generates a timing pulse whenever a logic level of the data of the data generator is inverted. A local oscillator generates a local oscillating frequency signal. A phase shifter shifts the local oscillating frequency signal with a phase difference of 90.degree.. A first double balanced mixer mixes the delayed signal from the timing circuit and the output from the phase shifter. A second double balanced mixer mixes the timing pulse from the logic circuit and the local oscillating frequency from the local oscillator. A signal mixer (synthesizing circuit) synthesizes the output signals of the first and second balanced mixers.

The present invention will now be described with reference to the drawings attached only by way of example.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:

FIG. 1A shows a circuit diagram of a BPSK modulation method;

FIG. 1B shows the operational waveforms of the parts of FIG. 1A;

FIG. 2A shows a circuit diagram of a BPSK modulation method wherein the frequency band is limited;

FIG. 2B shows the operational waveforms of the parts of FIG. 2A;

FIG. 3A shows a circuit diagram of the modulation method of the present invention;

FIGS. 3B and 3C show the operational waveforms of the parts of FIG. 3A;

FIGS. 4A, 4B and 4C show phase diagrams of mixer 18 of FIG. 3A.

Referring to FIG. 3A, a data generator 10 generates data being supplied to a timing circuit 11 and a logic circuit 13. The timing circuit 11 delays the data from the data generator by timing the data in synchronism with a given pulse. The logic circuit 13 generates a timing pulse whenever a logic level of the data from the data generator is inverted. A local oscillator 12 generates a local oscillating frequency signal. A phase shifter 16 shifts the local oscillating frequency signal with a phase difference of 90.degree.. A first double balanced mixer 14 mixes the delayed signal from the timing circuit 11 and the output from the phase shifter 16. A second double balanced mixer 15 mixes the timing pulse from the logic circuit 13 and the local oscillating frequency from the local oscillator 12. A signal mixer 18 synthesizes the output signals of the first and second balanced mixers.

The data from the data generator 10, as shown by a waveform A of FIG. 3B, is transmitted to the timing circuit 11 and the logic circuit 13. The timing circuit 11 delays the data from the data generator 10, by .tau./2, and outputs the delayed signal, as shown by a waveform B of FIG. 3B. The logic circuit 13 produces a pulse having the duration of .tau. whenever the data is inverted from 0 to 1 or vice versa. The local oscillator 12 supplies a local oscillating frequency to the phase shifter 16 and second double balanced mixer 15. The phase shifter 16 causes a signal to have a phase difference of 90.degree. with reference to another signal so as to produce a signal as shown by a waveform A of FIG. 3C, for example, if a signal is sin .omega.t , the another signal is caused to be cos .omega.t .

The signal as shown by a waveform A of FIG. 3C, produced by the phase shifter 16, and the signal as shown by a waveform B of FIG. 3B, produced by the timing circuit 11 are applied to the first double balanced mixer 1 to modulate the data delayed by .tau./2 into a 90.degree. phase-shifted signal so as to produce a signal as shown by a waveform C of FIG. 3C. The second double balanced mixer 15 modulates a signal as shown by a waveform C of FIG. 3B, produced by the logic circuit 13 in synchronism with a local oscillating frequency signal as shown by a waveform B of FIG. 3C produced by oscillator 12, so as to produce a signal as shown by a waveform D of FIG. 3C. The output signals of the first and second double balanced mixer 14 and 15 are mixed together through the signal mixer 18 to produce a signal as shown by a waveform E of FIG. 3C. In this case, considering the phase interval before the two signals synthesizing with respect to ABCDEFG in FIG. 4A, the phase retains the vlaue of 0 at A, as shown in FIG. 4B, then changed to 45.degree. and 135.degree. respectively at B and C in the period of .tau., finally retaining the value of 180.degree. at D. Successively, the phase is again changed through 135.degree. to 45.degree. during the interval EF finally to 0.degree. at G in the duration of .tau..

Consequently, the present invention is to provide a BPSK modulation circuit capable of achieving a higher transmission power and band limitation upon transmission, whereby a phase difference in such a BPSK modulation of a digital transmit data is changed in a short time interval by a continuous phase shift.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.