Vehicle Speed Control System for Motor Vehicle Having an Automatic Transmission Control System

A device for down-shifting the automatic transmission gear to decelerate the vehicle while the automatic speed control system is operating is shown in Japanese Laid-open Patent Application Publication No. SHO61-238531, dated Oct. 23, 1986. This down-shifting occurs to prevent increased velocity in combination with the closing of the throttle by the automatic throttle control system.

A device for down-shifting the automatic transmission gear when the throttle is at its maximum opening and the vehicle velocity is decreasing while the automatic speed control system is operating is shown in the Japanese Laid-open Patent Application Publication No. SHO60-1031, dated Jan. 7, 1985. This down-shifting occurs because of antihunting of the vehicle.

These devices are all intended to increase the comfort for vehicle occupants. However, when the automatic transmission control changes gears while the automatic speed control system is on, the speed stage may shift at the same time the automatic speed control starts. This can occur for example, when the switch for the automatic speed control is pushed. This may be uncomfortable, because the operator may not expect the gear change at the time the speed control is activated.

Further, if the automatic transmission becomes defective, a change of speed stage caused by movement of the throttle valve of the automatic speed control system may result in an unexpected and abrupt shift between speed stages, causing an unexpected shock to vehicle occupants.

When the automatic speed control system is controlling the vehicle velocity, both the avoidance of hunting and a relatively rapid return to the set vehicle velocity are necessary. Further, shocks resulting from shifts of the speed stage and operation of the throttle valve should be minimized.

It is an object of the present invention to maintain a comfortable ride for a vehicle having both an automatic transmission control system and an automatic speed control system.

It is a further object of the invention to decrease the delay time of the shift of the speed stage when the automatic speed control is activated to quickly reduce the present vehicle velocity to the set vehicle velocity.

It is a further object of the invention to establish an inhibition area for the shift of the speed stage when the automatic speed control is activated because of antihunting.

It is an another object of the invention to reduce the frequency of speed stage changes.

It is an another object of the invention to shift the speed stage of an automatic speed control according to the difference between the set vehicle velocity and the actual vehicle velocity.

It is still another object of the invention to inhibit undesired shifts of the speed stage of an automatic speed control system caused by movement of the throttle valve when the automatic transmission is subject to unexpected changes of gear.

It is another object of the invention to inhibit a concurrent shift of the speed stage at the time the automatic speed control system is activated.

Other and further objects of this invention will become obvious upon an understanding of the illustrative embodiment about to be described or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon practice of the invention.

FIG. 1 is an circuit diagram showing the electric control system for controlling operation of an automatic speed control system and an automatic transmission control system according to one embodiment of the present invention;

FIG. 2 is a flow chart showing a main routine for the microcomputer CPU in FIG. 1;

FIG. 3 is a flow chart showing a sub routine MODE CHANGE for the CPU;

FIG. 4 is a flow chart showing a sub routine MAP CHANGE for the CPU;

FIG. 5 is a flow chart showing a sub routine SHIFT JUDGMENT for the CPU;

FIG. 6 is a flow chart showing a sub routine LOCKUP DATA SET for the CPU;

FIGS. 7 through 9 are flow charts showing a sub routine SHIFT CHANGE for the CPU;

FIGS. 10 through 12 are flow charts showing a sub routine AUTOMATIC SPEED CONTROL for the CPU;

FIG. 13 is a flow chart showing a sub routine UP SHIFT PROHIBITION for the CPU;

FIG. 14 is a flow chart showing a sub routine TEMPORARY TIMER SET for the CPU;

FIG. 15 is a flow chart showing a sub routine SOLENOID ABNORMAL DETECTING for the CPU;

FIG. 16 is a flow chart showing a sub routine GET TRQ for the CPU;

FIG. 17 is a flow chart showing a sub routine GET TH for the CPU;

FIG. 18 is a flow chart showing a sub routine GET MAX TRQ for the CPU;

FIG. 19 is a flow chart showing a sub routine TIMER INTERRUPT for the CPU;

FIGS. 20, 21, 27, 28 and 29 are operational diagrams showing the operation of the timers of the CPU;

FIG. 22 is a table showing the timer data;

FIGS. 23 and 24 are graphs showing surveyed torques of a vehicle;

FIG. 25 is a table showing a torque diagram which is stored in the CPU;

FIG. 26 is a table showing a maximum torque diagram which is stored in the CPU;

FIGS. 30 through 33 are tables showing shift diagrams and lockup diagrams which are stored in the CPU;

FIG. 34 is a graph showing the operation of the automatic transmission control system;

FIG. 35 is a fragmentary flow chart showing a modified form of the sub routine AUTOMATIC SPEED CONTROL shown in FIG. 11;

FIG. 36 is a fragmentary flow chart showing a modified form of that sub routine SHIFT CHANGE shown in FIG. 7.

FIGS. 37 and 38 are tables showing variables, constants, timers and resistances of the CPU.

Referring to FIG. 1, there is shown an electric circuit of a vehicle speed control system for a motor vehicle having an automatic transmission control system (an automatic transmission control means) and an automatic speed control system (an automatic speed control means or a throttle opening control means). In this embodiment, the electrical control device is mainly comprised of a microcomputer CPU. The CPU has a microprocessor unit MPU (not shown), a programmable timer PTM (not shown), input ports P1 through P18, output ports P21 through P30, a random access memory RAM (not shown) and a read only memory ROM (not shown). The MPU has two accumulators A and B (not shown) and an index register X (not shown). The MPU executes a program stored in the ROM.

A battery BE is connected to a regulated voltage supply CON via an ignition switch IG. The battery BE is a battery established in the motor vehicle generally. The regulated voltage supply CON regulates the voltage of the battery BE to 5 volts. The microcomputer CPU, an input interface circuit lP and an output interface circuit OP are supplied with the 5 volts from the voltage supply CON.

This embodiment has two speed sensors. A speed sensor SP1 comprises a read switch for generating a frequency signal proportional to the rotational speed of a speedometer cable (not shown) by a permanent magnet (not shown) connected to the speedometer cable. The speed sensor SP1 is connected to the input port P1 of the CPU via an input interface comprising a diode D1, resistors R1, R2 and R3 and a transistor Q1. When the speed sensor SP1 is closed, the input port P1 changes to the "H" level. When the speed sensor SP1 is opened, the input port P1 changes to the "L" level.

A speed sensor SP2 comprises a read switch for generating a frequency signal proportional to the rotational speed of an output shaft (not shown) of the automatic transmission by a permanent magnet (not shown) connected to the output shaft. The speed sensor SP2 is connected to the input port P2 of the CPU via an input interface comprising resistors R4, R5, R6 and R7, and a transistor Q2. When the speed sensor SP2 is closed, the input port P2 changes to the "H" level. When the speed sensor SP2 is opened, the input port P2 changes to the "L" level.

A shift position switch SPS for detecting the position of a shift lever (not shown) comprises a neutral range switch SPS-N, a drive range switch SPS-D, a second speed range SPS-2 and a low speed range switch SPS-L. When the shift lever is positioned at the neutral range, the switch SPS-N is turned ON, and the switches SPS-D, SPS-2 and SPS-L are turned OFF. When the shift lever is positioned at the drive range, the reverse range or the parking range, the switch SPS-D is turned ON, and the switches SPS-N, SPS-2 and SPS-L are turned OFF. When the shift lever is positioned at the second range, the switch SPS-2 is turned ON, and the switches SPS-N, SPS-D and SPS-L are turned OFF. When the shift lever is positioned at the low speed range, the switch SPS-N is turned ON, and the switches SPS-N, SPS-D and SPS-2 are turned OFF. The switches SPS-N, SPS-D, SPS-2 and SPS-L are connected to the input ports P3, P4, and P5 of CPU, respectively, via input interfaces comprising resistors R8, R9 and R10, and buffers DR1, DR2 and DR3. When the switches SPS-N, SPS-2 and SPS-L are turned ON, the ports P3, P4 and P5 are changed to the "H" level, respectively. When the switches SPS-N, SPS-2 and SPS-L are turned OFF, the input ports P3, P4 and P5 are changed to the "L", respectively.

A mode switch MS for setting the mode in the vehicle speed control to an economy mode, a power mode or an auto drive mode is comprised of an economy mode switch MS-E, a power mode switch MS-P and an auto drive mode switch MS-A. In the economy mode, the economy mode switch MS-E is turned ON, and the power mode switch MS-P and the auto drive mode switch MS-A are turned OFF. In the power mode, the power mode switch MS-P is turned ON, and the economy mode switch MS-E and the auto drive mode switch MS-A are turned OFF. In the auto drive mode, the auto drive mode switch MS-A is turned ON, and the economy mode switch MS-E and the power mode swtich MS-P are turned OFF. The power mode switch MS-P and the auto drive mode switch MS-A are connected to the input ports P6 and P7 of the CPU, respectively, via input interfaces comprising resistors R11, R12, R13 and R14, and buffers DR4 and DR5. When the power mode switch MS-P is turned ON or OFF, the input port P6 is changed to the "H" level or the "L" level, respectively. When the auto drive mode switch MS-A is turned ON or OFF, the input port P7 is changed to the "H" lever or the "L" level, respectively.

A throttle opening sensor SS is for detecting the opening degree of the throttle valve (not shown) and comprises three contacts L1, L2 and L3 for dividing the throttle opening in to eight stages TH0 through TH7 and a contact IDL for detecting the engine idling condition. The relationship between the throttle opening THO through TH7 and and the states of contacts L1, L2 and L3 is as follows:

The contacts L1, L2 and L3 are connected to the input ports P8, P9 and P10 of the CPU, respectively, via input interfaces comprising resistors R15, R16, R17, R18, R19 and R20, and buffers DR6, DR7 and DR8. When the contacts L1, L2 and L3 are turned ON, the input ports P8, P9 and P10 are changed to the "L" level. When the contacts L1, L2 and L3 are turned OFF, the input ports P8, P9 and P10 are changed to the "H" level. The contact IDL is connected to the input port P11 of the CPU via an input interface comprising a diode D2, resistors R21, R22 and R23, and transistor Q3. When the contact IDL is turned ON, the input port P11 is changed to the "H" level. When the contact IDL is turned OFF, the input P11 is changed to "L" level.

A brake lamp BL is connected to the battery BE via a brake switch BS and a fuse FU. A line between fuse FU and the brake switch BS is connected to the input port P12 of the CPU via an input interface comprising resistors R24, R25 and R26, and a transistor Q4. When the fuse FU electrically connects between the battery BE and the brake switch BS, the input port P12 is changed to the "L" level. When the fuse FU melts, the input port P12 is changed to the "H" level. A line between the brake switch BS and the brake lamp BL is connected to the input port P13 of the CPU via an input interface comprising resistors R27, R28 and R29, and a transistor Q5. When the fuse FU is normal and the brake switch BS is turned ON, the input port P13 is changed to "L" level. When the fuse FU melts or the brake switch BS is turned OFF, the input port P13 is changed to "H" level.

A parking brake switch RK is turned ON when a parking brake (not shown) is operated. A set switch SP and resume switch RS for the vehicle speed control system are each comprised of a push button type switch wherein the switch is turned ON when the switch is pushed and is turned OFF when the switch is not pushed. A vacuum switch VS is for detecting vacuum in a surge tank (not shown). Such vacuum is required to operate the vehicle speed control system. The vacuum switch VS is turned ON when the vacuum pressure is higher than a preset value (In this case the vacuum pressure approaches atmospheric pressure). The parking brake switch PK, the set switch SP, the resume switch RS and the vacuum switch VS are connected to the input ports P14, P15, P16 and P17 of the CPU, respectively, via input interfaces comprising diodes D3, D4, D5 and D6, resistors R31, R34, R37 and R40, and transistors Q6, Q7, Q8 and Q9. When each of switches PK, SP, RS and VS is tuned ON, the input ports P14, P15, P16 and P17 are changed to the "H" level, respectively. When each of switches PK, SP, RS and VS is turned OFF, the input ports P14, P15, P16 and P17 are changed to the "L" level.

A main switch ADS for the vehicle speed control has an ON contact and an OFF contact. The ON contact is connected to the input port P18 of the CPU via an input interface comprising a diode D7, a resistor R43 and a transistor Q10. When the main switch is turned ON, the input port P18 is changed to the "H" level. When the main switch is turned OFF, the input port P18 is changed to the "L" level.

An actuator ACT1 for the automatic transmission comprises shift solenoids SL1 and SL2 and lockup solonoid SL3. The shift solenoids are for shifting of automatic transmission gearing. The relationship between the shift solenoids SL1 and SL2 with respect to the times they are electrically energized and electrically deenergized and the condition of the automatic transmission gearing are as follows:

The lockup solenoid SL3 is for controlling a lockup clutch (not shown) for accomplishing direct engagement an output shaft of an engine (not shown) with an input shaft of a torque converter (not shown). When the lockup solenoid SL3 is energized, the lockup clutch is engaged and therefore the lockup operation is accomplished. When the lockup solenoid SL3 is deenergized, the lockup clutch is disengaged and therefore the lockup operation is released. The solenoids SL1, SL2 and SL3 are operated in accordance with the condition of the output ports P21, P23 and P25 of the CPU respectively. A buffer DR11, a transistor Q21 and a diode D11 comprise an output interface for the shift solenoid SL1. When the output port P21 is changed to the "H" level, the solenoid SL1 is deenergized. When the output port P21 is changed to the "L" level, the solenoid SL1 is energized. A buffer DR12 and resistors R51 and R54 comprise a fail detecting circuit for the solenoid SL1. The solenoid SL1 is connected to the input port P22 via the fail detecting circuit. When the wire of the solenoid or the wire between the output interface and the solenoid is cut or broken, the input port P22 is changed to the "H" level. When the wire between the output interface and the solenoid SL1 is short-circuited to ground, the port P22 is changed to the "L" level. A buffer DR13, a transistor Q22 and a diode D12 comprise an output interface of the solenoid SL2. A buffer DR13 and resistors R52 and R55 comprise a fail detecting circuit for the solenoid SL2. A buffer DR15, a transistor Q23 and a diode D13 comprise an output interface for the solenoid SL3. A buffer DR16 and resistors R53 and R56 comprise a fail detecting circuit for the solenoid SL3. When the output port P23 is changed to the "H" level, the solenoid SL2 is deenergized. When the output port P23 is changed to the "L" level, the solenoid SL2 is energized. When the wire of the solenoid SL2 or the wire between the output interface of the solenoid SL2 and the solenoid SL2 is cut or broken, the input port P24 is changed to the "H" level. When the wire between the output interface of the solenoid SL2 and the solenoid SL2 is short-circuited to ground, the port P24 is changed to the "L" level. When the output port P25 is changed to the "H" level, the solenoid SL3 is deenergized. When the output port P25 is changed to the "L" level, the solenoid SL3 is energized. When the wire of the solenoid SL3 or the wire between the output interface of the solenoid SL3 and the solenoid SL3 is cut or broken, the input port P26 is changed to the "H" level. When the wire between the output interface of the solenoid SL3 and the solenoid SL3 is short-circuited to ground, the port P26 is changed to the "L" level.

An actuator ACT2 for the vehicle speed control comprises a release valve RV, a control valve CV, a vacuum pump VP, the surge tank (not shown) and a vacuum actuator (not shown). The vacuum pump VP operates as a vacuum source. The vacuum pump VP comprises a motor M. When the motor M rotates, a vacuum is generated. The vacuum generated by the vacuum pump VP is stored in the surge tank. The surge tank is connected to the vacuum actuator via release valve RV and control valve CV. The control valve CV communicates between the surge tank and the release valve RV when the control valve CV is energized. On the other hand, the control valve CV disconnects from the surge tank to release the vacuum to atmosphere via the release valve RV when the control valve CV is deenergized. The release valve RV communicates between the control valve CV and the vacuum actuator when the release valve RV is energized. On the other hand, the release valve RV releases atmosphere to the vacuum actuator when the release valve RV is deenergized. The control valve CV and the release valve RV operate in accordance with the condition of the output ports P27, P28 and P29 of the CPU. One end of the release valve RV is connected to the output port P27 via an output interface comprising a buffer DR17 and a transistor Q24. One end of the control valve CV is connected to the output port P28 via an output interface comprising a buffer DR18 and a transistor Q25. The other end of the release valve RV and the control valve CV is connected to the output port P29 via an output interface comprising a buffer DR19 and a transistor Q26. When the output ports P27 and P29 are changed to the "L" level at the same time, the release valve RV is energized. When the output ports P28 and P29 are changed to the "L" level at the same time, the control valve CV is energized. However, when the output port P27 is changed to the "H" level, the release valve RV is deenergized. When the output port P28 is changed to the "H" level, the control valve is deenergized. When the output port P29 is changed to the "H" level, the release valve RV and the control valve CV are deenergized together. The motor M of the vacuum pump VP is energized by the condition of the output port P30 of the CPU. The output port P30 is connected to the motor M via an output interface comprising a buffer DR20 and a transistor Q27. When the output port P30 is changed to the "L" level, the motor M is rotated, and when the output port P30 is changed to the "H" level, the motor M is not rotated.

Stored in the read only memory ROM of the microcomputer CPU are ECT shift data, ECT lockup data, ECT-A/D shift data, ECT-A/D lockup data, ECT up timer data, ECT down timer data, ECT-A/D up timer data, ECT-A/D down timer data, torque data, maximum torque data, and instructions for the vehicle speed control system. The ECT shift date are data of an ECT shift diagram as shown in FIG. 31 for shifting the speed stage of the automatic transmission when the automatic speed control system is not operating. The ECT-A/D shift data are data of an ECT-A/D shift diagram as shown in FIG. 32 for shifting the speed stage of the automatic transmission when the automatic speed control is operating. The ECT lockup data are data of an ECT lockup diagram as shown in FIG. 31 for operating the lockup clutch of the automatic transmission when the automatic speed control system is not operating. The ECT-A/D lockup data are data of an ECT-A/D lockup diagram as shown in FIG. 33 for operating the lockup clutch of the automatic transmission when the automatic speed control system is operating. For example, a map for shifting the speed stage as shown in FIG. 34 is set in the read only memory ROM as the ECT shift diagram. The ECT up timer data and the ECT-A/D up timer data are data for prohibition and delay of the up shift of the speed stage when the automatic speed control system is not operating and is operating, respectively. The ECT down timer data and the ECT-A/D down timer data are data for prohibition and delay of the down shift of the speed stage when the automatic speed control system is not operating and is operating, respectively. The torque data are data of torque diagrams as shown in FIG. 25 for calculating the torque of the vehicle. The maximum torque data are data of a maximum torque diagram as shown in FIG. 26 for calculating the maximum torque of the vehicle. The instructions for the vehicle speed control system are shown as flow diagrams in FIG. 2 through FIG. 19. Variables, registers, timers, flags and constants used in the flow diagrams are shown in FIG. 37 and FIG. 38.

When the ignition switch IG is turned ON and the regulated voltage supply CON begins to supply the voltage to the CPU, the operation of CPU is started. Referring to FIG. 2, in step 40, the condition of memories and ports is initialized. In this step, memories are cleared, ports P1 through P18, P22, P24 and P26 are set as input ports, ports P21, P23, P25 and P27 through P30 are set as output ports, and flags are set to the initial level thereof.

The condition of each input port is read out and flags or memories are set as follows (step 50):

Flag SW-D is set to "1" when the shift lever is positioned at the drive range, the reverse range or the parking range, and set to "0" when the shift lever is positioned at the neutral range, the second speed range or the low speed range.

Flag SW-BK is set to "1" when the brake switch BS is turned ON, and set to "0" when the brake switch BS is turned OFF.

Flag SW-PKB is set to "1" when the parking brake switch PK is turned ON, and set to "0" when the parking brake switch PK is turned OFF.

Flag SW-A/D-MAIN is set to "1" when the main switch ADS is turned ON, and set to "0" when the main switch ADS is turned OFF.

Flag SW-A/D-SET is set to "1" when the set switch SP is turned ON, and set to "0" when the set switch SP is turned OFF.

Flag SW-A/D-RES is set to "1" when the resume switch RS is turned ON, and set to "0" when the resume switch RS is turned OFF.

After step 50, a sub routine MODE CHANGE (step 60), a sub routine MAP CHANGE (step 80), a sub routine SHIFT JUDGMENT (step 100), a sub routine LOCKUP DATA SET (step 110), a sub routine SHIFT CONTROL (step 120) and a sub routine AUTOMATIC SPEED CONTROL (step 180) are executed continuously, and step 50 is executed again after these are completed.

The sub routine MODE CHANGE (step 60) as shown in FIG. 3 is executed for changing to ECT mode or ECT-A/D mode. The ECT mode is for actuating the automatic transmission control system only, and the ECT-A/D mode is for actuating both the automatic transmission control system and the automatic speed control system. When Flag SW-A/D-MAIN is "1", and Flag F-A/D-SET is "1", and timers T-T1, T-T2 and T-T3 are all "0", Flag F-ECT-A/D is set to "1" (step 61 through step 66), thereby changing the mode of the vehicle speed control system to ECT-A/D MODE. When Flag SW-A/D-MAIN is "0", and when Flag SW-A/D-MAIN is "1" and Flag F-A/D-CAN is "1", or when Flag SW-A/D-MAIN is "0", if timers T-T1, T-T2, T-T3, T-DEL-UP and T-DEL-MODE are all "0", then Flag F-ECT-A/D is set to "0" (step 61 and 68 through 73). Timers T-T1, T-T2 and T-T3, which are described later, are for shift of the speed stage. When these timers are not "0", the transmission is executing the shift of the speed stage. Timer T-DEL-UP is for delaying the up shift of the speed stage as described below. When timer T-DEL-UP is not "0", the up shift is not executed. Timer T-DEL-MODE is for delaying the mode changing. When timer T-DEL-MODE is not "0", the mode change is not executed. In this way, the mode of the vehicle speed control system is changed to ECT-A/D mode (flag F-ECT-A/D is set to "1") when the main switch ADS is turned ON, and further, the set switch is turned ON, and the mode of the vehicle speed control system is changed to ECT mode (flag F-ECT-A/D is set to "0") when the main switch ADS is turned OFF or the Flag F-A/D-CAN is set to "1". In this time, Flag F-ECT-A/D is set to "0" when the transmission is shifting (timers T-T1, T-T2 and T-T3 are not "0") or up shift is delayed (T-DEL-UP is not "0") or the mode change is delayed (T-DEL-MODE is not "0").

The sub routine MAP CHANGE as shown in FIG. 4 is executed after sub routine MODE CHANGE. When flag F-ECT-A/D is "1" (step 81), or when flag F-ECT-A/D is "0" and flag F-ACC is "1" and variable Vdev is not lower than 0.5 kilometer per hour (step 81 and step 84, 85 and 86), a constant ECT-SMAP is set to an address pointer Ps of the shift data and a constant ECT-LMAP is set to an address pointer P1 of the lockup data (step 82 and 83). When flag F-ECT-A/D is "0" and flag F-ACC is "0" and variable TH is equal to constant THmax (step 81, 84 and 90), or when flag F-ECT-A/D is "0" and flag F-ACC is "0" and variable TH is equal to constant THmax and flag F-ACC-SEN is "1" (step 81, 84, 90 and 91), a constant ECT-SMAP is set to an address pointer Ps of the shift data and a constant ECT-LMAP is set to an address pointer P1 of the lockup data (step 82 and 83) after flag F-ACC is set to "1" and timer T-DEL-UP is set to "0" (step 92 and 93). Variable Vdev is calculated in step 85 as the absolute value of the deviation between a present vehicle velocity Vc and the setting vehicle velocity Vset. The present vehicle velocity Vc is calculated by signals from the speed sensor SP1 and the speed sensor SP2. The setting vehicle velocity Vset is the vehicle velocity at the time which the set switch SP is turned OFF. Variable TH is the present throttle opening. Constant THmax is the maximum throttle opening, and the value of the THmax is "TH7". Thus, step 90 is a judgment step to determine whether the present throttle opening is "TH7". Flag F-ACC-SEN is set to "1" at timer interrupt, which is described below, when the amount of the throttle opening is large. Flag F-ACC is set to "1" if the present throttle opening is "TH7" or if the throttle opening is rapidly increased when the acceleration is not stepped at ECT-A/D mode. Flag F-ACC is set to "0" if the deviation between the present vehicle velocity Vc and the setting vehicle velocity Vset is smaller than 0.5 kilometer per hour when the acceleration is stepped at ECT-A/D mode. In this way, the value of the head address of ECT shift data (ECT-SMAP) is set to the address pointer Ps, and the value of the head address of ECT lockup data (ECT-LMAP) is set to the address pointer P1 at the ECT mode, at the time that the deviation Vdev is large but the accelerator is stepped at ECT-A/D mode, and at the time that the throttle opening is a maximum or moves quickly when the accelerator is not stepped at ECT-A/D mode. Therefore ECT shift and lockup data are used for shift and lockup judgment in this case.

When flag F-ECT-A/D is "0", flag F-ACC is "0", variable TH is not equal to variable THmax and flag F-ACC-SEN is "0" (step 81, 84, 90 and 91), a constant ECT-A/D-SMAP is set to the address pointer Ps and a constant ECT-A/D-LAMP is set to the address pointer P1 (step 88 and 89). When flag F-ECT-A/D is "0", flag F-ACC is "1" and variable Vdev is lower than 0.5 kilometer per hour (step 81, 84, 85 and 86), a constant ECT-A/D-SMAP is set to the address pointer Ps and a constant ECT-A/D-LMAP is set to the address pointer P1 (step 88 and 89) after flag F-ACC is set to "0" (step 87). In this way, the value of the head address of the ECT-A/D shift data (ECT-A/D-SMAP) is set to the address pointer Ps, and the value of the head address of the ECT-A/D lockup data (ECT-A/D-LMAP) is set to the address pointer P1 at the ECT-A/D mode, except when the deviation Vdev is large, but the accelerator is stepped, and the time that the throttle opening is a maximum or moves quickly when the accelerator is not stepped. Therefore the ECT-A/D shift and lockup data are used for shift and lockup judgment in this case.

The timer interrupt is shown in FIG. 19. The timer interrupt is executed one time per 200 milliseconds. Referring to FIG. 19, variable TH-CHK is set to the absolute value of the value by subtracting the value of variable TH-PAST from variable TH. The variable TH-PAST shows the value of the throttle opening before 200 milliseconds. In step 302, if the variable TH-CHK is larger than two, then flag F-ACC-SEN is set to "1". Thus, when the throttle opening is moved over two for 200 milliseconds, flag F-ACC-SEN is set to "1". In step 304, variable TH-PAST is replaced with the variable TH for next timer interrupt.

The sub routine SHIFT JUDGMENT as shown in FIG. 5 is executed after sub routine MAP CHANGE. When timer T-T4 is not "0" or when timer T-T5 is "0" and timer T-T3 is "0" (step 101, 102 and 103), a value of variable TH-REV is set in steps 104 through 107 and shift and lockup judgment is executed using the variable TH-REV, the present speed stage and the data indicated by the address pointers Ps and P1. Here, when the fixed duty control (described later) is executing, the shift and lockup judgment is not executed. The fixed duty control controls the throttle valve, so the throttle opening is changed, and the speed stage of the automatic transmission control system is shifted by the change of the throttle opening. This routine prohibits a new shift at the fixed duty rate control for decreasing the shock of the shift of the speed stage. In the shift and lockup judgment (step 108), if the created speed stage is lower than the last speed stage, then flag F-DWN is set to "1", and if the created speed stage is higher than the last speed stage, then flag F-DWN is set to "0". The variable TH-REV is set to TH+Vdev/5 at the ECT-A/D mode (flag F-ECT-A/D is "1"). The variation Vdev is a value Vc-Vset, wherein Vc is the present vehicle velocity and Vset is the setting Vehicle velocity. The variable TH-REV is set to TH at the ECT mode (flag F-ECT-A/D is "0"). In this way, at the ECT-A D mode, the shift and lockup judgment is executed taking the deviation Vdev into consideration. The variable amount of the shifting point and lockup point varies according to the magnitude of the deviation Vdev. If the deviation Vdev is positive, the down shifting is easier because the shift data is set so that the vehicle velocity at the shifting point is higher according to the increase of throttle opening. If the deviation Vdev is negative, the up shifting is easier because the shift data is set so that the vehicle velocity at shifting point is lower according to the decrease of throttle opening. When the vehicle is driven by the automatic speed control system, if the present vehicle velocity is smaller than the setting vehicle velocity, the vehicle is apt to raise the vehicle velocity because of easiness of down shift. When the vehicle is driven by the automatic speed control system, if present vehicle velocity is larger than the setting vehicle velocity, the vehicle is apt to reduce the vehicle velocity because of easiness of up shift.

Here, timer T-T3 (described later) indicates the time until the engaging of the lockup clutch is allowed from when the shift of the speed stage is completed. Timer T-T4 (described later) indicates the time until the start of the fixing duty rate control of the throttle valve. Timer T-T5 (described later) indicates the time until the end of the fixing duty rate control of the throttle valve from the start of the fixing duty rate control. Accordingly, in steps 101, 102 and 103, the shift and lockup judgment is not executed in the time from the shift to the end of the disengaging of the lockup clutch and in the time that the fixing duty rate control is executed.

The sub routine LOCKUP DATA SET, as shown in FIG. 6, is executed after sub routine SHIFT JUDGMENT. The deviation Vdev is set to the absolute value of the difference between the present vehicle velocity Vc and the setting vehicle velocity (step 112). When the deviation Vdev is larger than 2 kilometers per hour (step 113), flag F-EN-L/U is set to "0" (step 114), timer T-DIS-L/U is set to 5 seconds (step 115) and timer T-DIS-L/U is started (step 116). The timer T-DIS-L/U is decreased 1 bit according to a predetermined time, and becomes "0" after 5 seconds. When the deviation Vdev is smaller than 0.5 kilometers per hour (steps 113 and 117), flag F-EN-L/U is set to "1" (step 118). Flag F-EN-L/U is a lockup allowance flag. If the flag F-EN-L/U is "1", then the engaging of the lockup clutch is enablod, and if the flag F-EN-L/U is "0" than the engaging of the lockup clutch is not enabled during sub routine SHIFT CHANGE, described later. These operations are not executed if flag F-ECT-A/D is "0" (ECT mode).

The sub routine SHIFT CHANGE, as shown in FIGS. 7, 8 and 9, is executed after the sub routine LOCKUP DATA SET. When the shift of the speed stage is not occurring, flag F-DEL-UP, which indicates that the delay of up shift is occurring, is set to "0" and steps 161 through 170 are executed. When the shift of the speed stage is detected by the shift and lockup judgment of step 108 in FIG. 5, the speed stage is set to the RAM (step 123) and timers for shifting of the speed stage are established in the following step. When flag F-ECT-A/D is "0" (the mode is ECT mode) or flag F-ACC is "1" (the operation of the accelerator is occurring), if the shift of the speed stage is to a lower stage (flag F-DWN is "1"), then index register X is set to a constant ECT-DT, and if the shift of the speed stage is up shift (flag F-DWN is "0") then index register X is set to a constant ECT-UT at steps 125 through 127. The constant ECT-DT is a head address of the ECT down timer, and the timer data at the time that the shift of the speed stage is to lower stage are set in the contents of the addresses indicated by the values of ECT-DT to ECT-DT+4. The constant ECT-UT is a head address of the ECT down timer, and the timer data at the time that the shift of the speed stage is to higher stage are set in the contents of the addresses indicated by the values of ECT-UT to ECT-UT+4. After these steps, sub routine TEMPORARY TIMER SET is executed.

The sub routine TEMPORARY TIMER SET, as shown in FIG. 14, is for setting timers for shift of the speed stage. Referring to FIG. 14, variables T1-ORG, T2-ORG, T3-ORG, T4-ORG and T5-TRG are set to the value of variables T1-TEM, T2-TEM, T3-TEM, T4-TEM, T3-TEM, T4-TEM and T5-TEM, respectively. Variables T1-TEM, T2-TEM, T3-TEM, T4-TEM and T5-TEM are set to the contents of addresses X, X+1, X+2, X+3, X+4 and X+5, respectively. X is a value of the index register. The variables T1-ORG through T5-ORG are the old values of the timers T-T1 through T-T5, and the variables T1-TEM through T5-TEM are the temporary values of the timers T-T1 through T-T5. For example, in step 128 in FIG. 7, if the shift of the speed stage is to a lower stage, the variables T1-TEM, T2-TEM, T3-TEM, T4-TEM and T5-TEM are set to the contents of the addresses indicated by the values of ECT-DT, ECT-DT+1, ECT-DT+2, ECT-DT+3 and ECT-DT+4. In this way, the temporary timers are set. However, the timers are able to change according to the throttle opening, desired speed stage and the state of the lockup clutch, as shown if FIG. 22.

Referring to FIGS. 7 through 9 again, when the mode is ECT-A/D mode (flag F-ECT-A/D) is "1") and the acceleration is not operated (flag F-ACC is "0"), steps 132 through 143 are executed except for the case when the present vehicle velocity is lower than 50 kilometers and the setting speed stage in step 123 is 3rd speed. When the present vehicle velocity is lower then 50 kilometers and the setting speed stage in step 123 is 3rd speed, steps 132 through 160 are skipped. In this way, the shift for 3rd speed is not done, and the time of the shift of the speed stage is decreased, so the feeling to the vehicle occupants is more comfortable. The step 131 is able to change to the step in FIG. 36. In this routine, if each of the vehicle velocity Vc and the throttle opening TH is small, then the shift for O/D speed is not done. Also, if the throttle opening TH is large, then the shift for 1st and 2nd stage is not done. In step 132 through 143, if the shift of the speed stage is to a higher stage, the index register X is set to the value of constant ECT-A/D-UT, and sub routine TEMPORARY TIMER SET is executed. Further, if flag F-DEL-UP is "0", then timer T-DEL-UP is set to 4 seconds and the timer is started. In step 138, the sub routine UP SHIFT PROHIBITION is executed. Timer T-DEL-UP is an up shift delay timer, and delays the change of the speed stage until the timer become "0". In steps 132 through 143, if the shift of the speed stage is a down shift, the index register X is set to a constant ECT-A/D-DT, and sub routine TEMPORARY TIMER SET is executed. Further, timer T-DIS-UP is set to 5 seconds and the timer is started. Also, flag F-DEL-UP is set to "0".

The sub routine UP SHIFT PROHIBITION is shown in FIG. 13. In step 221, the index register X is set to the variable Vc (the present vehicle velocity), the register A is set to the variable NSHFT, which is the present shift position, and the register B is set to the variable TH (the present throttle opening). After that, the sub routine GET TRQ is executed.

The sub routine GET TRQ is shown in FIG. 16. Referring to FIG. 16, the index register X is set to a value by dividing the value of last index register X by 10 and by subtracting 4 (step 251). When a value after a decimal point occurs, then the value after the decimal point is omitted, because the index register X is not able to store the values after decimal point. For example, when the present vehicle velocity is 55 kilometers per hour, the value of index register X is changed to "1" after step 251. In step 251, the contents of index register X are stored in a stack. Then, if the value of index register X is larger than 5, the value of the index register X is replaced with 5, and flag CARRY is set to "1". If the value of index register X is smaller than 0, then the value of the index register is replaced with 0, and flag CARRY is set to "1". In step 258, the contents of the index register X are replaced with the value calculated by

In step 259, the value indicated by the index register X is stored in the register B. The TABLESIZ1 is a constant and means the number of the tables, as shown in FIG. 26. Referring to FIG. 26, there are six tables. For example, if the value of the index register X is "1" (the present vehicle velocity is 50 through 59 kilometers per hour), then Index 1 of the table (B) is selected. The TABLESIZ2 is a constant and means the number of speed stages (4 in this embodiment). For example, if the vehicle velocity is 67 kilometers per hour and the present speed stage is 2nd speed and further the present throttle opening is "TH5", then the value "170" is stored in register B. After that, the value calculated by step 251 is placed in index register X again. Here, the torque stored in the torque data is created by FIG. 23. FIG. 23 shows the relationship of the torque which is surveyed, the throttle opening, the speed stage and the vehicle velocity. For example, when the vehicle velocity is 50 kilometers per hour, the torque is as shown in FIG. 24.

Referring to FIG. 13 again, a variable TN is set to the value of the register B, which is the value of the present torque of the vehicle. After that, the register A is set to the value by adding 1 to the variable NSHFT. Then, the sub routine GET MAX TRQ is executed.

The sub routine GET MAX TRQ is shown in FIG. 18. The index register X has been set to the value calculated as the variable Vc in the sub routine GET TRQ. In step 291, the value in register A is replaced by a value calculated by subtracting 2 from the last value in the register A. The value in the index register X is replaced by a value calculated by multiplying the last value in the index register X by 3 and adding the value in the register A. Further, the value in the index register X is replaced by a value calculated by adding the constant TBL-MT to the last value in the index register X. In step 294, the register A is set to the contents of the address indicated by the index register X. The constant TBL-MT indicates the head address of the maximum torque data, and the register A contains a value which indicates the maximum torque of the vehicle, corresponding to the variable TN and the maximum torque data shown in FIG. 26. The variable TN shows the present torque, and the variable Vc shows the present vehicle velocity.

Referring to FIG. 13 again, in step 226, if the value of the variable TN is larger than the contents of the register A (the present torque is larger than the maximum torque), then flag F-DIS-UP is set to "1", and if the value of the variable TN is smaller than the contents of the register A (the present torque is smaller than the maximum torque), then flag F-DIS-UP is set to "0". Thus, in this sub routine, when the present torque is larger than the maximum torque, flag F-DIS-UP is set to "1" and the up shift of the speed state is prohibited.

Referring to the sub routine SHIFT CHANGE (FIG. 7, 8 and 9) again, in step 144 (FIG. 8), if timer T-DEL-UP is "0" then flag F-DEL-UP is set to "0" and the shift of the speed stage is allowed. After that, if the timers T-T1, T-T2, T-T3, T-T4 and T-T5 are all "0" (the shift of speed stage is not done at the present time), then the variables T1-TEM through T5-TEM are set to the timers T-T1 through T-T5, and timers T-T1, T-T2 and T-T4 are started. If one of the timers T-T1 through T-T5 is not "0", the deviation Vdev is set to the absolute value of the difference between the present vehicle velocity and the setting vehicle velocity. When the deviation is larger than 3 kilometers per hour, the values of the timers T-T1 through T-T5 are changed by subtracting the value of the passage time of the timers from the value of the temporary timers. The value of the passage time of the timers is calculated by subtracting the value of the present time of the timers form the value of the last temporary timers. If the changed value is less than zero, the changed value is replaced with zero. In this way, if the deviation Vdev is large, the value of the timers is decreased, and the shift of the speed stage occurs earlier. As shown in FIG. 19, when the deviation Vdev is small, the speed stage is not shifted for small changes of the throttle opening. As shown in FIG. 18, when the deviation is large, the shift of the speed stage is done for small changes of the throttle opening. In this way, when the deviation Vdev is large, the sensitivity is increased.

When timer T-T1 is "0" or the timer T-T1 ends, timer T-T3 is started (step 163). The end of timer T-T1 is at the time that the timer T-T1 is nearly "0". After that, when timer T-DIS-UP is "0" and flag F-DWN is "1" and when the timer T-DIS-UP is "0", Flag F-DWN is "0" and flag F-DIS-UP is "0", the data of the speed stage is sent to the output ports P21 and P23 (step 167). In short, when the up shift is not allowable, the shift of the speed stage of the transmission is not executed.

When timer T-T2 is "0" and timer T-T3 is not "0", high level voltage is sent from the output port P25 which is for lockup clutch control, so that the lockup clutch is disengaged. If timer T-T3 is at an end (T-T3 is "0"), then the value calculated by the shift and lockup judgment in step 108 is sent to the output port P25.

When timer T-T4 is "0" and the timer T-T4 is at an end, timer T-T5 is started. The end of timer T-T4 is at the time that the timer T-T4 is nearly "0".

For example, the state of timer T-T1, T-T2, T-T3, T-T4 and T-T5 and the states of shift of the speed stage and lockup clutch are shown in FIG. 20. Referring to FIG. 20, the shift of the speed stage is done at the end of timer T-T1. The lockup clutch is disengaged a the end of timer T-T2, and engaged at the end of timer T-T3. The fixing duty rate control that is described later is started at the end of timer T-T4, and ended at the end of timer T-T5.

After the timer operation, sub routine SOLENOID ABNORMAL DETECTING is executed (step 175). This routine is an abnormal detecting means. Referring to FIG. 1, when the output port P21 is high level, if the solenoid SL1 is normal, the input port P22 is turned to low level, and if the solenoid SL1 is opened, the input port P22 is turned to high level. When the output port P21 is low level, if the solenoid SL1 is normal, the input port P22 is turned to high level, and if each side of the solenoid SL1 is short circuited, then the input port P22 is turned to low level. In this way, if the solenoid SL1 is normal, when the output of the output port P21 is "1" (high), the input of the input port P22 is changed to "0" (low), and when the output is "0" (low), the input is "1" (high). The relation of the other output ports P23 and P25 and input ports P24 and P26 are same. Accordingly, if the value sent to the output port of a solenoid is equal to the value received at the input port of the solenoid, the failure of the solenoid is detected. Referring to FIG. 15, if the output data for solenoids is equal to the input data, then flag F-FAIL is set to "1" and the failure of the solenoid is able to be detected. When the solenoid is normal, flag F-FAIL is set to "0".

The sub routine AUTOMATIC SPEED CONTROL, as shown in FIGS. 10, 11 and 12, is executed after sub routine SHIFT CHANGE. When flag F-ACC is "0" and flag F-ECT-A/D is "1" and one of timers T-T1, T-T2 and T-T3 is not "0" at least, step 186 is executed. In step 186, if flag F-TH-HLD is "1", then step 194 is executed. The flag F-TH-HLD is for change states whether the fixed duty rate control is executed or not. When flag F-TH-HLD is "0", then the flag F-TH-HLD is turned to "1" (step 187). In step 188, index register X is set to variable Vc (present vehicle velocity), register A is set to variable NSHFT which is a present shift position, and register B is set to variable TH (present throttle opening). After that, sub routine GET TRQ is executed. In the sub routine, the present torque is stored in the register B. After sub routine GET TRQ, if the judgment of the shift of the speed stage is down shift, then a value calculated by subtracting 1 from NSHFT is placed in register A. If the judgment is up shift, then a value calculated by adding 1 to NSHFT is placed to register A. After that, the sub routine GET TH is executed.

Referring to FIG. 17, the variable TRQ is set to the value in register B, which contains the torque of the vehicle in the subroutine GET TRQ. The register B is set to a value "-1" (step 272). As the operation enters the loop consisting of steps 273 through 278, a value of +1 is added to the register A (step 273). When the contents of register B are smaller than a constant THmax, the contents of register B are stored to the stack, and sub routine GET TRQ is executed. In this subroutine GET TRQ, the torque of the vehicle is stored to the register B. If the value of the register B is not larger than variable TRQ, then the register B is set again to the value that is stored in step 275 and the operation is returned to step 273. If the value of register B is larger than variable TRQ, then register B is set again to the value that is stored in step 275. In these steps, the torque of the vehicle after the shift of the speed stage is calculated when the value of register A, which means the throttle opening is 0 through 7, and register B is stored with the torque at the time that the torque is larger than the present torque TRQ. If the torque is not larger than the present torque TRQ at the maximum throttle opening, then the register B is stored with the value THmax, indicating the maximum throttle opening.

Referring to FIG. 10 again, if the timer T-T4 is not "0", then step 197 is executed. If the timer T-T4 is "0" and the timer T-T5 is "0", then flag F-TH-HLD is set to "0" and step 197 is executed. If the timer T-T4 is "0" and the timer T-T5 is not "0", then the fixed duty rate control is executed in steps 208 and 209 in FIG. 11. Referring to FIG. 11, the variable THOUT is set to the value of register B that is stored with the value of the throttle opening after the shift of the speed stage. In step 209, the output port P29 is turned to low level, and the output ports P27 and P28 are controlled to keep the duty rate corresponding to the value of the variable THOUT (that is the fixed duty rate control).

In step 197, if flag SW-A/D-MAIN is "0", then flag F-A/D-CAN is set to "1", flag F-A/D-SET is set to "0" and the step 216 is executed. If flag SW-A/D-MAIN is "1" and flag SW-A/D-SET is "1", then the flag F-A/D-CAN is set to "0"and flag F-A/D-SET is set to "1". Further, timer T-DEL-MODE is set to one second and the timer is started. Thus, the timer T-DEL-MODE is started at ECT-A/D mode when the set switch SP is turned ON and delays the change of modes. For example, this relationship is shown in FIG. 21. When the mode is changed, the-speed stage is apt to shift, a shift of the speed stage does not occur at the same time the automatic speed control is set. Referring to FIG. 11 again, when flag F-ECT-A/D is "1", and flag F-FAIL is "0", the SPEED CONTROL routine (step 205) is executed. In this step, the vehicle velocity is held by controlling the duty rate of the output for the release valve RV and the control valve CV. Then flag F-TH-HLD is set to "0" (step 207), and the fixed duty rate control is cancelled. If the flag F-FAIL is "1", then flag F-A/D-CAN is set to "1", the automatic control is cancelled, and flag F-TH-HLD is set to "0". If the flag F-ECT-A/D is "0", then the sequence of steps 204 through 207 is not executed. In this routine, if the automatic transmission control system has a failure, the automatic speed control is cancelled. When a shift of the speed stage occurs by control of the throttle valve by the automatic speed control, if the solenoid of the transmission has failed, then the shift may be an unexpected shift. For example, when the solenoid SL2 fails to hold the ON state, the speed stage of the transmission can be only 1st speed or O/D speed. At this time, if the automatic speed control changes the stage very often between 1st speed and O/D speed due to changes in the grade of the road, the shock on the vehicle is very large and dangerous. But, in the present embodiment, this danger does not occur. Here, when the solenoid fails, the danger of a shift to the upper side of the speed stage is smaller than for the lower side. Thus, when a shift to the upper side of the speed stage occurs, the automatic speed control may be continued. This case is shown in FIG. 35. In step 204-a, when the flag F-FAIL is "1", if a shift to 3rd stage or O/D stage occurs, then the speed control is executed.

Referring to FIG. 12 again, in steps 210 through 215, the cancelling of the automatic speed control is executed. If flag SW-A/D-RES is "1", then flag F-A/D-CAN is set to "0", and the automatic speed control is not cancelled. When flag SW-A/D-RES is "0", if flag SW-PKB is "1", or if flag SW-BK is "1", or if flag SW-D is not "1", then flag F-A/D-CAN is set to "1", and the automatic speed control is cancelled.

In steps 216 through 218, if the present vehicle velocity is under 40 kilometers per hour, flag F-A/D-CAN is set to "1" and flag F-A/D-SET is set to "0". Accordingly, the automatic speed control is cancelled if the vehicle velocity is too low.