Method for Selecting a Spare Column and a Circuit Thereof

The present invention relates to a method for selecting a spare column and a circuit thereof for reading and storing data from and into a memory cell using MOS transistors.

In a circuit constructed with MOS transistors for reading and storing data from and into a memory cell, a normal bit line and a spare bit line exist. If there is something wrong in the normal bit line, it is widely known that data is read and written from and into a memory cell with the spare bit line.

In the prior art of selecting a spare column with a spare bit line, however, a clock signal which is produced by cutting a fuse for the spare column enables a spare column decoder after disabling a normal column decoder. Such method causes defects as are described below.

First, since the spare column is to be selected after disabling the normal column decoder, some delay time occurs which decreases speed in case of using the spare column. When the spare column and normal column are concurrently selected without this time delay, for a read cycle, a direct current path occurs through an input/output line between a sense amplifier of the spare bit line and that of the normal bit line during the read cycle; and for a write cycle, since data is concurrently written through the spare bit line and normal bit line, loading effect of bit line is doubled.

Second, when the spare column is selected, since the clock signal for selecting the spare column is applied to the normal decoder to disable the normal column decoder, the construction of logic schemetic becomes complicated.

It is an object of the present invention to provide a method of selecting a spare column which has no loss of speed by the way that at the selection of spare column, the function of disabling a normal column is substituted with the resultant function of the structure in which input/output line connected with the normal column can be isolated from an external read/write path, and which has no time delay at decoding the spare column.

Therefore, in the read cycle direct current source can be cut off between the sense amplifier of the spare bit line and that of the normal bit line, and since normal input/output line is open in this case, the effect of bit line loading reduces to very small quantity at the selection of the spare column. Consequently, rapid read and write operation can be performed.

In addition, no need to disable the normal column decoder leads to the simplification of the decoding logic because a clock signal for selecting the spare column does not relate to the decoding of the normal column decoder.

An other object of the present invention is to provide a spare column selecting circuit which can separate a spare bit line from a normal bit line at the selection of column decoder. A line switching unit is internally connected with the I/O unit connected with spare bit line and with the I/O unit connected with normal bit line and with the normal full-up circuit constructed in the I/O unit being connected with normal bit line, and these two circuits are designed to be controlled by the output of spare column decoder.

Therefore, in the case of selecting spare column, the I/O unit connected with spare bit line is separated from the I/O unit connected with normal bit line, and the I/O unit of normal bit line is designed to be ready for a next operating cycle with pulling up independently.

FIG. 1 is a circuit diagram of a spare column selection circuit of the present invention.

FIG. 2 is a graphic representation of various clocks for selecting a spare column in FIG. 1.

Referring to FIG. 1, a spare column selection circuit in which an external path unit PATH is arranged to transfer information during read and write cycles in connection with a pull-up circuit 17 supplying a constant supply voltage V.sub.CC.

A pair of spare input/output line unit 4 and 4' each connected with the PATH are coupled, in symmetry, with spare bit line pair 3 and 3', respectively, through MOS transistors pair MS1-MS4 and MS1'-MS4'. Each one terminal of the bit line of the spare bit line pair is connected to a corresponding sense amplifier including memory cell (not shown), respectively.

Similarly, a pair of normal input/output line units 5 and 5' are coupled, in symmetry, with normal bit line pair 6 and 6', respectively, through MOS transistors pair MN1-MN4 and MN1'-MN4'. Each one terminal of the bit line of the normal bit line pair is connected to a corresponding sense amplifier including memory cell (not shown), respectively. Both the spare input/output line unit pair 4 and 4' and the normal input/output line unit pair 5 and 5' are coupled with corresponding line switching pair 10 and 10' and normal line pull-up pair 20 and 20', respectively, all of which are composed of MOS transistor. A spare column decoder 1 is coupled with the line switching pair and the normal line pull-up pair. The line switching pair 10 and 10' and the normal line pull-up pair 20 and 20' are driven complementally each other by a clock pulse .phi..sub.D from the spare column decoder 1.

An inverter I.sub.1 connected to the spare column decoder 1 causes a clock .phi..sub.SCD which is produced at the time of the selection of the spare bit line pair to couple the spare bit line pair 3 and 3' with the PATH due to the application to the MOS transistors pair MS1-MS4 and MS1'-MS4' of the clock .phi..sub.SCD. A clock .phi..sub.NCD which is an output of a normal column decoder 11, is applied to the gates of MOS transistors pair MN1-MN4 and MN1'-MN4' so that the normal bit line pair 6 and 6' and the PATH are connected each other.

To the spare column decoder 1 are applied a column address signal COLADD, spare column selection clock .phi..sub.SC, and a clock .phi..sub.Y which gives an information that bit sensing operation has been completed. A logic level of the spare column selection clock .phi..sub.SC is determined whether the level is high or low, by the connection or cut of a fuse.

With the circuit arrangement described hereinbefore, the operation of the circuit will now be described.

During the operation of the normal column, an output of the spare column decoder 1 which is a high level generates the clock signal .phi..sub.D which opens a normal input/output unit, the clock signal .phi..sub.SCD through the inverter I.sub.1 is a low level. The low level clock signal .phi..sub.SCD is applied to the gate of the MOS transistors MS1-MS4, MS1'-MS4' to be kept in a cut-off state. Therefore, the spare bit line pair 3 and 3' are separated from the spare input/output line pair 4 and 4' in an open state.

The normal input/output line unit pair 5 and 5' and the spare input/output line unit pair 4 and 4' are connected each other by the line switching pair 10 and 10'. The normal bit line pair 6 and 6' are connected with the external PATH unit by the normal column decoding clock .phi..sub.NCD of high level generated from the normal column decoder 11 so that the information of a memory cell can be transferred. At this time, the pull-up circuit 17 supplies the supply voltage V.sub.CC to the lines in the PATH unit for stable operation.

For selecting the spare column, the clock .phi..sub.D outcomes in a low level and the clock signal .phi..sub.SCD outcomes in a high level, since the clock signal .phi..sub.SC being generated in accordance with cutting-off the fuse for the spare column.

At this instant, since the PMOS transistors of the normal line pull-up circuits 20 and 20' are turned on by the application of the clock .phi..sub.D of a low level, the clock .phi..sub.SCD of a high level through the inverter I.sub.1 turns on the MOS transistors pair MS1-MS4 and MS1'-MS4' after starting the pull-up of the normal input/output line pair 5 and 5' so that the spare bit line pair 3 and 3' are coupled with the external PATH unit.

The clock .phi..sub.SC notifying the selection of the spare column does not control the column decoder 11 and the clock .phi..sub.NCD generated from the normal column decoder 11 is controlled by the signal of column address signal. At a high level of .phi..sub.SC, the spare input/output line unit pair 4 and 4' and the normal input/output line unit pair 5 and 5' are separated each other, and hence the external PATH unit is not connected to them, so that the input/output line unit with respect to the normal bit lines waits for next cycle with the state pulled-up by the normal line pull-up circuits 20 and 20'. Since the clock .phi..sub.SCD is always generated after the separation of the spare input/output line unit pair 4 and 4' from the normal input/output line unit pair 5 and 5', the time taken for the spare bit line pair 3 and 3' to be connected with the normal bit line pair 6 and 6' can be logically excluded, and the time taken for the spare column to be selected by the spare column decoder 1 can be difined without relation with the time taken for the normal column to be selected.

FIG. 2 is a graphic representation of various clocks for selecting the spare column in FIG. 1. A clock RAS is a raw address strobe signal and CAS is a column address strobe signal, and at each low level of each signal, pertinent address signals to raw or column are supplied to address lines. After the passage of defined time which is different with a different logic at the RAS signal in a low level, sensing operation between bit lines is completed to generate the clock .phi..sub.Y which notifies the connection to the input/output lines. In accordance with the signal .phi..sub.Y, the signal .phi..sub.NCD of the output signal from the normal column decoder 2 is generated to connect the PATH unit with the normal bit line units at the selection of normal bit line, and at the selection of the spare column, the clock signal .phi..sub.SC is generated from the column address signal to notify the selection of the spare column. The selection of the normal column or spare column is defined according to on or off status of the fuse. At the selection of the spare column, the clock signal .phi..sub.NCD is generated from the column signal of column address, and the time taken for the spare column to be selected and the time taken for the normal column to be selected are able to be defined without relation with each other, therefore, the time delay occurring at the selection of the spare column can be out of the user's consideration.

But at the selection of the spare column, it is the first to generate the clock signal .phi..sub.D which turns on the normal input/output line units, and in the cut-off condition with the normal bit line, the clock .phi..sub.SCD from the spare column decoder is generated to connect the spare bit line with the PATH unit.

As described above, in the circuit according to the present invention, the spare input/output units which are connected with the spare bit line pair are arranged to be isolated from the normal input/output line units which are connected with the spare bit line pair are arranged to be isolated from the normal input/output line units which are connected with the normal bit line, each bit line is designed to be selected by means of the corresponding line switching unit which is controlled by the spare column decoder.

The time taken for the spare column to be selected can be determined without relation with the selection of the normal column, thus the time delay occurring at the selection of the spare column can be negligible from the user's consideration.

In addition, at the selection of the spare column, the decoding circuit for the normal column decoder can be simplified due to unnecessity of disabling the normal column decoder.

This invention is in no way limited to the example described hereinabove. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modification of embodiments as fall within the true scope of the invention.