Stepped-Waveform Inverter With Six Subinverters

The present invention relates to a power conversion system, and more particularly to an inverter for a power conversion system.

Power conversion systems, such as variable-speed, constant-frequency (VSCF) power conversion systems, are commonly used in aircraft and aerospace applications to generate AC and DC power from a prime mover, such as a jet engine. In such an application, variable-frequency AC power may be produced by a brushless, synchronous generator driven by the jet engine. The variable-frequency AC power is converted to DC power by an AC/DC converter, such as a rectifier bridge. An inverter is coupled to the AC/DC converter to transform the DC power into constant-frequency AC power, which is then filtered by a filter. The filtered AC output is then provided to an AC load bus which supplies power to various points throughout the aircraft.

The inverter used in VSCF systems may be of the stepped-waveform type. An inverter of this type is disclosed in U.S. Pat. No. 3,775,662 to Compoly, et al. Such a stepped-waveform inverter generates an output having a stepped shape that generally approximates a sine wave. The purpose of approximating a sine wave is to reduce the size of the filters, provided at the output of the inverter, that are used to remove unwanted harmonics. While previous stepped-waveform inverters may accomplish such goals, efficient and effective methods of control of such inverters have heretofore been lacking.

The present invention is directed to an inverter for use in a power conversion system. The inverter converts DC power into constant-frequency AC power. The inverter includes a summing transformer and is responsive to the AC power generated by the power conversion system. The inverter regulates the AC power by controlling the phase angles between various waveforms produced by a number of subinverters of the inverter.

In one aspect, the invention is directed to an inverter for use in a power conversion system that produces an AC output. The inverter has a summing transformer that includes six three-phase transformers. The transformers are grouped into three subgroups. Each subgroup consists of two subinverters and two three-phase transformers. One of the two three-phase transformers in each subgroup has star-connected primary windings and the other three-phase transformer has delta-connected primary windings. The transformers have secondary windings coupled to the primary windings.

Each of the subinverters generates a respective waveform in the primary windings of its associated transformer. The phase angle between two of the waveforms is a first variable angle, and the phase angle between another two of the waveforms is a second variable angle. A regulator circuit is coupled to sense the AC output, and the regulator circuit controls the first variable angle and the second variable angle based upon the AC output.

In another aspect of the invention, the regulator circuit senses both the current and voltage of the AC output, and the regulator circuit controls the first variable angle based upon the sensed voltage and the second variable angle based upon the sensed current.

These and other aspects, features, and advantages of the present invention will be apparent to those of ordinary skill in the art in view of the detailed description of the preferred embodiments, which is made with reference to the drawings, a brief description of which is provided below.

FIG. 1 is a block diagram of a VSCF power conversion system for generating AC and DC power from a prime mover;

FIG. 2 is a block diagram of the inverter of FIG. 1;

FIG. 3 is a circuit diagram of one pair of subinverters and their associated transformers of the inverter of FIG. 2;

FIG. 4 is a circuit diagram of one of the activation circuits of FIG. 2;

FIG. 5 illustrates a first phase relationship of a number of waveforms generated by the inverter and a waveform produced by the summation of those waveforms;

FIG. 6 illustrates a second phase relationship of a number of waveforms generated by the inverter and a waveform produced by the summation of those waveforms;

FIG. 7 illustrates a third phase relationship of a number of waveforms generated by the inverter and a waveform produced by the summation of those waveforms;

FIG. 8 illustrates a fourth phase relationship of a number of waveforms generated by the inverter and a waveform produced by the summation of those waveforms;

FIGS. 9a-9c are vector diagrams illustrating a first mode of operation of the inverter of the invention;

FIGS. 10a-10c are vector diagrams illustrating a second mode of operation of the inverter of the invention;

FIG. 11 illustrates various waveforms relating to the operation of the phase angle control circuit of FIG. 2;

FIG. 12 is a circuit diagram of the phase angle control circuit shown schematically in FIG. 2;

FIG. 13 is a circuit diagram of the output sensing circuit shown schematically in FIG. 2; and

FIG. 14 is a graph of two voltage signals used in the phase angle control circuit to control the phase relationship of the waveforms generated by the inverter.

A block diagram of a preferred embodiment of a VSCF power conversion system 10 incorporating the present invention is shown in FIG. 1. The VSCF system 10 includes a prime mover 12 coupled to a generator 14 for generating variable-frequency AC power. An AC/DC converter 16 is coupled to the generator 14 for converting the variable-frequency AC power into DC power. The DC output of the AC/DC converter 16 is supplied to various DC loads in the aircraft via a pair of lines 20a, 20b. A second pair of lines 22a, 22b provides the DC output to an inverter 24, which generates three-phase, constant-frequency AC power from the DC output of the converter 16. The inverter 24 is coupled to a filter 26 via three output lines 28a, 28b, 28c, each of which supplies a respective phase of the constant-frequency AC output to the filter 26. The output of the filter 26 is provided via lines 29 to a three-phase AC load bus which supplies AC power to various AC loads in the aircraft.

A block diagram of the inverter 24 is shown in FIG. 2. The inverter 24 includes three subinverter pairs 30, 32, 34. Each of the subinverter pairs 30, 32, 34 is coupled to a respective transformer pair 31, 33, 35. The output lines 28a, 28b, 28c interconnect each of the transformer pairs 31, 33, 35, and the transformer pair 35 is connected to a neutral line 28d. Each of the subinverter pairs 30, 32, 34 is controlled by a respective activation circuit 40a-c.

A regulator circuit for regulating the voltage on the transformer output lines 28a, 28b, 28c is shown to comprise an output sensing circuit 50 and a phase angle control circuit 52. The output sensing circuit 50 senses the current on the three transformer output lines 28a, 28b, 28c via three lines 56a, 56b, 56c, and the sensing circuit 50 senses the voltage on the three output lines 28a, 28b, 28c via three lines 58a, 58b, 58c. The output sensing circuit 50 generates a phase control signal, .PHI..sub.c, having a magnitude based on both the voltage and current sensed on the lines 28a-c and provides the .PHI..sub.c signal to the phase control circuit 52 via a line 60. Based on the magnitude of the .PHI..sub.c signal, the phase angle control circuit 52 causes the phase angles between the various waveforms generated by the three subinverter pairs 30, 32, 34 to be varied. As a result of the control of the phase angles, the magnitude of the voltage on the transformer output lines 28a, 28b, 28c is regulated.

Alternatively, instead of sensing the AC output on the lines 28a-c, the regulator circuit could sense the AC output on the lines 29 after the AC output is filtered by the filter 26.

The phase angle control circuit 52 varies the magnitude of the phase angles by generating a pair of reset signals, RES2 and RES3, based upon the magnitude of the phase control signal .PHI..sub.c and a pair of reference signals, REF1 and REF2. The REF1 and REF2 signals are transmitted to the phase angle control circuit 52 from the first and second activation circuits 40a, 40b via a pair of lines 66, 68, respectively. The RES2 and RES3 signals are transmitted from the phase angle control circuit 52 to the second and third activation circuits 40b, 40c via a pair of lines 70, 72, respectively. As described in more detail below, the RES2 signal controls the phase angle between the waveforms generated by the first subinverter pair 30 and the waveforms generated by the second subinverter pair 32, and the RES3 signal controls the phase angle between the waveforms generated by the second subinverter pair 32 and the waveforms generated by the third subinverter pair 34.

The first subinverter pair 30 and the first transformer pair 31 are shown in FIG. 3. The first subinverter pair 30 includes two subinverters 30a, 30b, and the first transformer pair 31 includes two three-phase transformers 31a, 31b.

The subinverter 30a includes six transistor switches 82a-c, 84a-c, each of which has a diode connected across it. The subinverter 30a is connected to three star- or wye-connected primary windings 80a-c of the transformer 31a which are controlled by the three pairs of switches 82a-c, 84a-c. The upper terminal of the winding 80a is connected to the junction of the switches 82a, 84a; the upper terminal of the winding 80b is connected to the junction of the switches 82b, 84b; and the upper terminal of the winding 80c is connected to the junction of the switches 82c, 84c. The primary windings 80a-c of the transformer 31a are coupled to three secondary windings 90a-c, respectively.

During operation of the subinvert 30a, exactly one of the two switches in each vertical branch is conducting. In particular, one of the two switches 82a, 84a is conducting and the other is off; one of the switches 82b, 84b is conducting and the other is off; and one of the switches 82c, 84c is conducting and the other is off. The switches 82a-c and 84a-c are switched in a conventional manner to generate the waveform 220 in FIG. 5 on each of the three wye-connected windings 80a-c, each of the three waveforms differing in phase by 120.degree. . Because the windings 80a-c are wye-connected, the waveform 220 has five possible amplitudes at any point in time, +A, +A/2, 0, -A/2, and -A, where A is the maximum amplitude.

The subinverter 30b includes six transistor switches 94a-c, 96a-c, each of which has a diode connected across it. The subinverter 30b is connected to three delta-connected primary windings 92a-c of the transformer 31b which are controlled by the three pairs of switches 94a-c, 96a-c. The upper terminal of the winding 92a is connected to the junction of the switches 94a, 96a; the upper terminal of the winding 92b is connected to the junction of the switches 94b, 96b; and the upper terminal of the winding 92c is connected to the junction of the switches 94c, 96c. The three delta-connected primary windings 92a-c are coupled to three secondary windings 98a-c of the transformer 31b, respectively.

The switches 94a-c and 96a-c are switched in a manner similar to switches 82a-c and 84a-c to generate the waveform 222 in FIG. 5 on each of the three delta-connected windings 92a-c, each of the three waveforms 222 having a phase difference of 120.degree. . Because the windings are delta-connected, such a waveform has three possible amplitudes, +A, 0, and -A, where A is the maximum amplitude.

While the switches 82a-c, 84a-c, 94a-c, 96a-c are shown to be transistors, other types of switches may be used, such as thyristors or Darlington-connected transistor pairs.

The circuit diagrams for the second and third subinverter pairs 32, 34 and the second and third transformer pairs 33, 35 are identical to the one shown in FIG. 3 and are not shown separately for purposes of simplicity.

The activation of the twelve switches 82a-c, 84a-c, 94a-c, 96a-c in each of the subinverter pairs 30, 32, 34 is controlled by a respective one of the activation circuits 40a-c. Since the three activation circuits 40-c are substantially identical, only one is shown. Referring to FIG. 4, the activation circuit 40 includes three four-bit counters 110, 112, 114 connected to an EPROM 116 connected to a driver circuit 118. The counters 110, 112, 114 are driven by a clock signal, CLK, generated by a main controller (not shown). The carry output of the counter 110 is input to the counter 112 via a line 111, and the carry output of the counter 112 is input to the counter 114 via a line 113. Upon each pulse of the CLK signal, the 10-bit output of the counters 110, 112, 114 is incremented by one. This 10-bit output is used as an address to address the EPROM 116.

The EPROM 116 has a six-bit binary code stored in each of its address locations. The six binary bits control the activation of the 12 switches in one of the subinverters. In particular, one bit of the six-bit binary code is output on the line 122 to the driver 118, which generates an uncomplemented switching signal on a line 124 and a complemented switching signal on a line 126. The line 124 is connected to the base of one transistor in one vertical branch of one of the subinverters, such as switch 82a, and the line 126 is connected to the base of the other switch in the vertical branch, such as switch 84a.

The remaining five bits of the six-bit binary code are output on the lines 130, 132, 134, 136, 138, respectively, to the driver circuit 118, which generates on its outputs a pair of complemented driving signals for each of the five binary signals. These driving signals are supplied to the remaining switches of the subinverter.

During operation of the activation circuit 40, as the CLK signal supplied to the counters 110, 112, 114 is periodically incremented, the six bits of the binary code are periodically output from the EPROM 116 via lines 122, 130-138 to the driver 118, and the 12 switches of each of the subinverters 30a, 30b, 32a, 32b, 34a, 34b are controlled to generate the waveforms 220, 222, 224, 226, 228, 230 shown in FIG. 5 on the primary windings of each of the transformers 31a, 31b, 33a, 33b, 35a, 35b, respectively.

The EPROM 116 generates a reference signal, REF, on a line 142. As described in more detail below, the REF signal is used as a phase reference signal.

A reset signal, RES, may be input to the counters 110, 112, 114 via a line 140. When the RES signal is activated, the counters 110, 112, 114 are reset, thus providing a 10-bit address to the EPROM 116 equal to zero. The contents of each EPROM in the three activation circuits 40-c are identical. If each of the EPROMs is given the same sequence of addresses, the resulting waveforms generated by the subinverters would be identical and thus have zero phase angle. Accordingly, the time of reset of the counters 110, 112, 114 of an activation circuit determines the phase angle between the waveforms generated by that activation circuit and the waveforms generated by the other two activation circuits.

When the activation circuit 40 of FIG. 4 is used for the activation circuit 40a shown in FIG. 2, the REF line 142 of FIG. 4 is connected to the REF1 line 66 of FIG. 2, and the RES line 140 of FIG. 4 is not used. When the activation circuit 40 of FIG. 4 is used for the activation circuit 40b, the REF line 142 of FIG. 4 is connected to the REF2 line 68 of FIG. 2, and the RES line 140 of FIG. 4 is connected to the RES2 line 70 of FIG. 2. When the activation circuit 40 of FIG. 4 is user for the activation circuit 40c, the RES line 140 of FIG. 4 is connected to the RES3 line 72 of FIG. 2, and the REF line 142 of FIG. 4 is not used.

Stepped-waveform inverters having six subinverters as shown in FIG. 2 are referred to as 36-step inverters.

Referring to FIG. 5, the waveforms generated by the subinverters 30a, 30b, 32a, 32b, 34a, 34b in the primary windings of the transformers 31a, 31b, 33a, 33b, 35a, 35b are shown. The summing transformer output waveform 240 shown in the bottom portion of FIG. 5 is generated on each of the three transformer output lines 28a, 28b, 28c, each of the three waveforms 240 being 120.degree. apart. The waveform 240 represents the summation of the waveforms 220, 222, 224, 226, 228, 230.

The inverter 24 of the present invention has two modes of operation. A first mode of operation is used when the current on the output lines 28-c of the summing transformer is below a predetermined threshold. A second mode of operation is used when the output current is above the predetermined threshold.

In the first mode of operation, the phase angle between the waveforms generated by the first subinverter pair 30 and the waveforms generated by the second subinverter pair 32 is held constant, preferably 15.degree., and the phase angle between the waveforms generated by the second subinverter pair 32 and waveforms generated by the third subinverter 34 is varied, depending upon the output voltage sensed on the transformer output lines 28a-c.

The waveforms shown in FIGS. 5 and 6 illustrate the first mode of operation. It should be noted that the first subinverter pair waveforms 220, 222 and the second subinverter pair waveforms 224, 226 of both FIGS. 5 and 6 have a fixed phase angle of 15.degree.. However, the phase angle between the second subinverter pair waveforms 224, 226 and the third subinverter pair waveforms 228, 230 is 0.degree. in FIG. 5 and 60.degree. in FIG. 6. By controlling the phase angle between the second and third subinverter pair waveforms, the resultant output voltage may be regulated. For example, the waveform 240 of FIG. 5 has a peak positive amplitude of +6A and a peak negative amplitude of -6A, whereas the output voltage waveform 240 of FIG. 6 has a peak positive amplitude of +51/2A and a peak negative amplitude of -51/2A.

Referring to FIGS. 9a-9c, the vector diagrams in those figures illustrate the first mode of operation. The vector V.sub.1 represents the first subinverter pair waveforms 220, 222; the vector V.sub.2 represents the second subinverter pair waveforms 224, 226; and the vector V.sub.3 represents the third subinverter pair waveforms 228, 230. In each of FIGS. 9a-c, the phase angle between V.sub.1 and V.sub.2 is constant, at 15.degree.. The phase angle between V.sub.2 and V.sub.3 may vary from a minimum phase angle of 0.degree. as shown in FIG. 9a to a maximum phase angle of 120.degree. as shown in FIG. 9c. In between the minimum and maximum phase angles, the phase angle may be any variable angle .alpha. as shown in FIG. 9b. The vector positions shown in FIGS. 9a and 9c represent the extreme phase angles of the first mode of operation, and during normal operation the phase angles will be as shown in FIG. 9b.

In the second mode of operation, the phase angle between the waveforms generated by the first and second subinverter pairs is a variable angle between 15.degree. and 120.degree., while the phase angle between the waveforms generated by the second and third subinverter pairs is held constant, preferably 120.degree.. As a result, the voltage on the transformer output lines is gradually reduced to zero. The second mode of operation is used when the current on the output lines 28a-c is above the predetermined threshold.

The waveforms shown in FIGS. 7 and 8 illustrate the second mode of operation. In FIGS. 7 and 8, the third subinverter pair waveforms 228, 230 lag the second subinverter pair waveforms 224, 226 by a constant 120.degree.. However, the phase angle between the first subinverter pair waveforms 220, 222 and the second subinverter pair waveforms 224, 226 is 45.degree. in FIG. 7 and 120.degree. in FIG. 8. The transformer output voltages, which are represented by the waveforms 240 in FIGS. 7 and 8, are gradually reduced to zero. In FIG. 7, the amplitude of the waveform 240 reaches a peak amplitude of +3A between 135.degree. and 150.degree. and -3A between 315.degree. and 330.degree., and in FIG. 8 the waveform 240 has zero amplitude.

Now referring to FIGS. 10a-10c, the vector diagrams in those figures illustrate the second mode of operation. The vector V.sub.1 represents the first subinverter pair waveforms 220, 222; the vector V.sub.2 represents the second subinverter pair waveforms 224, 226; and the vector V.sub.3 represents the third subinverter pair waveforms 228, 230. In FIGS. 10a-10c, the phase angle between V.sub.2 and V.sub.3 is constant, at 120.degree.. The phase angle between V.sub.1 and V.sub.2 may vary from a minimum phase angle of 15.degree. as shown in FIG. 10a to a maximum phase angle of 120.degree. as shown in FIG. 10c. In between the minimum and maximum phase angles, the phase angle may be any variable angle .beta. as shown in FIG. 10b.

One manner of controlling the phase angles is illustrated in FIG. 11, which illustrates the control of the phase angle between the subinverter 32a waveform 224 and the subinverter 34a waveform 228. Referring to Fig. 11, the waveform 224 is shown in its phase relationship with respect to the REF2 signal. As can be seen, REF2 changes from zero to positive when waveform 224 transitions to a positive amplitude and from positive to zero when waveform 224 transitions to a negative amplitude. A ramp signal, RAMP, is generated based upon the magnitude of the REF2 signal. The rising edge of the REF2 signal corresponds to the beginning of the RAMP signal. When the REF2 signal is positive, the amplitude of the RAMP signal slowly increases. When the magnitude of the REF2 signal changes to zero, the magnitude of the RAMP signal quickly decreases to zero.

The RAMP signal is used to generate the RES3 signal based on a phase control signal .PHI..sub.c3 generated from the phase control signal .PHI..sub.c of FIG. 2. The magnitude of the .PHI..sub.c3 signal varies, depending upon the magnitude of the current and voltage sensed on the transformer output lines 28a, 28b, 28c. The relative values of the RAMP and .PHI..sub.c3 signals are used to generate a comparison signal, COMP, having a positive amplitude when the value of the RAMP signal is greater than the value of the .PHI..sub.c3 signal and a zero amplitude when the value of the RAMP signal is less than the value of the .PHI..sub.c3 signal. The point of intersection of the rising portion of the RAMP signal and the .PHI..sub.c3 signal determines the magnitude of the phase delay between the subinverter waveforms. This intersection point is shown as point 260 in FIG. 11.

At the intersection point 260, the COMP signal changes from zero to a positive amplitude. The rising edge of the COMP signal triggers the RES3 signal to become positive, or activated. When the RES3 signal is activated, it resets the counters associated with the third subinverter pair 34. As a result, the counters produce a zero 10-bit address, and the EPROM starts to generate the waveform 228. Thus, the time-occurrence of the rising edge of the RES3 signal controls the phase difference between the waveform 224 and the waveform 228. This phase difference is shown in FIG. 12 as .DELTA..PHI..

It should be appreciated that the magnitude of the .PHI..sub.c3 signal determines the magnitude of the phase delay .DELTA..PHI.. If the magnitude of .PHI..sub.c3 is larger, the .PHI..sub.c3 signal will intersect the RAMP signal later, thus causing a larger phase delay. If the magnitude of .PHI..sub.c3 is smaller, the .PHI..sub.c3 signal will intersect the RAMP signal earlier, thus causing a smaller phase delay.

The manner of varying the phase angle between the first subinverter pair waveforms and the second subinverter pair waveforms is similar to the manner described immediately above, except that the phase angle is between waveforms 220 and 224, REF1 is used in place of REF2, and RES2 is generated instead of RES3.

One phase angle control circuit 52 for controlling the phase angles between the three subinverter pairs 30, 32, 34 is shown in FIG. 12. The REF1, REF2, and .PHI..sub.c signals are input to the phase angle control circuit 52 via the lines 66, 68, 60, respectively, and the circuit 52 generates the RES2 and RES3 signals on the lines 70, 72, respectively. Referring to FIG. 13, the circuit 52 includes a ramp generator comprising a comparator 302 having an inverting input which receives the REF1 signal and a noninverting input that receives a predetermined reference voltage. The ramp generator also includes a transistor 304, a capacitor 306, and a constant current source comprising an operational amplifier 308 and a transistor 310.

The capacitor 306 is slowly charged by the constant current source via the transistor 310 when the transistor 304 is nonconducting and is quickly discharged through the transistor 304 when the transistor 304 becomes conductive. The transistor 304 conducts when the value of the REF1 signal is less than the predetermined voltage provided at the noninverting input of the comparator 302. As a result, a ramp signal is produced on the line 312.

The ramp signal is input to the noninverting input of a comparator 314 via the line 312. The inverting input of the comparator 314 is supplied with a .PHI..sub.c2 signal having a magnitude based upon the .PHI..sub.c signal. The comparator 314 generates on a line 316 a comparison signal having a high output when the value of the ramp signal is greater than .PHI..sub.c2 and a low output when the value of the ramp signal is less than the value of .PHI..sub.c2. The comparison signal on line 316 is provided to a monostable multivibrator, or one-shot 318 comprising three inverters and a capacitor. The output of the one-shot 318 is the RES2 signal, which determines the phase angle between the waveforms of the first subinverter pair 30 and the waveforms of the second subinverter pair 32.

The RES3 signal is generated in a similar manner. A second ramp generator comprises a comparator 332 having an inverting input that receives the REF2 signal and a noninverting input that receives the reference voltage. The second ramp generator also includes a transistor 334, a capacitor 336, and a constant current source comprising an operational amplifier 338 and a transistor 340.

The capacitor 336 is slowly charged by the constant current source via the transistor 340 when the transistor 334 is not conducting and is quickly discharged through the transistor 334 when the transistor 334 conducts. The transistor 334 conducts when the value of the REF2 signal is less than the predetermined voltage provided at the noninverting input of the comparator 332. As a result, a ramp signal is produced on the line 342.

The ramp signal is input to the noninverting input of a comparator 344 via the line 342. The inverting input of the comparator 344 is supplied with the .PHI..sub.c3 signal. The comparator 344 generates on a line 346 a comparison signal having a high output when the value of the ramp signal is greater than .PHI..sub.c3 and a low output when the value of the ramp signal is less than the value of .PHI..sub.c3. The comparison signal on line 346 is provided to a one-shot 348 comprising three inverters and a capacitor. The output of the one-shot 348 is the RES3 signal which determines the phase angle between the waveforms of the second subinverter pair 32 and the waveforms of the third subinverter pair 34.

The magnitude of the .PHI..sub.c2 and .PHI..sub.c3 signals is determined by a third portion of the phase angle control circuit 52 shown in the bottom of FIG. 12, based upon the magnitude of the .PHI..sub.c signal. The .PHI..sub.c3 signal is generated by an operational amplifier 350 that acts as a voltage follower. Thus, the output of the amplifier 350 follows the magnitude of the .PHI..sub.c signal. A zener diode 352 is connected to the output of the amplifier 350 and acts to limit the magnitude of the .PHI..sub.c3 signal to a maximum predetermined value. This predetermined value is the voltage that causes a 120.degree. phase angle difference between the second and third subinverter pair waveforms.

The .PHI..sub.c2 signal is generated by an operational amplifier 354 that acts as an inverter. The .PHI..sub.c signal is supplied to the noninverting input of the amplifier 354, while a predetermined voltage signal is supplied to its inverting input. The predetermined voltage is produced by an operational amplifier 356 having its noninverting input connected to a reference source 358.

The .PHI..sub.c signal is generated by the output sensing circuit 50 based upon the current and voltage sensed on the transformer output lines 28a-c. The output sensing circuit 50 is shown in detail in FIG. 13. Referring to FIG. 13, the output sensing circuit 50 includes a first portion shown at the bottom of FIG. 13 that generates a voltage based on the amount of current sensed in the lines 56a, 56b, 56c. The three phases of output current, I.sub..PHI.A, I.sub..PHI.B, I.sub..PHI.C, on the lines 56a, 56b,56c, respectively, are rectified by a half-wave rectifier circuit 360. The output of the half-wave rectifier circuit 360 is filtered by a smoothing capacitor 362 and then provided to the inverting input of a operational amplifier 364 used for scaling purposes. The output of the operational amplifier 364 is passed through a zener diode 366 which is coupled to the inverting input of an operational amplifier 368 that acts as an inverter. The operational amplifier 368 generates a negative voltage, -I.sub.o, that is zero if the amount of current sensed in the lines 56a, 56b, 56c is not above a predetermined threshold. The current threshold corresponds to twice the rated current for the power conversion system 10. If the current sensed is above the threshold, then the magnitude of -I.sub.o is proportional to the amount of current over the threshold, or overcurrent. The -I.sub.o signal is transmitted to a summing point 370 via a line 372.

The upper portion of the output sensing circuit 50 comprises three precision full-wave rectifiers 390, 392, 394 coupled to receive the phase voltages, V.sub..PHI.A, V.sub..PHI.B, V.sub..PHI.C on the lines 58a, 58b, 58c, respectively. The rectified phase voltages are summed at the inverting input of an operational amplifier 400. The operational amplifier 400 generates a negative voltage at its output, -V.sub.o, which has a magnitude that is proportional to the average output voltage sensed on the lines 58a, 58b, 58c. The -V.sub.o signal is transmitted to the summing point 370.

The summing point 370 is also connected to a circuit 402 that generates a predetermined reference voltage, V.sub.ref. The V.sub.ref voltage represents the desired voltage at which the transformer output lines 28a-c should be kept. At the summing point 370, the V.sub.ref, -V.sub.o, and -I.sub.o signals are summed to produce an error signal, V.sub.err, which equals V.sub.ref -I.sub.o -V.sub.o. In normal operation, when the magnitude of the summing transformer output current is below the predetermined current threshold, the value of -I.sub.o will be zero, and the error signal will equal V.sub.ref -V.sub.o. However, if the output current exceeds the threshold, then I.sub.o will be a nonzero value, and it will effectively reduce the magnitude of the predetermined voltage, V.sub.ref. If the overcurrent is large enough, the magnitude of I.sub.o will become as large as V.sub.ref, and the effective reference voltage, V.sub.ref -I.sub.o, will become zero. As a result, the actual voltage V.sub.o will be reduced to zero. The amount of sensed current necessary to reduce the effective reference voltage to zero is three times the rated current for the system 10. Thus, when the current reaches three times the rated current, the output voltage on the lines 28a-c drops to zero.

The summed error voltage at the summing point 370 is input to the inverting input of an operational amplifier 404 which integrates the error. The amplifier 404 is coupled to an operational amplifier 406 that acts as a buffer and which produces the .PHI..sub.c signal, which ultimately determines the phase relationships of the waveforms generated by the three subinverter pairs 30, 32, 34.

Referring to FIG. 14, the magnitude of the phase control signals .PHI..sub.c2 and .PHI..sub.c3 is shown in the two modes of operation of the inverter 24 with respect to the magnitude of the .PHI..sub.c signal. During the first mode, the .PHI..sub.c2 signal has a constant voltage that produces a phase angle of 15.degree. between the waveforms of the first subinverter pair 30 and the waveforms of the second subinverter pair 32. In this mode the .PHI..sub.c3 signal has a voltage that gradually increases to cause a gradually increasing phase angle between the second and third subinverter pair waveforms, until it hits a peak voltage sufficient to cause a 120.degree. phase angle.

During the second mode of operation, the voltage of the .PHI..sub.c3 signal stays at its peak, and the voltage of the .PHI..sub.c2 signal gradually increases until it reaches a maximum voltage sufficient to cause a phase angle of 120.degree. between the waveforms of the first subinverter pair 30 and the waveforms of the second subinverter pair 32.

Modifications and alternative embodiments of the invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description is to be construed as illustrative only, and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which come within the scope of the appended claims is reserved.