Method for Forming Protective Barrier on Silicided Regions

FIGS. 1 through 10 are sideview schematic diagrams showing the processing steps of a preferred embodiment of the present invention wherein a platinum silicide protective layer is formed on the surface of a titanium disilicide region.

FIGS. 1 through 10 are sideview schematic diagrams showing a preferred embodiment of the present invention. In FIGS. 1 through 10, a protective layer is formed on the surface of a source/drain of a field effect transistor. As will become apparent to those skilled in the art in light of this specification, the use of the invention is not limited to that of source/drains in field effect transistors or to field effect transistors at all. The invention has wide applicability in all areas of integrated circuit fabrication.

FIG. 1 shows the initial steps of the preferred embodiment. Substrate 10 is a crystalline silicon substrate. Substrate 10 is a P type substrate in the described embodiment, however the doping type of the substrate does not play a significant part in the present process. For example, substrate 10 could be N type. Thick field silicon dioxide region 16 is formed by local oxidation of silicon using a process such as that shown in Havemann, et al., U.S. Pat. No. 4,541,167, issued Sept. 17, 1985 and assigned to the assignee of this application. Substrate 10 is then subjected to thermal oxidation in a steam environment for approximately 7 minutes at a temperature of approximately 850.degree. C. to form silicon dioxide layer 12 as shown in FIG. 1. Polycrystalline silicon layer 14 is then deposited using chemical vapor deposition to a thickness of approximately 4,500 Angstroms. Polycrystalline silicon layer 14 is then patterned using common photolithographic techniques. The structure of FIG. 1 is then subjected to an ion implantation of phosphorous ions having a density of approximately 2.times.10.sup.13 ions per centimeter.sup.2 and an energy of approximately 80 kiloelectron volts. This ion implantation is annealed to form lightly doped region 18 as shown in FIG. 1. Lightly doped region 18 is selected as an N type region to be opposite with the doping level of substrate 10. The doping type or level of this doped region does not impact practice of the invention itself but is specific to the described embodiment of the invention.

A layer of silicon dioxide 20 is the formed on the surface of the structure of FIG. 1 as shown in FIG. 2. Silicon dioxide layer 20 is conformally deposited using low pressure chemical vapor deposition. Silicon dioxide layer 20 is then etched using a mixture of oxygen, C.sub.2 F.sub.6, CHF.sub.3 and helium. The etching is conducted until the portion of silicon dioxide layer 12 overlying doped region 18 is cleared as shown in FIG. 3. In addition, silicon dioxide sidewall layer 22 is formed because of the nature of anisotropic etching. The resulting structure is shown in FIG. 3. The structure of FIG. 3 is subjected to a double ion implantation of arsenic and phosphorous ions. The arsenic ions are implanted at a density of approximately 3.times.10.sup.15 ions per centimeter.sup.2 and an energy of approximately 150 kiloelectron volts. The phosphorous ions are implanted at a density of approximately 4.times.10.sup.14 ions per centimeter.sup.2 and an energy of approximately 85 kiloelectron volts. This ion implantation forms doped region 24 as shown in FIG. 3.

A layer of titanium is then deposited by sputter deposition in a surface of the structure of FIG. 3 as shown in FIG. 4. Lightly doped region 18 and doped region 24 are combined to provide source/drain region 26 for convenience of description. The structure of FIG. 4 is then subjected to an annealing process at a temperature of approximately 625.degree. C. to 675.degree. C. in a nitrogen environment. A portion of titanium layer 28 reacts with silicon substrate 10 and polycrystalline silicon gate 14 to form titanium disilicide regions 30 and 32 as shown in FIG. 5. The unreacted portion of titanium layer 28 reacts with the nitrogen environment to form titanium nitride. This process is described in more detail in Lau, U.S. Pat. No. 4,545,116, issued Oct. 8, 1985 and assigned to the assignee of this application. The titanium nitride is removed by wet etching leaving titanium disilicide layers 30 and 32 as shown in FIG. 5. A layer of platinum 34 is then deposited on the surface of the structure of FIG. 5 as shown in FIG. 6. The structure of FIG. 6 is then subjected to an annealing step, preferably in a low temperature of approximately 450.degree. C. to 525.degree. C. but temperatures of up to 600.degree. C. may be advantageously used. The lower temperature anneal is selected to minimize diffusion of dopants in source/drain 26, for example. Other temperatures and a wide range of anneal times may be used, but the lower temperature is preferred. The unreacted portion of platinum layer 34 is then removed by wet etching in aqua regia leaving the structure of FIG. 7 having platinum silicide regions 36 and 38. Platinum silicide regions 36 and 38 are approximately 150 Angstroms thick and are formed along the exposed portions of titanium disilicide regions 30 and 32. Platinum silicide is more robust than titanium disilicide. Thus, platinum silicide regions 36 and 38 provide a protective layer over titanium disilicide regions 30 and 32.

An inter-level oxide layer 40 is then deposited on the surface of the structure of FIG. 7 to a thickness of approximately 10,000 Angstroms using low pressure chemical vapor deposition. A layer of photoresist is formed and patterned on the structure of FIG. 8 as shown in FIG. 9. Photoresist 42 provides an etch mask for the formation of via 44 which provides an opening to the surface of platinum silicide layer 36. Silicon dioxide layer 40 is etched using a mixture of oxygen, C.sub.2 F.sub.6, CHF.sub.3 and helium. Because this etching process is highly selective to platinum silicide, and is less selective to titanium disilicide, platinum silicide layer 36 provides a protective layer to protect the integrity of not only titanium disilicide layer layer 30 but source/drain region 26. In the absence of platinum silicide layer 36, formation of via 44 might etch completely through titanium disilicide layer 30 and source/drain region 26 to substrate 10. Photoresist layer 42 is then removed using common ashing and wet removal techniques and a conductive layer 46, for example a tungsten layer, is deposited on the surface of inter-level oxide layer 40 and into via 44 to provide contact at a surface of platinum silicide surface 36. If during the formation of via 44, titanium disilicide layer 30 and source/drain region 26 were etched through to substrate 10, conductive layer 46 would make direct contact to substrate 10 and the circuit containing the portion of FIG. 10 would be inoperable.

Although specific embodiments of the present invention are herein described, they are not to be construed as limiting the scope of the present invention. For example, although the preferred embodiment shows the use of protective platinum silicide layer 36 on the surface of titanium disilicide layer 30, platinum layer 36 can provide protective functions in other circumstances than the formation of vias to doped regions. For example, platinum silicide layer 38 may provide protection for titanium disilicide layer 32 during planarization of interlevel oxide layer 40 on the surface of the integrated circuit. Many embodiments of the present invention will become clear to those skilled in the art in light of the teachings of the specification. The scope of the invention is limited only by the claims appended hereto.