TTL-ECL Level Converting Circuit

1. Field of the Invention

The present invention relates to a TTL-ECL converting circuit, and more specifically to a TTL-ECL converting circuit which operates at a high speed and which is free from self-oscillation.

2. Description of Related Art

Recently, ECL (emitter coupled logic) circuits in the form of an integrated circuit having a high integration density have been used in various fields requiring a high speed operation, for example, so-called main frames, communication instruments, LSI testers, measuring instruments, etc. In many cases, however, the above mentioned instruments are provided, as a memory, with an inexpensive standard semiconductor memory having a TTL (transistor-transistor logic) interface. Therefore, an interface of the ECL integrated circuit having a high integration density has been provided with a TTL-ECL level converting circuit, and therefore, both an ECL interface and a TTL interface have been assembled within a single LSI chip.

However, the conventional TTL-ECL level converting circuits have been disadvantageous in that a base potential of a transistor receiving a TTL input signal is apt to cause vibration, and the vibrating voltage is propagated as noises to an ECL level output signal. The noise has the possibility of causing a next stage of ECL circuit to malfunction.

Furthermore, the conventional TTL-ECL level converting circuits have a logical amplitude of the ECL output signal much larger than the logical amplitude in ordinary ECL circuits. Therefore, the propagation delay time is inevitably large.

Accordingly, it is an object of the present invention to provide a TTL-ECL level converting circuit which has overcome the above mentioned defect of the conventional one.

Another object of the present invention is to provide a TTL-ECL level converting circuit free from a self vibration, so as to avoid possibility of causing a next stage of ECL circuit to malfunction.

A further object of the present invention is to provide a TTL-ECL level converting circuit outputting an ECL output signal having a logical amplitude comparable to the logical amplitude in ordinary ECL circuits.

The above and other objects of the present invention are achieved in accordance with the present invention by a TTL-ECL converting circuit comprising a Schottky barrier diode having a cathode connected to an input terminal for a TTL signal and an anode connected to a first connection node, a resistor having its one end connected to a high voltage supply line and its other end connected to the first connection node, a first transistor having a collector connected to the high voltage supply line, a base connected to the first connection node and an emitter connected to a second connection node, a first level shift means having its one end connected to the second connection node and its other end connected to a third connection node, a second level shift means having its one end connected to the third connection node and its other end connected to a fourth connection node, a constant current source having its end connected to the fourth connection node and its other end connected to a low voltage supply line, a second transistor having a collector connected to the first connection node, a base connected to the third connection node and an emitter connected through another resistor to an intermediate voltage supply line, and an emitter follower connected between the intermediate voltage supply line and the low voltage supply line and having an input connected to the fourth connection node and an output connected to an output terminal for an ECL signal.

The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a conventional TTL-ECL level converting circuit;

FIG. 2 is a circuit diagram of one embodiment of the TTL-ECL level converting circuit in accordance with the present invention;

FIGS. 3A, 3B and 3C are circuit diagrams illustrating various modifications of the TTL-ECL level converting circuit shown in FIG. 2; and

FIGS. 4A and 4B are voltage waveform diagrams illustrating the operation of the circuit shown in FIG. 2 and a comparative circuit.

Referring to FIG. 1, there is shown a circuit diagram of a conventional TTL-ECL level converting circuit. The shown circuit includes an input terminal IN for receiving a TTL level signal and an output terminal OUT for outputting an ECL level signal. The input terminal IN is connected to a cathode of a Schottky barrier diode D.sub.1, whose anode is connected to one end of a resistor R.sub.1, a base of a first transistor Q.sub.1 and a collector of a second transistor Q.sub.2, respectively. The other end of the resistor R.sub.1 and a collector of the first transistor Q.sub.1 are connected to a high voltage supply line V.sub.CC. An emitter of the first transistor Q.sub.1 is connected to a low voltage supply line V.sub.EE through a diode D.sub.21, a resistor R.sub.31 and a constant current source Ics. In addition, an emitter of the second transistor Q.sub.2 is connected to a ground line GND, and a base of the second transistor Q.sub.2 is connected through a resistor R.sub.21 to a connection node between the diode D.sub.21 and the resistor R.sub.31. Another Schottky barrier diode D.sub.31 is connected between the ground line GND and the connection node between the diode D.sub.21 and the resistor R.sub.31. Furthermore, there is provided a third transistor Q.sub.3 having a collector connected to the ground line GND, and a base connected to a connection node between the resistor R.sub.31 and the constant current source Ics. An emitter of the third transistor Q.sub.3 is connected through a resistor R.sub.4 to the low voltage supply line V.sub.EE and is also connected to the output terminal OUT.

Now, an operation of the above mentioned TTL-ECL level converting circuit will be explained. A TTL level signal applied to the input terminal IN is level-shifted by the diode D.sub.1, the transistor Q.sub.1, the diode D.sub.21 and the resistor R.sub.31, and outputted as an ECL level signal from the output terminal OUT through an emitter follower formed of the transistor Q.sub.3 and the resistor R.sub.4.

The ECL level signal is set as follows: When the TTL level signal of a high level V.sub.IH is inputted, the transistor Q.sub.1, the diode D.sub.21 and the transistor Q.sub.2 are brought into an on condition, and on the other hand, the diode D.sub.1 is brought into an off condition. If a forward direction voltage of diodes and transistors is expressed by V.sub.F, this input voltage V.sub.IH must fulfil the following condition (1) in order to render the diode D.sub.1 off:

In general, the forward direction operating voltage V.sub.F is 0.8 V in diodes and transistors and 0.4 V in Schottky barrier diodes, and therefore, the high level condition becomes stable if V.sub.IH .gtoreq.2.0 V. In this condition, the high level output V.sub.OH of the ECL level signal is expressed by the following equation (2):

where Ics is a current value of the constant current source Ics)

On the other hand, when the TTL level signal of a low level V.sub.IL is inputted, the diodes D.sub.1 and D.sub.31 are brought into an on condition, and the transistor Q.sub.2 is brought into an off condition. In this condition, in order to ensure the on condition of the diode D.sub.1, the input voltage V.sub.IL must fulfil the following condition (3):

Therefore, the low level condition becomes stable under the condition of of V.sub.IL .ltoreq.0.8 V.

In this condition, a low level output V.sub.OL of the ECL level signal is expressed by the following equation (4):

As seen from the equations (2) and (4), the ECL level output of the circuit shown in FIG. 1 has a logical amplitude (a difference between V.sub.OH and V.sub.OL) corresponding to the sum of the forward direction operating voltage of one transistor and the forward direction operating voltage of one Schottky barrier diode (about 1.2 V).

In the circuit shown in FIG. 1, when the input TTL level signal is brought from the low level to the high level, a base potential of the transistor Q.sub.1 is elevated to follow the input TTL level signal, and the elevating potential is level-shifted by the transistor Q.sub.1, the diode D.sub.21 and the resistor R.sub.21 and applied to the base of the transistor Q.sub.2 so as to cause to turn on the transistor Q.sub.2. Namely, an current flows through the resistor R.sub.1 with the result that a balanced and stable condition is established. In the above mentioned process, a propagation delay will occur in the course of the level shifting, and therefore, the base potential of the transistor Q.sub.1 is apt to cause vibration due to a delay of the turning-on of the transistor Q.sub.2 and a voltage drop caused across the resistor R.sub.1 by an abruptly increasing operation current.

Specifically, when the input signal on the input terminal IN changes from the low level to the high level, the base potential of the transistor Q.sub.1 elevates towards a potential of the high voltage supply V.sub.CC through the resistor R.sub.1. This elevated voltage is propagated to the base of the transistor Q.sub.2 through the transistor Q.sub.1, the diode D.sub.21 and the resistor R.sub.21 with a delay corresponding to a propagation delay time of these elements. As a result, the current of the transistor Q.sub.2 is increased, and a collector potential of the transistor Q.sub.2 is correspondingly decreased due to a voltage drop across the resistor R.sub.1. The drop of the collector potential of the transistor Q.sub.2 is propagated to the base of the transistor Q.sub.2 after a constant delay time, so that the base potential of the transistor Q.sub.2 is decreased, and therefore, the collector current of the transistor Q.sub.2 is correspondingly decreased. As result, the collector potential of the transistor Q.sub.2 is elevated at this time.

The above mentioned operation is repeated and therefore the base potential of the transistor Q.sub.1 fluctuates or vibrates. This vibration waveform is level-shifted, and thereafter, is propagated as noises to the high level of the ECL level output signal. The noise has the possibility of cause a next stage of ECL circuit to malfunction.

Furthermore, the circuit shown in FIG. 1 has the logical amplitude of the ECL output signal corresponding to the sum of the forward direction operating voltage of one transistor Q.sub.2 and the forward direction operating voltage of one Schottky barrier diode D.sub.31. This logical amplitude of the ECL output signal is much larger than a logical amplitude of 0.6 V in ordinary ECL circuits. Therefore, the propagation delay time inevitably becomes large.

Referring to FIG. 2, there is shown a circuit diagram of one embodiment of the TTL-ECL level converting circuit in accordance with the present invention. In FIG. 2, elements similar or corresponding to those shown in FIG. 1 are given the same Reference Characters, and explanation thereof will be omitted for simplification of description.

As seen from FIG. 2, a level shift circuit in the conversion circuit shown FIG. 2 connected to the emitter of the transistor Q.sub.1 is composed of a series circuit consisting of a resistor R.sub.3 and a diode D.sub.2 in such a manner that the resistor R.sub.3 is connected at its one end to the emitter of the transistor Q.sub.1 and at its other end to an anode of the diode D.sub.2, and a cathode of the diode D.sub.2 is connected to the current source Ics. A connection node between the resistor R.sub.3 and the diode D.sub.2 is connected directly to the base of the transistor Q.sub.2. In addition, a resistor R.sub.2 is connected between the emitter of the transistor Q.sub.2 and the ground line GND. A cathode of an anode-grounded diode D.sub.3 for low level clamping is connected to the cathode of the diode D.sub.2 which forms an output end of the level shift circuit.

Now, an operation of the TTL-ECL level converting circuit shown in FIG. 2 will be explained. When the TTL level input signal is at a high level V.sub.IH, the transistors Q.sub.1 and Q.sub.2 and the diode D.sub.2 are brought into an on condition, and on the other hand, the diodes D.sub.1 and D.sub.3 are brought into an off condition. In other words, an operation current of the transistor Q.sub.2 flows through the resistor R.sub.1 so that an anode potential of the diode D.sub.1 is maintained at a constant level. Therefore, a voltage difference V(D.sub.1) between the anode potential of the diode D.sub.1 and the high level of TTL level signal applied at the cathode of the diode D.sub.1 becomes smaller than the forward direction operation voltage V.sub.F (D.sub.1) of the diode D.sub.1, and therefore, the diode D.sub.1 is turned off. With this, the status is balanced. In this condition, the operating current I.sub.F (Q.sub.2) of the transistor Q.sub.2 is expressed by the following equation (5):

In addition, the voltage difference V(D.sub.1) applied across the Schottky barrier diode D.sub.1 is expressed by the following equation (6):

A condition for maintaining the Schottky diode D.sub.1 in an off condition can be expressed by the following equation (6a):

Here, assuming V.sub.F (Q.sub.1)=V.sub.F (Q.sub.2)=0.8V, R.sub.3 =2K.OMEGA., Ics=0.3mA, R.sub.2 =1K.OMEGA., V.sub.CC =5V, R.sub.1 =20K.OMEGA., V.sub.IH .gtoreq.2.0V, and V.sub.F (D.sub.1)=0.4V, the above mentioned condition is fulfilled.

In this case, the high level V.sub.OH of the ECL level output is expressed by the following equation (7):

On the other hand, when the TTL level signal of a low level V.sub.IL is inputted, the diodes D.sub.1 and D.sub.3 are brought into an on condition, and the transistor Q.sub.2 is brought into an off condition. In this condition, the cathode potential of the diode D.sub.2 becomes a low voltage sufficient to turn on the diode D.sub.3. The condition for this is expressed by the following equation (8):

Here, assuming V.sub.IL .ltoreq.0.8V, V.sub.F (D.sub.1)=0.4V, V.sub.F (Q.sub.1)=V.sub.F (D.sub.2)=V.sub.F (Q.sub.3)=0.8V, R.sub.3 =2K.OMEGA., and Ics =0.3mA, the above mentioned condition (8) is fulfilled.

In this condition, a low level output V.sub.OL of the ECL level signal is expressed by the following equation (9):

As seen from the above equations (7) and (9), the logical amplitude of the ECL output signal of the converting circuit shown in FIG. 2 is expressed by the following equation (10):

Here, if I.sub.F (Q.sub.2) is calculated in accordance with the equation (5) in the example in which the respective elements have the above mentioned values, respectively, the logical amplitude of the ECL level output signal of the converting circuit shown in FIG. 2 have about 0.93 V, which is apparently smaller than that of the circuit shown in FIG. 1. In addition, if a Schottky barrier diode is used as the diode D.sub.3 and the value of the resistor R.sub.2 is 1.5K.OMEGA., the logical amplitude of the ECL level output signal can be reduced to 0.6 V under the condition that the equations (6a) and (8) are fulfilled.

Next, a vibration restraining effect obtained by inserting the resistor R.sub.2 between the emitter of the transistor Q.sub.2 and the ground line GND will be explained on the basis of a result of simulation. FIG. 4A shows a graph illustrating voltage variations on various points in the converting circuit shown in FIG. 2 in which the resistor R.sub.2 is removed and the emitter of the transistor Q.sub.2 is directly connected to the ground line GND. FIG. 4B is a graph illustrating voltage variations on various points in the converting circuit shown in FIG. 2. These figures show transitions when the TTL input signal is brought from the low level to the high level. In each of these figures, the line A shows the TTL level input signal, and the line B shows the base potential of the transistor Q.sub.1. The lines C, D and E indicate the cathode potential of the diode D.sub.2, the ECL level output signal, and a reference voltage for the ECL level signal, respectively. In addition, the values of the respective elements used in the circuit for the simulation are in accordance with the values as mentioned hereinbefore.

As shown in FIG. 4A, in the case of no resistor R.sub.2, the base potential of the transistor Q.sub.2 greatly vibrates, and therefore, the ECL level output signal correspondingly vibrates. If this vibration exceeds the reference voltage for the ECL level signal indicated by the line E, a malfunction will occur. On the other hand, in th circuit shown in FIG. 2, the vibration of the base potential of the transistor Q.sub.1 is almost perfectly restrained, and therefore, there is little possibility of malfunction.

Turning to FIGS. 3A, 3B and 3C, there are shown some modifications of the level shift circuit portion of the converting circuit shown in FIG. 2.

In the modification shown in FIG. 3A, the level shift circuit is composed of a series circuit consisting of two diodes D.sub.21 and D.sub.2. In this modified converting circuit, since the level shift circuit is composed of a low impedance circuit formed of only the diodes, the propagation delay can be shortened to a minimum extent.

In the modification shown in FIG. 3B, the level shift circuit is composed of a series circuit consisting of two resistors R.sub.3 and R.sub.32. In this modified converting circuit, since the constant current flows through the resistors of the level shift circuit, a temperature dependency of the threshold of the converting circuit is eliminated. Ordinarily, the forward direction operating voltage of diodes and transistors has the temperature dependency of about 2 mV/.degree.C. In the circuit shown in FIG. 2, the temperature dependencies of the Schottky barrier diode D.sub.1 and the transistors Q.sub.1 are countervailed or compensated to each other. In the modification shown in FIG. 3B, on the other hand, the level shift circuit does not have a temperature dependency. As a result, the converting circuit modified in accordance with the modification shown in FIG. 3B has the threshold with no temperature dependency. This is very advantageous in that even if the converting circuit and an ECL circuit which generates a large amount of heat due to power consumption are integrated in the same chip, the converting circuit maintains its threshold at a constant level regardless of temperature change.

In the modification shown in FIG. 3C, the level shift circuit is composed of a series circuit consisting of a diode D.sub.21 and a resistor R.sub.32 in such a manner that the diode D.sub.21 is connected at its anode to the emitter of the transistor D.sub.21 and at its cathode to one end of the resistor R.sub.32 and the base of the transistor Q.sub.2. This modified converting circuit has an excellent balance concerning both of the delay time and the threshold temperature dependency.

The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.