Visual Aid for the Hearing Impaired

The invention described herein was made in the performance of work under a NASA contract and by an employee of the United States Government and is subject to Public Law 96-517 (35 U.S.C. .sctn.200 et seq.). The contractor has not elected to retain title to the invention.

The invention relates generally to hearing aid apparatus and more particularly to a multi-channel electronic device for the hearing impaired or deaf providing a visual indication as to directivity and loudness of the sounds received.

This invention has particular utility in providing hearing impaired persons with an indication not only of specific sounds, but the direction from which they emanate. A common but very difficult problem exists among individuals who are totally deaf in one ear. While these individuals are able to hear adequately with hearing aid devices, they are unable to quickly discern the direction from which the sound originates. Normally this is not a life threatening problem. Situations, however, do exist where such individuals must be made immediately aware of the origin of the sound, particularly a loud sound. Typical examples include general automobile traffic, fire alarms, loading dock traffic, sirens and variety of less common audibles, but of equal warning power. Recent contact with such individuals having this type of hearing disability has dramatically emphasized the severity of the problem. In addition, people who are totally deaf or hearing impaired encounter difficulties while operating a motor vehicle with respect to hearing and locating an emergency vehicle in the vicinity.

It is an object of this invention to provide an improvement in visual aids for the hearing impaired or deaf.

It is another object of this invention to provide a visual aid which is directionally sensitive.

It is a further object of this invention to provide an improvement in visual aids which are able to detect not only the direction from which the sound originates, but also to provide a visual indication of both the direction and intensity of the sounds.

It is still another object of this invention to provide a directional visual aid comprised of integrated circuits in order to minimize size and power dissipation.

The foregoing and other objects of the invention are achieved by a multi-channel electronic, usually indicating device which is able to signal to the wearer in a binaural or a quadraphonic configuration whether sound is coming from the left or right, front or back, or both. For each channel, which operate in pairs, the sound is picked up by a respective microphone amplified and rectified into a DC voltage. The DC voltage is next fed to a three bit analog to digital converter comprised of seven parallel comparators and an eight by three encoder. The three bit binary codes from the encoder are coupled into a logic circuit where the three bit binary codes are decoded to seven output levels which are used to drive an indicator which provides a visual indication of the sound level received. The three bit binary codes for each pair of channels are also fed into a digital comparator. The output of the comparator is used to enable the logic circuits of the two channels such that if, for example, the signal coming from the right is louder than that coming from the left, the outputs of the logic unit of the right channel will be enabled and the corresponding indicator activated, indicating the direction of the sound source. Also an indication of the loudness is provided for that channel. Our preferred embodiment only gives an indication for the stronger channel because it is deemed that a multiple channel indication, with relative volumes being indicated, would lead to confusion.

FIG. 1 is a perspective view generally illustrative of a four channel or quadraphonic visual aid in accordance with the subject invention which is carried by a pair of eyeglasses;

FIG. 2 is a perspective view generally illustrative of a two channel or visual aid in accordance with the subject invention which is carried by a sun visor which is worn by the user;

FIG. 3 is an electrical block diagram illustrative of the circuitry included in the preferred embodiment of a two channel visual aid in accordance with the subject invention;

FIG. 4 is a partial electrical schematic further illustrative of the block diagram shown in FIG. 3;

FIG. 5 is an electrical schematic diagram illustrative of the analog to digital converter shown in FIG. 4;

FIG. 6 is an electrical schematic diagram illustrative of the 8.times.3 digital encoder shown in FIG. 4;

FIG. 7 is an electrical schematic diagram illustrative of the digital comparator circuit shown in FIG. 4; and

FIG. 8 is an electrical schematic diagram illustrative of one of the digital logic units shown in FIG. 4.

FIG. 9 is an electrical block diagram generally illustrative of a three channel, vehicle mounted visual aid for receiving signals from an emergency vehicle in accordance with the invention.

With respect to the drawings wherein like reference numerals refer to like components throughout, FIG. 1 discloses a directional visual aid included in the frame 10 a pair of eyeglasses. The configuration of FIG. 1, moreover, is intended to illustrate the concept of a directional visual aid wherein the wearer can be visually alerted to sounds coming from four directions, namely left, right, front and rear. Further as shown the left and right temples 12 and 14 have a pair of front and rear directional microphones 16, 18, and 20, 22, respectively, mounted thereon. The left temple 12, moreover, includes a battery compartment 24 and an amplifier module 26 for the microphones 16 and 20. The right temple in addition to including an amplifier module 28 for the microphones 18 and 22 also includes a logic unit 30 which includes integrated circuitry of the type to be described hereinafter to detect the direction from which sounds are received and drive four light emitting diode (LED) devices, two of which 32 and 34 are located in the left lens rim 36 while the other two 38 and 40 are located in the right lens rim 42. Although this embodiment describes a display system based on LED devices, other types of indicators could be implemented, such as vibrating tactile devices. The LED 32, in the example, would be used to display the existence of sounds coming from the front left of the wearer, while LED 34 would be used in indicate sounds coming from the left rear. In the same fashion, the LED 38 would indicate sounds coming from the right front, while the LED 40 would indicate sounds coming from the right rear. The brightness of the light generated by four LED's would be further modulated to indicate the loudness of the respective sounds coming from the four directions.

It should be recognized that while FIG. 1 illustrates an embodiment of the invention where the support means for the electronics are a pair of eyeglasses and the LED's integrated with the frame, neither LED's nor frame integration are critical. Other types of visual indicators could be used and, for example, could be integrated into the lenses.

Referring now to FIG. 2, there is disclosed a binaural or two channel embodiment of the invention which is supported by a piece of headwear such as a sun visor 44. It could, however, be included in a cap of any desired type. What is significant is that left and right directional microphones 46 and 48 are located on the left and right side of the head of the wearer. As shown, the microphones 46 and 48 are located along the temple members 50 and 52 of the visor and are coupled by means of electrical wiring 54 to a composite battery and electronic package 56. On the forehead band portion 58 on the outer extremity thereof, there is located a pair of light bar display elements 60 and 62 which are for the purpose of providing an indication of sound coming from either the left or right direction and the loudness or intensity thereof.

Turning attention now to the electronics circuitry for implementing either of the two embodiments shown in FIG. 1, FIG. 3, for example, discloses a block diagram for a two channel system for detecting sounds coming from the left and right It should be understood, however, that the same circuitry would merely be duplicated for a four channel system where front and back directivity is desired.

Considering FIG. 3, the left and right microphones 46 and 48 of FIG. 2, are coupled to respective audio amplifiers 64 and 66. The output of each of the amplifiers 64 and 66 are connected to electrical resistive potentiometer elements 68 and 70 for providing means for adjusting the output level or volume for each of the signal channels. The slider portions of the two potentiometers 68 and 70 are respectively coupled to a pair of rectifiers 72 and 74 which provide a DC voltage output. The respective DC outputs of the rectifiers 72 and 74 are fed to an analog to digital converter and encoder 76 and 78. A digital comparator and logic circuit 80 is coupled to the digitally encoded output of the circuit components 76 and 78 and operates to determine which of the two inputs is of a greater magnitude and to enable an output from the channel having the greater magnitude. Seven levels of magnitude are coupled to an enabled driver 82 or 84 which controls the left and right indicators 60 and 62 comprising the bar display elements shown in FIG. 2 to indicate the level of the sound received in that particular channel.

The details of the circuitry shown in FIG. 3 are disclosed in the remaining FIGS. 4 through 8. Considering now FIG. 4, the input amplifiers 64 and 66 are shown comprising operational amplifiers with signal inputs from the microphones 46 and 48 being applied to the non-inverting (+) inputs thereof. The output of the operational amplifiers shown in FIG. 4 are coupled to diode rectifiers 72 and 74 between which are located the potentiometers 68 and 70. The connections shown in FIG. 4 vary slightly from that shown in FIG. 3 in that the slider elements are coupled back to the inverting (-) inputs of the operational amplifiers 64 and 66. In addition, filter capacitors 73 and 75 are shown coupled from the output of the rectifier diodes 72 and 74 to ground.

The analog to digital converter and encoder circuits 76 and 78 are shown further comprising analog to digital converter blocks 86 and 88, which provide seven outputs. These outputs are fed to 8.times.3 digital encoders 90 and 92 which provide three outputs each and which are, in turn, coupled to a digital comparator circuit 94, and a pair of logic units 96 and 98 which include seven outputs each.

As shown in FIG. 5, each analog to digital converter 86 and 88 is comprised of seven parallel signal comparators comprised of operational amplifiers 100, 102 . . . 110, 112 whose non-inverting inputs are commonly coupled to the input voltage from a diode rectifier (FIG. 4) and dropped across resistor 114. The inverting inputs are coupled to selected equal valued voltage points of a voltage divider network 116 consisting of a series string of fixed resistors 118 coupled between a positive source of voltage and ground. The A/D converter operates to convert the analog DC input signal appearing on circuit lead 119 to a 7-bit digital output code D.sub.6, D.sub.5 . . . D.sub.1, D.sub.0 at terminals 120 . . . 131 which ranges in value from 0000001 to 111111 according to the magnitude of the input signal.

Further, as shown in FIG. 4, seven output leads from the A/D converters 86 and 88 are respectively fed to seven inputs D.sub.0, D.sub.1 . . . D.sub.6 of two identical 8.times.3 encoders 90 and 92 which translates the seven bit outputs of the respective A/D converters into respective three bit binary codes B.sub.0, B.sub.1, B.sub.2 and A.sub.2, A.sub.1 and A.sub.0.

Referring now to FIG. 6, there is shown the details of one of the encoders, i.e. encoder 92, which provides outputs of A.sub.0, A.sub.1, and A.sub.2. The encoder is comprised of four signal inverters 132, 134, 136, 138 coupled to signal input lines D.sub.1, D.sub.3, D.sub.5, D.sub.2, respectively. Four NAND gates 140, 142, 144 and 146 have one input respectively coupled to the input line D.sub.0, D.sub.2, D.sub.4 and D.sub.1 while their other inputs are connected to the outputs of the inverters 132, 134, 136 and 138. A set of four intermediate logic inverters 148, 150, 152 and 154 are coupled to the output of the NAND gates 140, 142, 144 and 146 which selectively couple into a pair of NOR gates 156 and 158 along with the input lines D.sub.5 and D.sub.6. The output of the NOR gate 156 is fed through three logic inverters 160, 162 and 164 where the output A.sub.0 appears at terminal 165. The output of the NOR gate 158 is fed through three logic inverters 166, 168 and 170 where the output A.sub.1 is provided at terminal 171. The third output A2 is provided at terminal 175 by a pair of series connected logic inverters 172 and 174 connected to input line D.sub.3.

The following truth table illustrates the three bit binary code which is generated in response to the six inputs D.sub.0 . . . D.sub.6.

Next, the digital comparator 94 is shown in FIG. 7 and is used to compare the signals being conducted in the left and right channels to generate control signals A<B, A>B and A=B to enable the logic units 96 and 98. The comparator as shown in FIG. 7 includes three pairs of input lines for the signals A.sub.0, B.sub.0 . . . A.sub.2, B.sub.2. These signals are fed to respective signal inverters 176, 178, 180, 182, 184 and 186 with cross coupled inputs and outputs of the logic inverters being fed to six NAND gates 188, 190 198. Adjoining pairs of NAND gate outputs are next fed to three NAND gates 200, 202 and 204 and which are also respectively connected to six intermediate logic inverters 206, 208 . . . 216. The outputs of the NAND gates 200, 202 and 204 are coupled to respective logic inverters 218, 220 and 222. Five NAND gates 224, 226 . . . 232 are selectively coupled to the logic inverters 218, 210, 212, 214, 216 and 222. Next a pair of NOR gates 234 and 236 are included with the NOR gate 234 having inputs connected thereto from the output of the logic inverter 206 and the two NAND gates 224 and 228. The second NOR circuit receives inputs from the logic inverter 208 and the two NAND gates 226 and 230. A logic inverter 238 is coupled to the output of the NOR gate 234 and provides an output when A<B and is fed as an enabling signal to the logic unit 96 (FIG. 4).

In a like manner, logic gate 240 is coupled to the output of the NOR gate 236 and provides an output when the signal A>B and comprises an enabling signal which is coupled to the logic unit 98. The output of the NAND gate 232 is coupled to a third logic inverter 242 whose output comprises a signal A =B. Under such circumstances, an enabling signal is fed to both logic units 96 and 98. The operation of the comparator circuit shown in FIG. 7 can readily be understood with reference to the following Truth Table II. FIG. 9 represents another embodiment of the invention which provides a solution to a significant problem encountered by the deaf or hearing impaired while operating motor vehicles in the vicinity of emergency vehicles. The system portrayed by FIG. 9 allows for such persons to be alerted to the emergency siren alarms through a plurality of microphones placed about the vehicle. One such system, illustrated by FIG. 9 has three microphones placed left, right and rear. The system electronics is the same as that illustrated in the prior figures except an additional channel is included for a third direction, for example, a rear facing direction. The signals from the three microphones are fed to three A/D converters, the same or similar to elements 86 and 88, depicted in FIG. 4. The outputs of these converters drive a comparator similar to that shown in FIG. 4, element 94, except that this is a three channel comparator with an enabling input. The enabling input is designed to receive an RF signal transmitted from the emergency vehicle, only allowing a display to occur when that RF input is received, thus avoiding displays caused by other sources not emanating from the emergency alarm system. The enabling input receives the signal from an RF antenna and then converts that RF signal to a DC signal by conventional methods, the DC signal being the required signal to enable the comparator. As illustrated, the enable signal controls the comparator but could be used to enable other functions of the system. The output displays the signal that is the most intense of those signals received by the microphones. The most intense signal from the comparator, once enabled, is fed to the appropriate display driver, which drivers are the same or similar to those illustrated in FIG. 3 as elements 82 and 84, that, in turn, drive the lights of the display unit which are associated with the most intense signal. Again, the lights which are lit give the hearing impaired vehicle driver an indication of the direction from which the most intense audio signal is coming.

The design of one of the logic units 96 and 98, i.e. logic unit 98, is shown in FIG. 8. These circuits function to translate the respective three bit binary codes A.sub.0, A.sub.1, A.sub.2 and B.sub.0, B.sub.1 and B.sub.2 into seven different signal output levels D.sub.0, D.sub.1 . . . D.sub.6 which are used to drive seven bit input bar display components 60 and 62 shown in FIG. 2. Logic unit 98, for example, is comprised of input lines A.sub.0, A.sub.1 and A.sub.2 which are coupled to two NOR gates 244 and 246, a logic inverter 248 and five NAND gates 250, 252 . . . 258. The outputs of the two NOR gates 244 and 246 are coupled to logic inverters 262. The output of the NAND gate 250 is connected to a first intermediate NAND gate 264 along with the output of the logic inverter 285 which is also coupled to the logic inverter 266. The outputs of the two NAND gates 252 and 254 are coupled to a second intermediate NAND gate 268. The two bottom input NAND gates 256 and 258 are coupled to respective logic inverters 270 and 272. The intermediate logic elements are respectively coupled to one input of seven output NAND gates 274, 276 . . . 286 whose other inputs are respectively connected to a common enabling signal line, which as noted above, can be the signal A<B, A>B or A=B. All seven of the output NAND gates 274, 276 . . . 286 are coupled to respective logic inverters 288, 290 . . . 300 which provide respective outputs of D.sub.0, D.sub.1 . . . D.sub.6 according to the Truth Table III set forth below.

The Boolean equations for the outputs of the logic circuits shown in FIG. 8 are:

D.sub.0 =A.sub.0 +A.sub.1 +A.sub.2

D.sub.1 =A.sub.1 +A.sub.2

D.sub.2 =A.sub.0 A.sub.1 +A.sub.2

D.sub.3 =A.sub.2

D.sub.4 =A.sub.1 A.sub.2 +A.sub.0 A.sub.2

D.sub.5 =A.sub.1 A.sub.2

D.sub.6 =A.sub.0 A.sub.1 A.sub.2

The electronic circuitry shown and described has been implemented in a custom built monolithic integrated circuit structure using 3-micron P-well CMOS technology; however, when desirable, it can readily be fabricated using other types of discrete integrated circuits well known to those skilled in the art.

Having thus shown and described what is at present considered to be the preferred embodiments of the invention, it should be noted that the same has been made by way of illustration and not limitation. Accordingly, all modifications, alterations and changes coming within the spirit and scope of the invention are herein meant to be included.