Low-Power DSP Squelch

This invention relates to squelch systems. In particular this invention relates to squelch systems used in frequency modulation (FM) receives to disable stages of the receiver when signal is absent.

Typical squelch circuits in FM receivers test the output of the discriminator and disable the output of the audio amplifier stage of the receiver when there is no signal present on the channel. These squelch circuits therefore require that the discriminator remain active in the standby mode of the receiver. While squelch circuits principally eliminate unwanted white noise from being heard at the speaker output they can also substantially extend the life of a battery powering a portable FM receiver by powering down unneeded stages in the receiver when signal is absent from the channel.

Digital signal processors (DSP's), which use relatively large amounts of power and which are becoming commonplace in FM receivers, frequently perform the function of a discriminator, a function previously performed by relatively low-power analog circuits. Powering a DSP however to continuously perform a discriminator function to squelch the radio's audio system would waste substantial amounts of power. Using a DSP squelch algorithm not requiring the output of a discriminator but permitting the DSP to be disabled when its not required could substantially extend the life of a battery powering a portable radio that uses DSP's.

A method of detecting information on an FM channel is disclosed which operates on digital samples of non-demodulated signals. The non-demodulated signal is a stream of digital complex numbers that have real and imaginary components. The real and imaginary components, denoted I and Q, are the in-phase and quadrature components respectively of a phasor that rotates about the origin of a set of Cartesian coordinates having imaginary components along the Y axis and real components along the X axis. (When an FM signal is present on a receiver channel, the phasor rotates about the origin at a rate related to the instantaneous deviation of the FM modulating signal plus the frequency offset of the modulating signal from the center frequency of the channel.) These I and Q components are digitally filtered to reduce noise components in the FM signal. The filtering removes undesired frequency components outside the bandwidth of interest at, for example, the first IF stage.

After filtering, each complex sample in the stream of samples is multiplied by the complex conjugate of a temporally adjacent sample to produce another stream of complex phasors whose angles represent the phase angle difference between the first sample and the temporally adjacent sample of which the complex conjugate was formed.

This product of a first phasor in the stream of phasors and a complex conjugate of a temporally adjacent phasor is performed repetitively on all samples output from the digital-to-analog convertor to produce the second stream of phasors. The phase angles of the phasors formed by the product of the sample and the complex conjugate of an adjacent sample are evaluated statistically to generate a numerical index or value on the probability of the channel content being noise.

The statistical evaluation of the phasors formed by the product of the sample values and the complex conjugate of the sample values numerically weights these phasors according to some appropriate algorithm and accumulates the results obtained by the operation of this algorithm on the phasor samples. The accumulation of results is used to make a decision as to whether or not the FM channel contains signal or noise. If the channel contains noise, other processing in the DSP can be disabled.

Several algorithms or weighting functions are possible as detailed below.

FIG. 1 shows a subsection of the functional blocks required of the FM receiver of the present invention.

FIG. 2 shows a function block required to perform the invention described herein.

FIG. 3 shows a set of Cartesian coordinates having imaginary and real axes.

FIG. 1 shows the functional elements of an FM receiver front end required by the preferred embodiment of the invention herein. The FM receiver includes an antenna (12), an RF amplifier that amplifies low-level signals (14), a first mixer (16) driven by a local oscillator (18) that shifts the incoming signals to a lower frequency at which the signals are filtered by the first IF (20) to suppress undesired signals and noise in the frequency band of interest.

The output of the first IF (20) is coupled to a second mixer, (30) which mixes the output of the first IF (20) with a second oscillator (32) to produce a second IF signal (34) at a frequency at which a practical A/D converter can operate. (Note that faster A/D's might be able to sample the output of the first mixer or even the output of the RF amplifier but would require more power.)

In the preferred embodiment, the second IF signal (34) is sampled by an A/D converter (40) to produce a stream of real digital numbers. The stream of real digital numbers is digitally band-pass filtered (41) and sent to a digital mixer (42) driven by a digital complex oscillator (43), which oscillates at the 2nd IF frequency. The output of the digital mixer (42) is a stream of complex digital numbers at a center frequency of 0 hz. This stream of samples may then be further low-pass filtered and decimated (44) to obtain a suitably low sample rate. (Decimating effectively divides the data rate of samples from the digital mixer (42) so that digital signal processing can be performed by slower devices.) This sample rate should be at least three to four times the maximum frequency deviation of the expected signal; higher sample rate improve speed and reliability at the cost of processing power.

In FIG. 2, the signal processing of the output of the decimating filter (44) is shown in detail. (All processing shown in FIG. 2 is in a digital format using a digital signal processor such as a Motorola 56000 DSP. Programming details of the Motorola DSP 56000 series of signal processors are available in the 56000 series user's manual, Motorola Publication No. DSP56000UM/AD rev. 1. A listing of the program for the preferred embodiment of the squelch system shown in FIG. 2 is given below.)

As described above, each complex sample in the stream of samples from the decimator (44) is multiplied (54) by the complex conjugate of a temporally adjacent sample (55) to produce a second stream of phasors (56) whose phase angles represent the differences between the phases of the two samples multiplied in the multiplier (54). (The two samples multiplied in the multiplier are actually pairs of samples, being a first sample and the complex conjugate of a temporally adjacent second sample. The temporal ordering of the first and second samples from the decimator is arbitrary. The complex conjugate sample can either temporally precede or follow the other sample.) These phase differences can be considered to be the instantaneous deviation of the frequency of the received signal or noise from the center of the channel. When there is an FM signal on the channel, the deviation is limited by the transmitter and should be less than the maximum allowable deviation depending on the channel specification. If there is noise on the channel, the deviation is not limited since noise does not have the constant-envelope property of a frequency-modulated signal and the phase (56) output from the multiplier (54) may even pass through or near the origin (I=0, Q=0) at any time, resulting in large instantaneous frequency deviations.

To determine whether the channel contains noise, this angular deviation phasor (56) is tested by a digital signal processor using relatively simple instruction cycles to determine the phase angle of the phasor with respect to the X axis. While it is burdensome to calculate the exact phase angle of this phasor, it is adequate to consider a more approximate, or quantized, value which is considerably easier to calculate. The phase angles of these phasors are quantized (58) into one of either sectors or octants. Quantizing the phasors produces a stream of real numbers which are evaluated to permit predicting that the channel contains noise. Since these real numbers representing the quantized phasor angles have finite resolution. In the preferred embodiment, the phase angles of the phases were quantized into octants of 45.degree. each.

FIG. 3 shows a cartesian coordinate system of I and Q axes divided into eight octants. The octants are numbered 0 through +3, counterclockwise above the Q axis. Octants below the Q axis are numbered -0 to -3, clockwise. In the preferred embodiment, the numbering of the octants corresponds to the value assigned to a phasor falling anywhere within that octant, thereby quantizing phasors into one of eight octants.

After being quantized (58) the phasor angles are high-pass filtered (59) to eliminate DC content in the phasors (56) from a small frequency offsets between the transmitter and receiver frequencies.

Statistical analysis of the angles of successive phasors (60) generates a numerical index which indicates the probability that the channel contains noise and not information. If many of the angles of the phasors lie in the positive or negative third or fourth octants (octants 2, 3, -2 and -3 shown in FIG. 3), there is a substantial probability that the channel contains noise. If the angles of the phasors lie predominantly in the first and second octants (octants 0, 1, -0 and -1) the channel likely contains an FM modulated signal.

Output of the filter (59) is weighted by a mathematical weighting function (60) which permits more reliable evaluation of the probability that the channel contains noise. In one embodiment, the weighting function (60) numerically squares the output of the filter (59) to produce a second value. Squaring the quantized phasors, some of which have negative values such as -3, 2, or -1, yields a string of positive numbers. The string of positive numbers is used to generate a certainty value or number, indicative of the probability the channel contains noise. Alternatively, the weighting function could calculate the absolute value of the product of two distinct samples from the filter (59) as implemented in the assembly language listing appended below. Other weighting functions may be used depending on the characteristics of the expected signal.

The output of the weighting function (60) is averaged or low-pass filtered (62) to produce an averaged result. The averaged result is indicative of the probability of noise present in the channel. Using the weighting functions described above, the value output by the averaging filter (62) will be lower is signal is present in the channel than if the channel contains only noise. The detection threshold or thresholds may be set depending on the sensitivity desires. A value above the threshold represents noise on the channel; a value below the threshold indicates the presence of a desired signal.

The output of the integrator circuit (62) may be passed to a digital comparator algorithm (not shown) which can compare accumulated value in the integrator (62) to the aforementioned threshold. Depending upon the value chosen for the reference value in the comparator, a decision can be made to squelch or unsquelch subsequent signal processing circuits in the receiver thereby saving power or to enable the signal processing circuits and turn on the output.

The following source code performs the functions of FIG. 2. ##SPC1##