Circuit Arrangement for Providing Power for an IC Chip in a Telephone Subset

This invention relates to telephone subsets and in particular to telephone subsets of the high voltage type which incorporate a semiconductor line switch and at least one microprocessor to perform and control various circuit functions such as visual display, memory dialling, clock, calendar, call duration timer, alarm etc. Some of these functions are required when the subsets are in the on-hook mode.

Telephone subset microprocessors require relative high current for operation and normally, when one such subset is connected to a single exchange line and is in the on-hook mode, the microprocessor is energized by energy stored in a storage capacitor. The voltage across the storage capacitor is monitored such that when it is below a predetermined value a control circuit operates the line switch to rapidly charge the storage capacitor to a voltage sufficient to maintain the microprocessor. Thereafter the voltage on the storage capacitor is maintained via a bleed circuit.

When, however, two or more such subsets are connected in parallel to a single exchange line, a problem arises in providing sufficient energizing power to the microprocessor of any subset in the on-hook mode when one other subset is in the off-hook mode. Momentarily operating the line switch, as described above, in the subset/s in the on-hook mode is highly undesirable because of interference which this would cause to the transmission from the off-hook subset.

It is therefore an object of the present invention to provide an arrangement for providing power to microprocessor means incorporated in a telephone subset, which avoids the aforementioned disadvantage.

According to the present invention, in a telephone subset of the high voltage type incorporating line terminal means, at least one processor means and a controllable semiconductor line switch means, a circuit arrangement for providing power, derived from line current connected to the line terminal means, to said processor means when said telephone subset is in an on-hook mode and voltage dropped across said line terminal means is either of a first magnitude, or a second magnitude which is below first magnitude, said circuit arrangement comprising a storage capacitor means coupled across power terminal means of said processor means, a first capacitor charging circuit adapted to operate said line switch means for a short predetermined period when said subset is in the on-hook mode and connect said line current via the operated line switch means to said storage capacitor means to charge said storage capacitor means to a first predetermined voltage and thereafter maintain said first predetermined voltage with a second storage capacitor charging circuit which couples said line current to said storage capacitor means, wherein said circuit arrangement includes a third capacitor charging circuit for maintaining a charge of a second predetermined voltage, of less magnitude than said first predetermined voltage, across said storage capacitor means when the voltage across said line terminal means is of said second magnitude to power said processor means.

In order that the invention can be readily understood an embodiment thereof will now be described with reference to the FIGURE of the accompanying drawing which shows a schematic circuit of part of a high voltage telephone subset.

Referring to the drawing, subset circuit 1 includes a polarity guard arrangement D1 to whose input terminals are connected line L1 and L2 terminals for connection to an exchange line (not shown) and across which a parallel subset (not shown) may be connected. The negative output of polarity guard D1 is connected to the subsets--ve voltage rail VDD, and the positive output is connected to terminal "a" of a controllable semiconductor line switch 2. The line switch's controllable switching path appears across said terminal "a" and "b" thereof. The control element input of the line switch is at terminal "c" which is connected to a high voltage line switch control transistor TR1 via resistor P.4. Terminal "b" of the line switch is coupled to the subset's transmission circuit (T/X) (not shown). The subset's circuit further comprises a microprocessor (uP)3, a storage capacitor C2 and a parallel voltage reference device in the form of zener diode D3 coupled across terminals VSS and VDD of microprocessor 3 via the "in" terminal and "out" terminal of a conventional three terminal voltage regulator VR. The characteristics of voltage regulator VR ensure a constant 3 volts at the "out" terminal irrespective of any voltage above 3 volts at its "in" terminal. The subset circuit further includes a first capacitor charging circuit comprising line terminal L1, resistor R1, line switch 2, diode D4, inductance I1 to plate of capacitor C2; a second capacitor charging circuit comprising line terminal L1, resistor R2, collector/emitter junction of transistor TR3 to plate of capacitor C2; and a third capacitor charging circuit comprising line terminal L1, resistors R1, R3 and R4, collector/emitter junction of transistor TR1, diode D2 to plate of capacitor C2. The base element of transistor TR2 is coupled via resistor R6 to the "DP" terminal of microprocessor 3 and controlled thereby. A diode D5 couples the collector/emitter junction of transistor TR2 to the base of transistor TR4 whose collector/emitter junction is coupled to the base of transistor TR3. Inductance I1 in the first capacitor charging circuit ensures that speech current is not shunted away from the transmission circuit.

In operation, when the line terminal L1 and L2 of the on-hook subset and a parallel on-hook subset (not shown) are initially connected to an exchange line with capacitor C2 uncharged, 50 v exchange battery appears across line terminals L1 and L2 subset, transistor TR1 is turned on via resistor R2. Line switch 2 is thereby turned on via resistor R4 and terminal "c". Line current via L1, resistor R1, switching path "a"-"b" of line switch 2, diode D4, inductance I1 charges capacitor C2 which rapidly charges to 3.5 volts whereupon transistors TR4 and TR3 turn on. Transistor TR1 is now turned off and thus turns off the line switch. The 3.5 volt charge on capacitor C2 is sufficient to energize microprocessor 2 which thereupon produces a signal at terminal DP for 1 second. This signal is extended to the base element of transistor TR2 via resistor R6. Transistor TR2 operates and thereby operates transistor TR1. Line switch 2 operates and connects line current via line terminal L1, switching path "a"-"b" of line switch 2, diode D4, inductance I1 to storage capacitor C2. The voltage across capacitor C2 now rises to 6.8 volts equal to the knee voltage of zener diode D3. After 1 second the microprocessor removes the signal from terminal DP, transistor TR2 and TR1 turn off in turn. The relatively high voltage across capacitor C2 ensures that transistor TR1 is fully turned off. This is necessary to prevent transistor TR1 from presenting a DC loop to the exchange equipment during an incoming ring condition, and tripping the ring. The charge on capacitor C2 is maintained at the zener voltage (6.8 volts) by line current via line terminal L1, resistor R2 and collector/emitter path of transistor TR3. Voltage regulator VR now provides a regulated 3 V at VSS of microprocessor 2 which ensures sufficient power to provide any on-hook functions.

In the event of the parallel subset going off-hook, the microprocessor 2 in subset circuit 1 which is in on-hook mode still requires about 12 uA to provide on-hook functions. As soon as the parallel subset goes off-hook the voltage across the line terminals L1 and L2 drops from 50 volts to about 10 volts. This causes the voltage across capacitor C2 to decay from 6.8 volts towards 3.5 volts. This occurs because the voltage across resistor R2 is not sufficient enough to provide the 12 uA required by microprocessor 2.

When the voltage across capacitor C2 falls to 3.5 volts the difference between the voltage on the "in" terminal and the voltage on the "out" terminal of voltage regulator VR falls to 0.5 volts and therefore the b/e voltage of transistor TR4 is not sufficient to keep that transistor on. Transistors TR4 and TR3 turn off. Line current via resistor R2 is now directed into the base of transistor TR1 which is turned on sufficiently to conduct enough current to maintain capacitor C2 at 3.5 volts. If the voltage across capacitor C2 rises above 3.5 volts transistors TR3 and TR4 turn on more, thereby subtracting base current from transistor TR1. Line current via line terminal L1, resistors R1, R3, R4 collector/emitter of transistor TR1, diode D2 maintains, by virtue of the regulating effect of transistor TR1, a voltage of 3.5 volts across capacitor C2. This current, however, which is typically 12 uA, is insufficient to turn on line switch 1.

While the present invention has been described with regard to many particulars, it is understood that equivalents may be readily substituted without departing from the scope of the invention.

The claims defining the invention are as follows: