High Speed ECL to CMOS Translator Having Reduced Power Consumption

The present invention relates in general to voltage translators, and more particularly, to an Emitter Coupled Logic (ECL) to Complimentary Metal Oxide Semiconductor (CMOS) voltage translator combining high speed operation and reduced power consumption.

It is well known that many of today's complex systems mix and match integrated circuits (ICs) of different logic families to accomplish a series of interrelated functions. In one example, signals produced in one logic family, ECL, are translated to levels compatible with another logic family, CMOS, for further processing. One known voltage translator, disclosed in U.S. Pat. No. 4,644,194, comprises an emitter-follower NPN transistor having its emitter coupled to the base of a second transistor through a first resistor. The collector-emitter conduction path of the second transistor is coupled between an upper power supply conductor operating at V.sub.CC and a lower power supply conductor operating at V.sub.EE through a pair of serially coupled diodes and a second resistor for translating the ECL input signal, which is typically referenced to the upper V.sub.CC rail, to a potential across the second resistor referenced to the lower V.sub.EE rail. The base of a third transistor is responsive to the potential developed across the second resistor for providing the output signal at the collector thereof. In addition, a regulation circuit is coupled to the base of the second transistor to compensate for changes in V.sub.EE such that the output signal is independent of power supply variation.

When a logic high ECL input signal is applied at the base of the emitter-follower transistor, collector current flows through the first resistor and turns on the second transistor to establish a current flowing through its collector-emitter conduction path. The impedance between the emitter of the second transistor and power supply conductor V.sub.EE is made very low (three PN junctions) for providing high speed operation, but the low impedance also permits excessive current to flow through the translating conduction path. The large current tends to saturate the third transistor and generate excessive power dissipation, both of which are undesirable.

Hence, there is a need for an improved ECL to CMOS translator for combining the features of high speed operation and reduced power consumption with minimal additional components.

Accordingly, it is an objective of the present invention to provide an improved ECL to CMOS voltage translator.

A further objective of the present invention is to provide an improved ECL to CMOS voltage translator for limiting the current flowing through the level translating components to reduce the power consumption.

Another objective of the present invention is to provide an improved ECL to CMOS translator requiring a minimal number of additional components to achieve the reduction in power consumption.

In accordance with the above and other objectives there is provided an improved ECL to CMOS translator responsive to an input logic signal for providing an output signal of a predetermined logic level comprising, first circuit coupled between first and second power supply conductors for developing a first potential in response to the input logic signal wherein the first potential is independent of variations in the supply voltage of the first and second power supply conductors; a second circuit for conducting current between the first and second power supply conductor in response to the first potential; a third circuit for developing a feedback signal proportional to the magnitude of the current flowing through the second circuit; and a fourth circuit for applying the feedback signal to the first means stage for controlling the magnitude of the first potential to limit the magnitude of the current flowing through the second circuit to a predetermined value.

The sole FIGURE is a schematic diagram illustrating the preferred embodiment of the present invention.

Referring to the sole figure, voltage translator 10 comprises NPN transistor 12 having a base coupled for receiving an ECL input signal, and a collector coupled to power supply conductor 14, typically operating at ground potential. The emitter of transistor 12 is coupled through resistor 16 to the collector of transistor 20. The base and emitter of transistor 20 are then coupled through resistors 22 and 24, respectively, to power supply conductor 26 which typically operates at a negative supply voltage, V.sub.EE, such as -5.2 volts. The base of transistor 20 is also coupled to the emitter of transistor 28, the latter of which includes a collector coupled to power supply conductor 14 and a base coupled through current supply 30 to power supply conductor 26. Diodes 32 and 34 are serially coupled between the base of transistor 28 and the emitter of transistor 36. The collector of transistor 36 is coupled to power supply conductor 14, while the base of transistor 36 is responsive to an applied bias voltage, V.sub.BIAS, the latter of which is typically established at the mid-range of the ECL input signal; zero volts for a logic high and -0.8 volts for a logic low.

The aforedescribed circuitry operates as a regulator wherein variation in the power supply V.sub.EE is absorbed in the potential across resistor 24. For the purpose of this discussion, the base currents are considered negligible. Voltage V.sub.BIAS (-0.4 volts with respect to V.sub.CC) is applied to the base of transistor 36 enabling a current to flow through diodes 32 and 34 into current supply 30. The potential developed at the base of transistor 28 is three PN junction potentials (base-emitter of transistor 36 and diodes 32 and 34) below voltage V.sub.BIAS ; a sufficient level to turn on transistors 28 and 20 and establish a potential across resistor 24, V.sub.24, equal to:

where:

V.sub.36 is the base-emitter junction potential (V.sub.be) of transistor

V.sub.32 is the potential across diode 32

V.sub.34 is the potential across diode 34

V.sub.28 is the V.sub.be of transistor 28

V.sub.20 is the V.sub.be of transistor 20

The potentials across the base-emitter junctions of transistors 20, 28 and 36 and diodes 32 and 34 at a given temperature are substantially constant since each varies logarithmically with current. Thus, variation in voltage V.sub.EE is reflected in the voltage across resistor 24 thereby changing the current flowing therethrough. This same current flows through resistor 16 producing the identical variation in the voltage at the collector of transistor 20 as observed in power supply conductor 26. Hence, the potential developed at the collector of transistor 20 is constant with respect to power supply voltage V.sub.EE.

The collector of transistor 20 provides the input signal to the translating stage of voltage translator 10 comprising transistor 38, diodes 40 and 42 and resistor 44. The collector and emitter of transistor 38 are coupled to power supply conductors 14 and 26, respectively, the latter path including serially coupled diodes 40 and 42 and resistor 44. The cathodes of diodes 40 and 42 are coupled to the anode of diode 46 and to the base of transistor 48, respectively. The collector of transistor 48 is coupled to the cathode of diode 46 and to power supply conductors 14 through resistor 50, while the emitter of the same is coupled to power supply conductor 26. The output of voltage translator circuit 10 is provided at output 52 that is the collector of transistor 48.

Transistor 12 is an emitter-follower whereby the potential developed at the emitter follows the potential applied to the base. Assuming that a logic high ECL input signal, V.sub.L (0 volts with respect to V.sub.CC) is applied to the base of transistor 12, the potential at the base of transistor 38 as well as the potentials at the cathodes of diodes 40 and 42 follow the input signal although shifted in voltage by the potentials across the base-emitter junction of transistor 38 and diodes 40 and 42, respectively, developing a sufficient potential across resistor 44 to turn on transistor 48. The voltage at output 52, V.sub.52, is then given by:

where:

V.sub.48 is the V.sub.be of transistor 48

V.sub.42 is the potential across diode 42

V.sub.46 is the potential across diode 46

Since voltage V.sub.48, V.sub.42 and V.sub.46 are essentially equal, voltage V.sub.52 is clamped to one diode potential above power supply voltage V.sub.EE. Although the addition of clamping diode 46 limits the voltage developed at the collector of transistor 48 to avoid saturation, the current flowing through the translating stage continues to conduct through a low impedance path to power supply conductor 26. To limit the current flowing in transistor 38 and diodes 40 and 42, transistor 54 is provided including a base coupled to the anode of diode 46, and a collector and an emitter coupled to the base of transistor 38 and the collector of transistor 48, respectively. A predetermined current flows through the collector-emitter conduction path of transistor 38 and establishes a potential at the anode of diode 42 equal to potential across diode 42 plus the voltage across resistor 44 with respect to power supply voltage V.sub.EE. The current flowing through diode 46, as a function of the voltage developed at the anode of diode 42, is mirrored in the collector-emitter conduction path of transistor 54 such that the voltage developed at the base of transistor 38 maintains the predetermined current flowing therethrough. It is the values of resistors 16 and 44 that determine the magnitude of the predetermined current flowing through the translating stage; the greater the values of these resistors, the smaller the current flowing. However, excessive values of resistors 16 and 44 tend to slow the speed of voltage translator 10; typical value for the speed/power trade off is 3000 ohms for both. Hence, the voltage developed at the base of transistor 38 is regulated by the collector current flowing through transistor 54 to maintain a predetermined current flowing through the translating stage proportional to the value of resistors 16 and 44. If the potential at the base of transistor 38 should attempt to increase, the resulting increase in current flowing through transistor 38 would develop a larger potential across resistor 44 which in turn increases the potential at the base of transistor 54 causing the latter to conducting additional collector current thereby reducing the voltage at the base of transistor 38 to reestablish the predetermined current flowing through the translating stage.

For the case of a logic low ECL input signal (-0.8 volts with respect to V.sub.CC) applied to the base of transistor 12, the potentials developed at the emitter of transistor 38 and the cathodes of diodes 40 and 42 again follow the input signal reducing the potential developed across resistor 44 to an insufficient level to turn on transistor 48 and allowing the voltage at output 52 to rise toward V.sub.CC via resistor 50. The current flowing through the translating stage is determined by the value of resistor 44. Hence, the total translator power dissipation for a logic low input signal is determined by resistor 44, while the total translator power dissipation for a logic high input signal is determined by the values of resistors 16, 44 and 50.

Hence what has been provided is a novel voltage translator responsive to an ECL input signal for providing a CMOS output signal combining the features of high speed and reduced current flowing through the translating stage to reduce power consumption wherein all of the above are provided with minimal additional components.