Resistive Element Using Depletion-Mode MOSFET's

This invention relates to a linear resistance element suitable for use in integrated circuits, particularly integrated 10 circuits that require a large linear resistance independent of voltage potential applied across the resistive element.

Long lines of heavily-doped polysilicon have been used to form resistors in integrated circuits. However, the relatively low resistivity of this material limits the values of resistance which can be obtained. Lightly-doped regions of silicon, such as p-well diffusions or implants, have been used to form resistors with higher values. However, these resistances are not particularly accurate or reproducible and are susceptible to fixed charge or states, as for example at interfaces, which can affect their linearity and resistance values. Depletion-mode transistors have been used as resistive loads but their current-voltage relationships are significantly nonlinear. Large, linear resistances are usually regarded as impractical in IC technology.

U.S. Pat. No. 4,001,612 discloses a linear resistance element for LSI circuitry. The circuit of this invention is composed of two similar depletion type, field effect transistors having their source electrodes connected together and to a voltage source. Their drain electrodes are similarly connected together and to the other side of the voltage source. The gates of the two FET's are connected one to the common drain electrode and the other to the common source electrode. The resistance of this FET pair is substantially independent of the circuit current or voltage. A limitation of this linear resistance element is that the channels of the two FET's are connected in parallel 11 which results in a linear resistance element having less resistance than would otherwise be provided by resistive elements connected in series within the same area.

U.S. Pat. No. 4,667,216 discloses an electric resistor consisting of at least two simultaneously produced monolithically combined MIS field-effect transistors for integrated circuits. Each transistor has a source electrode and a drain electrode that define a source-drain path, a gate terminal, and a channel width to channel length ratio. The transistors are connected in series with each other through the source-drain paths. The gate terminals of each transistor are connected to one of the source and drain electrodes. The gates of each transistor forming a pair are connected together and to the source and drain electrodes that connect each transistor. The channel width to channel length ratios of each transistor comprising a transistor pair are different. This configuration provides a two terminal resistor such that the transistors are graded and balanced against each other with respect to the channel width to channel length ratios. In the operation of this resistor, a given fixed potential V.sub.M is applied to one of the resistor terminals. A first voltage (V.sub.1 -V.sub.M) and a second voltage (V.sub.m -V.sub.2) are alternately applicable to the other terminal wherein (V.sub.1 -V.sub.M)=-(V.sub.M -V.sub.2). Equal and oppositely directed current flows through the resistor when the first voltage is applied as compared to when the second voltage is applied. However, because one of the 11 terminals must be at a fixed potential, this device is unsuitable for applications requiring linearity independent of potential.

Thus, there is a need for a linear resistor suitable for application in integrated circuits which functions independently of potential and which provides greater resistance for a given number of transistors having a particular geometry than is available using present linear resistance elements.

The present invention is a linear resistance element suitable for use in integrated circuits that provides a resistance which is substantially independent of the voltages applied to the terminals of the element over a certain operating range. The invention also provides a greater resistance for a given number of transistors having a particular geometry than is available using present linear resistance elements.

The present invention provides a linear resistance element comprising a pair effect transistors. The transistor pair includes first and second depletion-type field effect transistors each having a gate, a source electrode, a drain electrode, a channel mobility, and a threshold voltage. The source and drain electrodes of each transistor define a source-drain current path through a channel. The first and second transistors are connected with their source-drain paths in series with each other. The gates of the first and second transistors are connected in common to the series connection between the source-drain current paths. The channel width-to-length ratio, channel mobility, and threshold voltage of the first transistor are substantially equal to the corresponding properties of the second transistor. Any number of transistor pairs may be serially connected together.

FIG. 1 illustrates a schematic diagram of a resistive element using depletion-mode MOSFET's.

FIG. 2 illustrates a series of serially connected linear resistive elements where each element includes a pair of depletion-mode MOSFET's.

FIG. 3 is a graph which illustrates measured DC current-voltage characteristics of an n-channel version of the circuit in FIG. 1.

The present invention, shown in FIG. 1, is linear resistance element 8 composed of two MOS series connected, depletion-type, field effect transistors 10 and 12 having gates 14 and 16, respectively. The source and drain terminals of each of transistors 12 and 14 provide a source-drain path through the channel region of each transistor. Current carrying terminals 18 and 20 of transistors 10 and 12, respectively, are operably connected in common with gates 14 and 16. Terminals 22 and 24 provide external access to resistance element 8. Depending on the direction of current flow, the source terminal of either transistor 10 or 12 and drain terminal of the other transistor are connected to commonly connected gates 14 and 16. Transistors 10 and 12 may both be either n- or p-channel type field effect transistors. Furthermore, as shown in FIG. 2, a linear resistance element 100 may be constructed of a series of serially connected transistor pairs 102, where each pair 102 consists of transistors having the characteristics of transistors 10 and 12. In the operation of linear resistance element 8, assume that the devices are operated in the linear or triode region so that the drain current I.sub. d of each transistor 12 and 14 is given to first order by:

where the subscripts d, g, and s indicate drain, gate, and source, respectively, V.sub.T is the threshold voltage, and K=.mu. C.sub.ox W/L, where .mu. is the channel mobility, C.sub.ox is the capacitance per unit area of the gate oxide, and W/L is the width-to-length ratio of the channel of the transistor. It is assumed that the parameters V.sub.T, .mu., and the channel width-to-length ratios are substantially equal for transistors 12 and 14. Therefore, the constant K is also substantially equal for each of transistors 12 and 14. Equation (1) governing transistors 12 and 14 in linear resistance element 8 may be solved for the common gate voltage under DC conditions and the result back-substituted to obtain the DC current-voltage relationship for the circuit illustrated in FIG. 1:

where V is the voltage drop across linear resistance element 8 and I is the current flowing through this element. Equation 2 is 14 valid while both transistors are operated in the linear region. Saturation of one of the devices occurs when the magnitude of V reaches the value V.sub.sat given by:

The conductance, G.sub.o =dI/dV at zero voltage is 1/2K V.sub.T. At V=V.sub.T, the predicted deviation from the linear relation I=G.sub.o V is approximately thirteen percent, while at V=1/2V.sub.T, I is only three percent. In practice, the linearity of the circuit is influenced by second-order effects as well, such as the body effect which arises due to substrate-to-source bias in bulk silicon. This effect may be minimized by restricting the range of voltages applied to terminals 22 and 24 of linear resistance element 8, which in any case must remain within the supply voltages in a bulk silicon implementation.

The gate capacitance of the transistors results in an imaginary component of the impedance which becomes significant at a frequency dependent upon the geometries and electrical parameters of the transistors. We linearize the circuit for a small-signal analysis about the operating bias V, allowing R.sub.1 to represent the incremental resistance of the transistor whose source is connected to the gates, C.sub.1 to represent its incremental gate-to-drain capacitance, and allowing R.sub.2 and C.sub.2 to represent, respectively, the resistance and gate-to-source capacitance of the device whose drain is connected to the gates. The impedance, Z, of the circuit becomes:

where s is the complex frequency parameter, R.sub.s =R.sub.1 +R.sub.2, .tau..sub.1 =R.sub.1 C.sub.1, .tau..sub.2 =R.sub.2 C.sub.2, and .tau..sub.p =(C.sub.1 +C.sub.2)R.sub.1 R.sub.2 / (R.sub.1 +R.sub.2). About V=0, R.sub.1 =R.sub.2 =1/2R.sub.s, the capacitances are evenly divided between the sources and drains, and .tau..sub.p =.tau.1=.tau.2=.tau., where:

Using a simple estimate of the gate-to-drain and gate-to-source capacitances in the triode region:

where X=V.sub.ds /(V.sub.gs -V.sub.T), and evaluating the incremental resistances, we obtain approximate values for the time constants at non-zero biases; about V=V.sub.T, .tau..sub.p =.tau., .tau..sub.1 =1.7, and .tau..sub.2 =0.8, while about V=1/2V.sub.T, .tau..sub.p =.tau., .tau..sub.1 =1/2.tau., and .tau..sub.2 =0.9.tau..

We have fabricated this circuit in a thin film silicon-on-sapphire material, using both n- and p-channel depletion-mode transistors. With this material and process, the devices are isolated on the dielectric substrate, eliminating the body effect and its accompanying nonlinearity. This material also permits voltages at terminals 22 and 24 to assume values in any range, even outside the supply voltages, so long as the voltage drop across the resistor is limited to prevent saturation per Equation 3.

The results presented herein are for one particular example of an embodiment of the present invention using an n-channel version of the circuit. The film and gate oxide are both 100 nm thick. Channels were implanted with 10.sup.12 arsenic atoms/cm.sup.2. Channel W/L ratios are 3 .mu.m/15 .mu.m for each device. Threshold voltages, estimated using data obtained from individual transistors, are bout -7.75 V. This value, along with an estimate of the mobility from the same data, gives a predicted resistance of 204 K.OMEGA. at V=0, and a time constant, .tau., of 800 ps, corresponding to a frequency of 200 MHz.

FIG. 3 depicts the results of I-V measurements performed on this embodiment. The resistance of V=0 is 212 k.OMEGA., obtained by linear regression using the four data points nearest the origin, at V=.+-.0.25 V and .+-.0.5 V. This corresponds to an effective "sheet resistance" of about 21 k.OMEGA. per square of channel region. The deviation from the linear relationship predicted by this resistance is measured at six percent when V=7.75 V, the magnitude of the threshold voltage; it is less than the expected deviation due to second-order effects. Nonlinearity becomes more significant as V approaches V.sub.sat, which is around IIV.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Therefore it is to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.