Multichannel Data Compressor

1. Field Of The Invention

The invention is related to data compression communication systems and, in particular, a data compressor which generates a composite data value from the data received from a plurality of data sources.

2. Prior Art

Data compression has been known in the art to reduce the bandwidth of the transmission system or to increase the sampling rate of the data to be sent. As data requirements become higher and higher, data compression remains one way in which more data can be transmitted without having to increase the bandwidth of the transmission system. Eng et al. in U.S. Pat. No. 4,593,318 discloses a technique for time compressing television signals in which the transmission comprises a line, frame, or field, as received plus two other lines, frames or fields as differential signals Eng et al. also teaches multiplexing the output of three different video sources so that the output of the three different video sources can be transmitted in the same time span normally required to transmit the same data, as originally generated from a single video data source.

Cavanaugh, in U.S. Pat. No. 4,099,202, Brown et al. in U.S. Pat. No. 4,237,484, Shimoyama et al. in U.S. Pat. No. 4,542,406 and Tu in U.S. Pat. No. 4,544,950 teach the multiplexing of the digital audio and video data for simultaneous transmission, rather than transmitting them on separate sidebands as done with commercial television transmissions.

Various data compression techniques and multiplexing data from a plurality of data sources are known in the art. The present invention is a multichannel data compression system wherein the data from a plurality of data sources is compressed and multiplexed to generate a compressed data word which significantly increases the sampling rate of the plurality of data sources over the sampling rate if the data from each data source was transmitted in its entirety.

A multichannel data compressor for a transmission system has a plurality of data sources and a transmitter for transmitting compressed data to a remote location. The multichannel data compressor has a plurality of difference amplifiers, one for each data source, which subtract the previous data value generated by its associated data source from the current data value to generate a plurality of difference data values. A like plurality of summing means sum said plurality of difference data in different sequences to generate a plurality of composite data values. A multiplexer multiplexes the plurality of composite data values in a predetermined format to generate a compressed data word for transmission by the transmitter.

The preferred embodiment includes a remotely located receiver system having a receiver and a multichannel data expander. The multichannel data expander has a demultiplexer for demultiplexing the transmitted compressed data word to reconstruct each of the plurality of composite data values. Composite data sum amplifiers sum selected composite data values, to generate correction data values which correspond to the difference data values generated by the multichannel data compressor. A plurality of adders, one associated with each data value, add each correction data value to its associated data value to update each of the data values stored in a current data latch to generate a current data value.

A selector switch is provided in the multichannel data compressor for transferring selected data values received from the data sources when one or more of the composite data values exceeds a predetermined value.

The object of the multichannel data compressor is to compress the data from a plurality of data sources permitting the bandwidth of the transmitter to be reduced.

Another object of the multichannel data compressor is to generate a plurality of data values which are a composite of the data generated by the plurality of data sources.

Another object of the multichannel data compressor is to increase the sampling rate of the transmission system without increasing its bandwidth.

These and other objects and features of the data compressor will become apparent to one skilled in the art from reading the detailed description of the invention in conjunction with the drawings.

cl BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a data communication system embodying a multichannel data compressor and a multichannel data expander;

FIG. 2 is a circuit diagram of the multichannel data compressor;

FIG. 3 is a circuit diagram used to explain the function of the selector switch 50;

FIG. 4 shows the 18 bit format of the compressed data word transmitted by the transmitter;

FIGS. 5-7 show the 18 bit format of the different transmitted data value words transmitted by the transmitter; and

FIG. 8 is a circuit diagram of the multichannel data expander.

A typical communication system in which the multichannel data compressor may be used is illustrated in FIG. 1. In this system, the information generated by three different sources are to be transmitted to a remote location by radio or any other type of communication link. Although the preferred embodiment is illustrated and described with reference to a system having three information sources, it is to be understood that concept of the multichannel data compressor will not be limited to this number.

Referring to FIG. 1, the illustrated system, has a transmitter subsystem 2 and a receiver subsystem 4. The transmitter subsystem has a first analog data source 10, a second analog data source 12 and a digital data source 14. The analog data sources 10 and 12 may be of any type known in the art, such as an audio signal generator, the analog data output of a television camera, or the output of an analog sensor. In a like manner, the digital data source 14 may be of any known type, such as the output of a computer, or a digital sensor. As would be recognized by a person skilled in the art, all the data sources may be analog data sources or may all be digital data sources, or the data sources 10, 12 and 14 may be any combination of analog and digital data sources.

Prior to being transmitted to the multichannel data compressor (MCDC) 20, the analog data generated by the analog data sources 10 and 12 are converted to a digital format by Analog-to-Digital (A/D) converters 16 and 18, respectively. The multichannel data compressor 20 will compress the data into a unique format which is transmitted to the receiver subsystem 4 at a remote location by a transmitter 22. The transmitter 22 may be a radio transmitter as shown, may be a wire transmitter such as a telephone communication link or a fiber optic communication link.

A receiver 24 at the remote location will receive the information transmitted by the transmitter 22 and forward it to a Multichannel Data Expander (MCDE) 26. The Multichannel Data Expander 26 will reconstruct the data to a digital format identical to that received by the multichannel data compressor 20. If required, Digital-to-Analog (D/A) converters 28 and 30 will convert the digital data corresponding to the analog data received from Analog Data Sources 10 and 12 back to their original analog format. The analog data from Digital-to-Analog converters 28 and 30 are available at output terminals 32 and 34, respectively, while the digital data corresponding to the data received by the multichannel data compressor 20 from the Digital Data Source 14 is available at output terminal 36 which is connected directly to the data output of the Multichannel Data Expander 26.

The details of the multichannel data compressor 20 will now be discussed relative to FIG. 2. The digital data "A" corresponding to the output of the first Analog Data Source 10 after being converted to a digital format by Analog-to-Digital converter 16 is received at an input terminal 38. In a like manner, the digital data B corresponding to the output of the second Analog Data Source 12 after being converted to a digital format by Analog-to-Digital converter 18 is received at input terminal 40 while digital data C from Digital Data Source 14 is received directly at input terminal 42.

The absolute value of data A received at input terminal 38 is communicated directly to a data latch 44, a positive input of a difference circuit 52 and a selector switch 50. The latch 44 stores the absolute value of data A for one data cycle. The value of data A stored in the data latch 44, hereinafter identified as data A.sub.t, is transmitted to the negative input of difference circuit 52 in response to a transmit clock signal generated by a transmit clock 70 in synchronization with the receipt of the next subsequent absolute value A.sub.t+1 of data A. A 10 megahertz clock 68 clocks the data in and out of data latches 44, 46, and 48 and in and out of a composite data latch 64 in a conventional manner.

The difference circuit 52 subtracts the value of A.sub.t from the value of A.sub.t+1 to produce difference data value .DELTA.A which is the difference between the current value (A.sub.t+1) and the preceding value (A.sub.t) of data A. The output of difference circuit 52 is connected to a positive input of sum circuits 58 and 60 and a negative input of sum circuit 62.

In a like manner, terminal 40 which receives the absolute value of data B is connected to the input of a data latch 46, the positive input of a difference circuit 54 and to the selector switch 50. The data latch 46 stores the absolute value of data B for one data cycle and transmits the data B, referred to as data B.sub.t to the difference circuit 54 in synchronization with the next iteration, data B.sub.t+1 of data B. The difference circuit 54 subtracts B.sub.t from B.sub.t+1 to generate difference data value .DELTA.B which is the difference between the current value (B.sub.t+1) and the preceding value B.sub.t of data B. The difference data value .DELTA.B is applied to the positive inputs of sum circuits 58 and 62 and to the negative input of sum circuit 60.

Input terminal 42 is connected to the input of data latch 48, the positive input of difference circuit 56 and to selector switch 50. The data latch 48 stores the absolute value of data C as C.sub.t which is transmitted to the negative input of difference circuit 56 in synchronization with the next iteration, data C.sub.t+1 of data C. The difference circuit 56 subtracts C.sub.t from C.sub.t+1 to generate difference data value .DELTA.C which is the difference between the current value (C.sub.t+1) and the preceding value (C.sub.t) of the data C. The difference data .DELTA.C is transmitted to the positive inputs of sum circuit 60 and 62 and the negative input of sum circuit 58.

The sum circuit 58 generates composite data value D which is the sum of difference data values A, .DELTA.B, and .DELTA.C where:

In a like manner, the output of sum circuit 60 is composite data E where:

and the output of sum circuit 62 is composite data F where:

The outputs of the sum circuits 58, 60, and 62 are connected to a composite data latch 64 which independently stores the composite data values D, E, and F. The outputs of the sum circuits 58, 60, and 62 are also connected to the selector switch 50 and are used to determine whether the composite data values D, E, and F or the absolute values A.sub.t+1, B.sub.t+1 and C.sub.t+1 are to be transmitted by the transmitter 22 as shall be explained with reference to FIG. 3.

The composite data latch 64 has three outputs, one for each of the three composite data values D, E, and F, which are directly connected to the selector switch 50. As previously discussed, the absolute values data A.sub.t+1, B.sub.t+1, and C.sub.t+1, received at input terminals 38, 40 and 42 are also transmitted to selector switch 50. The selector switch 50 will select for transmission, either the absolute values of the received data A.sub.t+1, B.sub.t+1, and C.sub.t+1, or the composite data values D, E, and F dependent upon the magnitude of the composite data D, E or F. If the magnitude of any one of the composite data D, E or F exceed a predetermined value, the absolute value of the data A.sub.t+1, B.sub.t+1, or C.sub.t+1 will be transmitted, otherwise the composite data D, E and F will be transmitted.

The output of the selector switch 50 is connected to a multiplexer 72 which assembles the data received from the selector switch 50 into a predetermined format. The multiplexer 72 will then serially transfer this data to the transmitter 22 through output terminal 74.

The logical function of the selector switch 50 is shown in FIG. 3. The composite data values D, E and F are received, respectively, by a set of comparators 76, 78 and 80. Each of these comparators compares the magnitude of the composite data value, for example, the number of bits, with a predetermined value, and generates an output when the composite data value exceeds the predetermined value. The outputs of comparators 76, 78 and 80 are received by a logic circuit 82. The logic circuit has a first output "a" which connected to inputs to OR gates 84 and 86, a second output "b" connected to OR gates 86 and 88 and a third "c" output which is connected to OR gates 84 and 88. The logic circuit 82 also generates a two bit digital code which is transmitted to the multiplexer 72 identifying the data to be transmitted.

Table I shows the truth table for the logic circuit 82 as a function of the outputs of comparators 76, 78 and 80 in response to the composite data values D, E and F received from the sum circuits 58, 60, and 62.

This truth table is based on the assumption that the priority of data C is less than the priority of data B and that the priority of data B is less than the priority of data A. When the outputs d, e and f of all three comparators are logic 1's than the logic circuit 82 will sequentially generate digital codes 01 and 10 such that the absolute values of A.sub.t+1 and B.sub.t+1 and A.sub.t+1 and C.sub.t+1 will be transmitted in the next two transmissions.

Referring back to FIG. 3, the OR gate 84 is connected to one input of AND gate 90 and to the inverting input of NAND gate 92. The absolute value of data A.sub.t+1 is received at the other input of AND gate 90 and the composite data value D is received at the non-inverting input of NAND gate 92. The outputs of AND gate 90 and NAND gate 92 are connected to the inputs of OR gate 102 whose output is connected to multiplexer 72. In a like manner, the output of OR gate 86 is connected to one input of AND gate 94 and to the inverting input of NAND gate 96. The absolute value of B.sub.t+1 is received at the other input of AND gate 94 and the composite data value E is received at the noninverting input of NAND gate 96. The outputs of AND gate 94 and NAND gate 96 are connected to OR gate 104 whose output is connected to multiplexer 72. The output of OR gate 88 is received at one input of AND gate 98 and the inverting input to NAND gate 100. The absolute value of C.sub.t+1 is received at the other input of AND gate 98 and the composite data value F is received at the noninverting input of NAND gate 100. The outputs of AND gate 98 and NAND gate 100 are connected to OR gate 106 whose output is connected to the multiplexer 72.

The operation of the selector switch 50 is as follows:

If the outputs d, e and f of comparators 76, 78 and 80 are all logical 0's, than the outputs a, b, and c of logic circuit 82 are all logical 0's disabling AND gates 90, 94 and 98 and enabling NAND gates 92, 96 and 100. In this state, the selector switch will transmit the composite data values D, E, and F, currently stored in latch 64 to the multiplexer 72. The logic circuit 82 will also generate a digital code 00 which is also transmitted to the multiplexer 72 along with the composite data. The multiplexer 72 will multiplex the composite data values D, E and F and the binary code to form an 18 bit compressed data word which is transferred to the transmitter 22 in response to the signals received from the 18 stage counter 66.

If the outputs d, e, or both d and e of comparators 76 and 78 are logical 1's, than the output "a" of logic circuit 82 will become a logical 1 enabling AND gates 90 and 94 to pass the absolute data values A.sub.t+1 and B.sub.t+1 to the multiplexer 72 through OR gates 102 and 104, respectively, and disabling NAND gates 92 and 96. The logic circuit 82 will also forward the binary code 01 to the multiplexer 72 identifying that the absolute data A.sub.t+1 and B.sub.t+1 are to be transmitted.

If the outputs e and f of comparators 78 and 80 are logical 1's, the output "b" of logic circuit 82 will become a logical 1 enabling AND gates 94 and 98 to pass the absolute data B.sub.t+1 and C.sub.t+1 to the multiplexer 72 an disabling NAND gates 96 and 100. The logic circuit will also generate the code 11 identifying that the absolute data B.sub.t+1 and C.sub.t+1 are to be transmitted.

If the output "f" or outputs d and f of comparators 76 and 80 are logical 1's, the output c of logic circuit 82 will become a logical 1 enabling AND gates 90 and 98 to pass the absolute data A.sub.t+1 and C.sub.t+1 to the multiplexer 72 and disable NAND gates 92 and 100. The logic circuit 82 will then generate the code 10 identifying that the absolute values of data A.sub.t+1 and C.sub.t+1 are to be transmitted.

If the outputs "d", "e", and "f" of comparators 76, 78, and 80 are all logical 1's, the output "a" of logic circuit 82 will first become a logical 1 enabling AND gates 90 and 94 to pass the absolute data A.sub.t+1 and B.sub.t+1 to the multiplexer 72 and the logic circuit 82 will simultaneously transmit the code 01 to the multiplexer signifying that the absolute data A.sub.t+1 and B.sub.t+1 are to be transmitted. After the transmission of A.sub.t+1 and B.sub.t+1, the output "c" of the logic circuit 82 will become a logical 1 enabling AND gates 90 and 98 to pass the absolute data A.sub.t+1 and C.sub.t+1 to the multiplexer 72 and the logic circuit will simultaneously transmit the code 10 to the multiplexer 72 signifying that the absolute data A.sub.t+1 and C.sub.t+1 are to be transmitted.

The operation of the multichannel data compressor 20 will now be discussed with reference to a specific example to illustrate the degree of data compressibility obtainable. In this example, the digital data values A, B, and C received from their respective sources is in the form of an 8 bit byte and the compressed data transmission by transmitter 22 is in the form of an 18 bit word as shown in FIG. 4 in which the least significant bit is bit 1. The most significant bits, bits 18 and 17 are a binary code, such as 00, identifying the message as a compressed data message containing composite data values D, E and F. Bits 16-12 contain composite data values "D", bits 11-7 contain composite data value "E" and bits 6-2 contain composite data value "F". In the event one or more of the compressed data value exceeds 5 bits, the logic circuit 82 will initiate the transmission of the absolute values of data A.sub.t+1, B.sub.t+1 and C.sub.t+1 as previously described. FIG. 5 shows the data format for the transmission of the absolute values of data A.sub.t+1 and B.sub.t+1. Again, the most significant bits 18 and 17 are a binary code, such as 01, identifying that the data contained in the transmitted word contains the absolute values of data A.sub.t+1 and B.sub.t+1. The 8 bit value of absolute data a.sub.t+1 is contained in bits 16-9 of the transmitted word and the 8 bit value of absolute data B.sub.t+1 is contained in bits 8-1.

In a like manner, the transmission formats for the 8 bit values of absolute data A.sub.t+1 and C.sub.t+1 and of absolute data B.sub.t+1 and C.sub.t+1 are shown in FIGS. 6 and 7, respectively. As discussed relative to the transmission formats shown in FIGS. 4, 5, 6, and 7, bits 18 and 17 are a binary code identifying the type of data contained in the transmitted word. As is known in the art, the transmitter 22 may add parity bits to the beginning end of the transmitted word to check the accuracy of the transmission.

Referring to FIG. 2, as the initial 8 bit absolute values of the data A, B, and C are received, they are temporarily stored in data latches 44, 46, and 48, respectively. Since the initial content of data latches 44, 46, and 48 are zero (0), the outputs .DELTA.A, .DELTA.B and .DELTA.C of difference circuits 52, 54, and 56 are respectively equal to the absolute values of data A, data B and data C. As a result, the outputs of the sum circuits 58, 60, and 62 will normally be greater than 5 bits, therefore the selector switch 50 will select the absolute values of data A, B and C for the initial transmissions by the transmitter 22. The transmitter 22 will transmit two sequential messages as previously described, each containing different combinations of the absolute values of the data A, B and C such that all three absolute values of the data A, B and C are transmitted.

In a like manner, the next iteration data A.sub.t+1, B.sub.t+1 and C.sub.t+1 are stored in data latches 44, 46, and 48, respectively. Simultaneously, the data A.sub.t, B.sub.t and C.sub.t previously stored in data latches 44, 46 and 48 are subtracted from the values of data A.sub.t+1, B.sub.t+1 and C.sub.t+1 in difference circuits 44, 46, and 48 to produce difference data values .DELTA.A, .DELTA.B, and .DELTA.C. The difference data values .DELTA.A, .DELTA.B and .DELTA.C are then summed in sum circuit 58, 60 and 62 to generate the composite data values D, E and F which are temporarily stored in composite data latch 64. If each of the composite data values D, E and F is 5 bits or less, the selector switch 50 will pass the composite data values D, E and F from the composite data latch 64 to the multiplexer 72 for the next transmission. The multiplexer 72 will format the composite data in the compressed data format shown in FIG. 4, add the data code bits in bit positions 18 and 17 and serially transmit the formatted compressed data word to the transmitter 22 for transmission.

In the event one or more of the compressed data D, E or F is larger than 5 bits, the selector switch 50 will transfer the appropriate absolute values of A.sub.t+1, B.sub.t+1 or C.sub.t+1 to the multiplexer 72 where it is formatted as required (FIGS. 5, 6 or 7) and forwarded to the transmitter 22 for transmission.

The effectiveness of the multichannel data compressor 20 is obviously a function of how frequently absolute values of the data need to be transmitted. Table II shows the data compression ratio as a function of the frequency (% of time) of transmissions in which absolute values of data are sent.

The data compression ratios listed on Table II are calculated on the basis that it takes 30 bits to transmit the uncompressed data from the three sources used in the embodiment shown in FIG. 1. The 30 bits include an 8 bit data value from each source plus a 2 bit data identification code which identifies the source of the data. The compression ratio when only composite data D, E, and F is being transmitted is 30/18=1.67. For the sampling rate, it is assumed the transmitter is capable of transmitting 1,000K bits per second. The sampling rate (SR) for a conventional system is therefore: ##EQU1## For the multichannel data compressor, the sampling rate SR (MCDC) when only compressed data is being transmitted is: ##EQU2##

As can be seen from Table II, the compression ratio decreases as the number of transmission of absolute values increases per unit of time. When absolute data values must be sent at least 70% of the time, the compression ratio becomes less than unity and the effectiveness of the multichannel data compressor is extinguished. However, when the absolute data values are transmitted less than 30% of the time, the data compression is significant resulting in a 28 to 67% increase in the sampling rate.

The details of the multichannel data expander (MCDE) 26 of the receiver subsystem 4 are shown in FIG. 8. A demultiplexer 108 decodes the binary code attached to each 18 bit word message received from the receiver 24 and will demultiplex the received data accordingly. For example, if the binary code is 00 indicating that the received transmission contains composite data values D, E, and F, the demultiplexer 108 will transfer the composite data values D, E, and F to the sum amplifiers 110, 112 and 114 as shown. Sum amplifier 110 will add composite data values D and E then divide the sum by 2 to produce a correction value .DELTA.a which is equal to difference data value .DELTA.A.

where:

In a like manner, sum amplifier 112 sums composite data values D and F to reproduce the correction value .DELTA.b which is equal to difference data value .DELTA.B.

where:

(D+F)/2=(2.DELTA.B)/2=.DELTA.B=.DELTA.b

Sum amplifier 114 sums composite data values E and F to produce a correction data value .DELTA.c which is equivalent to difference data value .DELTA.C.

where:

The correction values .DELTA.a, .DELTA.b, and .DELTA.c generated by sum amplifier 110, 112 and 114, respectively, are temporarily stored in correction data latches 116, 118 and 120, respectively.

The receiver data latches 128, 130 and 132 respectively store the values of the data A.sub.t, B.sub.t and C.sub.t generated from the content of the preceding transmission received by the receiver 24. The value A.sub.t stored in latch 128 is updated to the new value A.sub.t+1 by adding in sum amplifier 122 the value of A.sub.t currently stored in receiver data latch 128 with the correction data value .DELTA.a stored in correction data latch 116. This new value of data A.sub.t+1 is then stored in receiver data latch 128 as the current value of data A. This process is substantially the reverse of the process used to generate the composite data values D, E, and F in the multichannel data compressor 20.

In a like manner, the data value B.sub.t stored in receiver data latch 130 is updated to its new value B.sub.t+1 by adding in sum amplifier 124, the value of data B.sub.t currently stored in receiver data latch 130 with the correction data value .DELTA.b stored in correction data latch 118. The sum of B.sub.t and .DELTA.b, is the value of data B.sub.t+1 which is stored in receiver data latch 130 as the current value of data B. The data value C.sub.t+1 is generated by adding in sum amplifier 126 to the correction data value .DELTA.c to the value of the data C.sub.t stored in receiver data latch 132. The new value, data C.sub.t+1, is then stored in receiver data latch 132 as the current value of data C.

When the binary code contained in the 18 bit word received from the receiver 24 is not 00, indicating that the received word contains the absolute value of two of the three data sources, the demultiplexer 108 will identify from the binary code which absolute data values were received and transfer them directly to the receiver data latches 128, 130 or 132 as required. For example, if the binary code contained in the most significant bit positions (bits 18 and 17) of the received 18 bit word is 01, indicating that the absolute values of the data A.sub.t+1 and B.sub.t+1 are contained in the received word, the demultiplexer 108 will transfer the absolute value of data A.sub.t+1 to receiver data latch 128 where it is stored as the current value of data A and will transfer the 8 bit absolute value of data B.sub.t+1 to receiver data latch 130 where it is stored as the current value of data B. When the binary code is 10, the demultiplexer 108 will transfer the 8 bit absolute value of data A.sub.t+1 to receiver data latch 128 where it is stored and will transfer the 8 bit absolute value of data C.sub.t+1 to receiver data latch 132. When the binary code is 11, the demultiplexer 108 will transfer the 8 bit absolute value of data B.sub.t+1 to receiver data latch 130 and transfer the 9 bit absolute value of data C.sub.t+1 to receiver data latch 132 where it is stored.

The receiver data latches 128, 130 and 132 always store the most current values of data A, B, and C. These values may be the 8 bit absolute values of the data contained in the 18 bit words, or the absolute values generated from compressed data. The data values may be transferred directly to a utilization device or may be converted to an analog format by Digital-to-Analog converters as shown in FIG. 1.