Single-Supply Digital-to-Analog Converter for Control Function Generation

1. Field of the Invention

This invention relates to the field of digital to analog conversion and, in particular, to converters adapted for use in disk drive controllers and similar applications, such as many servo systems, where a need exists for an output voltage function of the form V.sub.out = V.sub.1 + V.sub.2 (1-2D) or V.sub.out = V.sub.1 - V.sub.2 (1-2D), where both V.sub.1 and V.sub.2 may be supplied as input variables and D is function from 0 to 1, supplied as a digital value to control a DAC.

2. Discussion of the Prior Art

Digital-to analog converters are needed in many applications. Of particular interest herein is their use in control systems, such as electro-mechanical servo mechanisms. In recent years, the use of digital servo techniques has become widespread to control disk drive read/write head positioners (i.e., actuators) and spindle motors. Handling the analog signals for driving such transducers requires the use of analog-to digital converters (ADC's), digital to analog converters (DAC's), operational amplifiers, logic functions and discrete components. The combination of these elements can take up a large section of precious board space in a hard disk drive system.

In a hard disk drive system, the disk heads produce low level analog signals that are amplified and are subsequently passed through detection and demodulation circuits prior to being converted to digital form. The digital data is then supplied to a servo micro controller that computes position and velocity of the read/write head. The micro-controller executes a control algorithm which takes as input the position and velocity information and outputs control data to a DAC which then drives the power amplifier that operates the read/write head actuator, to position the read/write head accordingly. One basic need for disk drive applications, therefore, is a DAC which, at half scale, presents an output sitting at some defined bias point V.sub.bias. This bias voltage establishes a zero-error position of the read/write head. With a half scale digital code applied to the DAC, the head is presumed to be directly over the data track. Feedback acts to increase or decrease the DAC code, to keep the head centered over the data. The magnitude of the DAC output voltage swing obviously depends on the individual system parameters and is essentially another independent variable, V.sub.swing. An ideal disk drive DAC thus provides an output voltage given either by the formula V.sub.out = V.sub.bias + V.sub.swing (114 2D) or by the formula V.sub.out = V.sub.bias - V.sub.swing (1-2D), where D represents the equivalent fractional value of the full scale DAC resolution indicated by the digital code applied to the DAC and ranges between 0 and 1. Hereinafter, therefore, we shall use the simplified expression "V.sub.out = V.sub.bias .+-. V.sub.swing " as a way of saying that the function is V.sub.out = V.sub.bias + V.sub.swing (1-2D) or V.sub.out = V.sub.bias - V.sub.swing (1- 2D). V.sub.swing defines the span of the signal, V.sub.bias is a DC reference level on which the V.sub.swing signal is superimposed and the composite signal can thus span the range between V.sub.bias - V.sub.swing to V.sub.bias + V.sub.swing (i.e., as D varies between 1 and 0).

The disk drive application is a specific case of the more general situation in which a DAC is needed to supply an output which is offset from zero (by some predetermined amount) when a zero code input is provide to the DAC.

Traditional ADC's and DAC's require additional signal conditioning circuits to interface with these signals, since they only handle ground referenced or differential input signals. In order to get an output range of V.sub.bias .+-. V.sub.swing from a conventional DAC such as the model AD7569 DAC from Analog Devices, Inc., of Norwood, Mass., at least three solutions exist. The first solution is shown in FIG. 1. There, the circuit 10 provides an output range of V.sub.bias .+-. 2.5 volts. The circuit is thus limited in that it can provide only a predefined .+-. 2.5 volt swing, rather than a swing which is arbitrarily set (within some predetermined limits) by application of a variable voltage V.sub.swing. Additionally, an external reference of +1.25 volts has to be provided. If the external reference does not match the internal reference, the swing will not be symmetrical about V.sub.bias. The restricted swing can be overcome by the circuit 20 of FIG. 2. This circuit provides an additional op-amp 22 to generate a zero to V.sub.swing output range from the zero to +1.25 volt output of the DAC 24. This circuit, however, also has the problem of matching the two reference voltages, since the output of op-amp 26 will not swing symmetrically about V.sub.bias unless the V.sub.swing /2 signal applied at node 28 is matched to the output of op-amp 22. An alternative is the circuit 30 of FIG. 3 which, instead of requiring a V.sub.swing /2 voltage requires a V.sub.bias - V.sub.swing voltage at the input. However, an additional operational amplifier (not shown) is probably required to generate this difference voltage. Again, the circuit suffers from having to match the internal reference (gain adjusted to produce V.sub.swing DAC output) with the external V.sub.swing voltage.

An approach published in CMOS DAC Application Guide, Analog Devices, Inc., Norwood, Mass., 1984 at 20 (Analog Devices Pub. No. G872-30 10/84), is shown in FIG. 4. There, a voltage switching circuit is shown. The OUT2 terminal of DAC 31 is driven by a lower offset voltage V.sub.2 via buffer 32, and the OUT1 terminal is driven by a full scale output voltage via buffer 33. If the DAC ladder termination resistor is connected to the AGND terminal, the output voltage V.sub.out for a given digital input code D is given by:

If the ladder termination resistor is connected to the DAC's OUT2 terminal, the output voltage is given by:

Consequently, the end points of the span are V.sub.2 and approximately V.sub.1. In other words, the inputs are not conveniently V.sub.bias and V.sub.swing but, rather, are functions which must be derived from those variables (using additional components, not shown). Moreover, the outputs of buffers 32 and 33 should never go negative with respect to OUT2 or parasitic action may damage the DAC.

Another approach is shown in FIG. 5, which is a variant of the circuit of FIG. 4 in which V.sub.1 = V.sub.bias + V.sub.swing and V.sub.2 = V.sub.bias -V.sub.swing. A resistive divider formed of resistors 42 and 44 supplies via buffer amplifier 46 a voltage V.sub.bias + V.sub.swing to the reference voltage input of a DAC 50 and to the anode of a Zener diode 52. The cathode of the Zener diode 52 is connected to ground through a resistor 54 and to the analog ground terminal (AGND) of DAC 50. When V.sub.bias + V.sub.swing is adequate to keep the diode 52 conducting, the output V.sub.drive = V.sub.bias .+-. V.sub.swing. Of course, this circuit is limited in that V.sub.swing is established by the Zener diode 52 (where V.sub.zener = 2 V.sub.swing) and cannot be supplied as a variable input on a signal lead. Additionally, V.sub.swing must be a positive voltage. FIG. 5 essentially shows an approach published in M. Byrne, AD7224 Provides Programmable Voltages over Varying Ranges, Analog Devices, Inc., Norwood, Mass. 198 , Analog Devices Application Note No. E910-15-5/85.

For disk drive (and many other servo) applications, the ability to provide both V.sub.bias and V.sub.swing as variable values is important. Further, the DAC should be capable of operating from a standard single sided supply voltage in order to avoid creating an unnecessary need for a second supply voltage. A DAC requiring both positive and negative supplies would, for most applications, not be commercially acceptable.

Accordingly, it is an object of the invention to provide an improved DAC for hard disk drive servos and other similar servo systems.

A further object of the invention is to provide a DAC which operates from a single sided supply and is capable of supplying as an output a signal of the form V.sub.bias .+-. V.sub.swing, or equivalently V.sub.bias + V.sub.swing (1-2D) or V.sub.bias V.sub.swing (1-2D), where V.sub.bias and V.sub.swing represent voltages which are applied to the DAC as input variable and D is a fractional code from 0 to 1.

Yet another object of the invention is to provide an improved DAC which is capable of supplying as an output a signal of the for V.sub.bias .+-. V.sub.swing, where the output varies symmetrically

Still another object of the invention is to provide an improved DAC which is capable of supplying as an output a signal of the for V.sub.bias .+-. V.sub.swing, where the need to carefully match voltages and/or components is minimized.

The foregoing objects are achieved in several simple but effective circuits which constitute alternative embodiments of the invention. In each embodiment, a DAC is combined with an operational amplifier and (typically) three or four resistors. The voltage V.sub.swing, or a current corresponding thereto, is applied to the reference input terminal of a DAC. The DAC output provides a suitably scaled and signed signal which is then added to the offset signal V.sub.bias.

The operation and advantages of the present invention will become more fully understood from the detailed description below, which should be read in conjunction with the accompanying drawing.

In the drawing:

FIG. 1 a schematic circuit diagram for a prior art circuit which provides the function V.sub.out = V.sub.bias -2.5 v (1-2D), where D is the decimal or fractional equivalent value of the digital code supplied to the DAC;

FIG. 2 is a schematic circuit diagram for a first prior art circuit which provides the function V.sub.out = V.sub.bias - V.sub.swing (1-2D);

FIG. 3 is a schematic circuit diagram for a second prior art circuit which provides the function V.sub.out = V.sub.bias - V.sub.swing (1-2D)

FIG. 4 is a schematic circuit diagram for a third prior art circuit which under some conditions provides the same function;

FIG. 5 is a schematic circuit diagram of still a fourth prior art circuit which under appropriate conditions provides the same function;

FIG. 6 is a schematic circuit diagram of a first embodiment according to the present invention;

FIG. 7 is a schematic circuit diagram of a second embodiment of the present invention;

FIG. 8 is a schematic circuit diagram of a third embodiment of the present invention;

FIG. 9 is a schematic circuit diagram of a fourth embodiment of the invention, employing a CMOS DAC;

FIG. 10 is a schematic circuit diagram for a fifth embodiment of the invention;

FIG. 11 is a schematic circuit diagram of the converter of FIG. 9 with the addition of a circuit for the current source;

FIG. 12 is a schematic circuit diagram of a sixth embodiment of the invention, employing a CMOS DAC; and

FIG. 13 is a schematic circuit diagram of an alternative embodiment of the circuit of FIG. 12, which may be used if it is required to produce a complementary transfer function to that of FIG. 12.

The schematic circuit diagram for a first embodiment of the present invention is shown in FIG. 6, from which it will be seen that the invention is made from a DAC 60, an operational amplifier 62, and four resistors: 64, 66, 68 and 72. Resistors 64 and 68 have a resistance value R and resistors 66 and 72 have a resistance value 2R. DAC 60 is a multiplying DAC controlled by, for example, an 8-bit digital word supplied via a data input bus 74. The output of DAC 60 is the voltage applied to the reference input V.sub.ref (i e., V.sub.swing) multiplied by a factor D, which ranges from 0 to (2.sup.n -1)/2.sup.n, where n is the resolution of the DAC, in bits. The factor D equals the decimal equivalent of the code on bus 44, divided by 2.sup.n. The following equations show how the output voltage varies from V.sub.bias - V.sub.swing to V.sub.bias + V.sub.swing, as D varies from 0 to 1/2 to 1: ##EQU2## Intermediate the D values D = 0 and D = 1/2, on the one hand, and D = 1/2 and D = 1, on the other, the output smoothly varies from V.sub.bias - V.sub.swing to V.sub.bias, on the one hand, and from V.sub.bias to V.sub.bias + V.sub.swing, on the other.

A variation on the circuit theme of FIG. 6 is shown in FIG. 7. There, however, in addition to a DAC 60, the circuit requires two op-amps 82 and 84, as well as six resistors 85-90, all of which must be trimmed to the same value.

As shown in FIG. 8, a simplification of the circuit of FIG. 6 can be achieved, if the DAC 98 output impedance 100 is not zero (as assumed in FIG. 6) but instead is a value R which then may be used as one of the "R's38 in the DAC output divider. Thus in both FIG. 6 and FIG. 8 we may say that the DAC output is provided to the non inverting input of the op-amp through a resistor of resistance R. Further, the resistor 64 of resistance R can be replaced by two parallel resistors of value 2R each. Thus, the V.sub.swing /2 signal can be obtained from a simple voltage divider formed by resistors 102 and 104, each of resistance 2R, placed in series across the V.sub.ref and analog ground (AGND) terminals to which the V.sub.swing signal is applied. For incremental purposes, resistors 102 and 104 are actually in parallel, providing an incremental resistance R between a V.sub.swing /2 source and the inverting input of op-amp 106, just as the same incremental resistance is employed in FIG. 6.

Since the user can separately specify V.sub.bias and V.sub.swing as input variables, he or she has great flexibility in handling different input and output signal levels. The voltage V.sub.bias can be drawn from the reference voltage available in the disk drive system, which is normally 5 to 6 V. Like the circuits of FIGS. 1-5, only positive supply voltages are required for the circuits of FIGS. 6 13, making these circuits useful in the numerous situations where only positive supply voltages are available, typically from a single supply.

Another circuit which provides the same output function is shown in FIG. 9. The DAC 110 is a standard CMOS R-2R ladder DAC, such as the Model AD7240 DAC from Analog Devices, Inc. The reference current I.sub.ref is determined by the required voltage swing V.sub.swing and is given as I.sub.ref = V.sub.swing /R.sub.m, where R.sub.m is the value of the matched resistors 112 and 114. R.sub.m is independent of the DAC ladder resistance.

If in FIG. 9 I.sub.ref is made to be a current out of the terminal to ground (instead of into the DAC from V.sub.DD), the complementary output function is obtained--i.e., V.sub.out = V.sub.bias - V.sub.swing (1-2D).

FIG. 10 shows a variation of the circuit of FIG. 9, wherein a bipolar DAC 120 is used and the current I.sub.ref = V.sub.swing /R.sub.m is provided by a transconductance amplifier formed by op-amp 122 and transistor 123, the latter being the reference transistor in the DAC. The output of op-amp 122 also biases the bases of all of the common emitter transistors in each leg of the DAC (i.e., connected to each 2R resistor in the R-2R ladder). Op-amp 122 has a differential input. The non inverting input receives the voltage V.sub.bias ; the inverting input receives the voltage V.sub.bias - V.sub.swing (which can be generated by another op-amp, not shown). The voltage across resistor 124 (whose resistance is R.sub.m) is substantially equal to V.sub.swing, since there is essentially no voltage drop across the amplifier inputs. Further, since there is virtually no input current to the amplifier due to its high impedance, the current V.sub.swing /R.sub.m through resistor 124 must be supplied via feedback path 126, as the collector current in transistor 123. Substantially the same current is pulled through emitter resistor 130 and, thus, through the DAC resistor ladder, where it divides up in accordance with the positions of DAC switches 132 1 through 132-n. An offset voltage V.sub.bias is applied at terminal 134 and is superimposed at the non inverting input of amplifier 136 with the voltage induced by the difference in DAC output currents I.sub.1 and I.sub.2, to provide the output signal V.sub.out of the form discussed above.

Implementation of the circuit of FIG. 9--i.e., a converter using a CMOS DAC, is dependent on proper formulation of a current source for I.sub.REF, since V.sub.OUT has the desired form only if I.sub.REF = V.sub.swing /R.sub.m. FIG. 11 shows a method for generating a current source proportional to V.sub.swing. The circuit is similar to that of FIG. 10. The voltage V.sub.swing is applied to the non-inverting input of an op-amp 140. The inverting input of the op-amp is connected to ground through a resistor 142 of resistance R.sub.m. The output of the op-amp drives the bases of a pair of PNP transistors 144 and 146, both of which have their emitters connected to the voltage source V.sub.DD through a resistance R. Consequently, both transistors operate with the same collector current. The collector of transistor 144 is connected to the inverting input of op-amp 140, providing a current I.sub.FB into node 148 equal and opposite to that produced in resistor 142 by the input signal--i.e., I.sub.FB = V.sub.swing /R.sub.m. Thus, I.sub. ref, the collector current of transistor 146 and the current at the DAC V.sub.ref terminal is also V.sub.swing /R.sub.m, as desired.

Another approach is shown in FIG. 12, where the source applied to the DAC's V terminal is a function of both V.sub.bias and V.sub.swing, allowing both V.sub.bias and V.sub.swing to be ground referenced. Op-amp 154, with equal feedback resistors 154 and 155, serves as a current mirror.

One reason for using a PNP-based DAC is that their high output impedance makes them impervious to voltage changes on the OUT1 and OUT2 output lines. With the addition of an extra op-amp (relative to the embodiments of FIGS. 9 and 11, that is), it is possible to avoid voltage changes on the OUT1 and OUT2 lines for a CMOS DAC over the full digital code range, as well. A suitable circuit appears in FIG. 13. The reference terminal of DAC 160 may be driven with the current source of FIG. 11 or with the voltage reference source of FIG. 12, for example. If the resistance R.sub.m of feedback resistor 162 is actually the DAC ladder resistance, the desired output function is obtained. The complementary output function may be obtained, as with FIG. 9, by changing the direction of I.sub.ref.

Consequently, several examples have been shown of circuits producing the transfer function V.sub.out = V.sub.bias .+-. V.sub.swing (1-2D), where D represents the equivalent fractional value of the full scale DAC resolution indicated by the digital code applied to the DAC. Though the circuits are all different, they all have as a common thread the fact that (a) a function of the V.sub.swing signal (or a corresponding current) is applied to the DAC's reference input and (b) both V.sub.bias and V.sub.swing are positive voltages referenced to ground.

Having thus described several illustrative embodiments of the invention, it will readily be apparent that other embodiments as well as various alterations, modifications and improvements to the disclosed embodiments will occur to those skilled in the art. Accordingly, the foregoing embodiments have been presented by way of example only, and are not in any way intended to be limiting of the invention. The invention is limited only by the following claims and equivalents thereto.