Switching Regulator Having a Constant Current Through Its Inductance

The present disclosure relates to the subject matter of U.S. patent application Ser. No. 07/399,119, filed Aug. 24, 1989.

The present invention is drawn to a switch or boost regulator apparatus and a method of operating the switching regulator apparatus, in which the switching regulator has a setting member or controllable electronic switch means which is controlled by a pulse width modulator, the pulse width modulator receiving a sawtooth-shaped signal having an approximately constant maximum amplitude and a signal dependent upon the current through the switching regulator inductance.

A switching regulator in which there is combined control of the setting member or controllable electronic switch means in dependence on a sawtooth-shaped signal and a switch current proportional signal is disclosed in German Patent No. DE-2,920,166.C2. Such a switching regulator has high stability, particularly against the tendency to oscillate even in cases in which its keying ratio (switch conductive period to OFF period) is more than one-half of a period of the switching frequency in duration.

It is known to change the keying ratio (on-to-off duration ratio) as a function of a switching regulator in that the amplitude of a sawtooth-shaped signal is changed in dependence on the magnitude of the input voltage as shown in the publication "Schaltnetzteile--Motorensteuerungen" [Switching Network Components--Motor Controls], published by Dr. Alfred Huthig Verlag, Heidelberg, 1982, at pages 101-102. However, this publication does not provide a suggestion as to how to operate a switching regulator to optimally suppress a noise voltage in the input voltage.

For example, a problem with the prior art switch controllers can occur due to the presence of alternating components in the otherwise steady input voltage of the switch controller, particularly CS noise (conducted susceptibility), which can adversely affect the operation of the switching regulator.

It is an object of the present invention to provide an improved switching or boost regulator apparatus and method of operating the apparatus, so that the influence of noise signals in the direct input voltage on the output voltage of the switching regulator is substantially suppressed.

This is accomplished according to the invention by supplying a second sawtooth-shaped signal to the pulse width modulator whose maximum amplitude depends on the negative value of the direct input voltage of the switching regulator and, in order to keep constant the arithmetic mean of the current flowing toward the output end of the switch controller, a signal is supplied to the pulse width modulator which is inversely proportional to the value of the direct input voltage supplied to the switching regulator.

A switching regulator according to the invention includes a direct voltage source for producing an input voltage; an output; a controllable electronic switch connected between the voltage source and the output for switching the input voltage to the output; an inductance connected between the input voltage and the controllable electronic switch; a pulse width modulator connected for controlling the electronic switch; a first sawtooth signal generator connected to the pulse width modulator for feeding the pulse width modulator a sawtooth signal of approximately constant amplitude; an inductance connected between the input voltage and the controllable electronic switch, and further including a second sawtooth signal generator connected to the pulse width modulator for feeding the pulse width modulator a sawtooth signal having an amplitude which is proportional to the negative value of the input voltage, and a further signal means connected to the pulse width modulator for producing a signal having an amplitude which is an inversely proportional function of the magnitude of the input voltage of the input voltage source for maintaining the arithmetic mean of the current through the inductance constant.

The present invention provides the following advantages. Alternating components in the direct input voltage of the switch regulator, particularly CS noise (conducted susceptibility), are attenuated considerably. Therefore, the expenditures for filtering means to filter these alternating components in the direct input voltage, which is supplied to the load circuit of the switch regulator, can be kept very low. Stability problems are reduced or do not occur. In operating the switch regulator according to the present invention, the arithmetic mean of the current through the inductance of the switch regulator is caused to be independent of the direct input voltage, and therefore the current through the inductance is likewise independent of alternating components which may be caused by alternating components present in the direct input voltage.

The invention will now be described in greater detail with reference to the drawing figures.

FIG. 1 is a basic circuit diagram of a switching regulator according to the invention.

FIG. 2 is a circuit diagram to derive some of the control signals.

A switching regulator or boost (upward) regulator 1 is shown in FIG. 1 which includes a direct input voltage source Q.sub.E which has a terminal voltage U.sub.E. A switching regulator inductance or choke Dr is in series connection with a rectifier GL between a positive terminal 2 of the direct input voltage source Q.sub.E and a positive terminal 8 at an output means or end 40 of the switching regulator 1 having an output voltage U.sub.A.

A smoothing capacitor CG is disposed at the output end 40 of the switching regulator 1 between an upper terminal 6 and a lower terminal 7. A switching regulator setting member or controllable electronic switch means S1 is shown which is in the form of a bipolar transistor which is disposed between a terminal 10--located between the choke Dr and the rectifier GL--and a terminal 11 connected with a negative terminal 3 of the direct input voltage source Q.sub.E.

The setting member or controllable electronic switch means S1 has a base 12 connected to the output of a pulse width modulator PBM. The setting member or controllable electronic switch means S1 has a conductive period which is controlled by way of signals supplied by the pulse width modulator PBM. The following applies for this duty cycle D.

The duty cycle D indicates for which time t of a period T the setting member S1 is turned on(D=t/T). The pulse width modulator PBM is configured as a comparator. The pulse width modulator PBM has an inverting input 13 which is connected in series with a current measuring resistor RS for measuring the current I.sub.L(t) through the choke Dr, a first sawtooth generator (SZ1, a second sawtooth generator SZ2, and a direct voltage source QD. The direct voltage source QD has a direct voltage which is selected to be greater than an auxiliary direct voltage source U.sub.H. The pulse width modulator PBM has a non-inverting input 14 which is connected to the output of an adder ADD which additively links the following signals together:

a signal U.sub.N, having a value U.sub.N =-K.sub.A .multidot.U.sub.E, where K.sub.A is a proportionality constant;

the auxiliary direct voltage U.sub.H, having a value U.sub.H =K.sub.A .multidot.U.sub.A ; and

a signal U.sub.KV, which is the output signal of a multiplier MU.

The sawtooth generator SZ1 produces an output signal which has a value U.sub.SK(t) as a function of time as follows:

The value U.sub.SK(t) has a maximum amplitude U.sub.SK, where U.sub.SK is selected to have a value U.sub.SK =K.sub.A .multidot.U.sub.A. The value U.sub.SK becomes approximately constant due to the regulation according to the invention of the output voltage U.sub.A.

The sawtooth generator SZ2 produces an output signal which has a value U.sub.SV(t) as a function of time as follows:

The value U.sub.SV(t) has a maximum amplitude U.sub.SV, where U.sub.SV is selected to have a value ##EQU1##

In the above equation, the symbol R.sub.M represents the resistance of the current measuring resistance RS divided by the current converter ratio W2/W7 and the symbol L represents the inductance of the choke Dr. The resistance R.sub.M, when multiplied with the value of the current I.sub.L(t) through the choke Dr, results in a current proportional voltage which is proportional to the value of the current at the choke Dr, the current proportional voltage being supplied at the inverting input 13 of the pulse width modulator PBM. That is, a current converter CC disposed between terminal 10 and the collector of electronic switch S1 is used to obtain the choke current proportional signal during conduction of electronic switch S1 supplied through the current measuring resistor RS. For example, the current converter CC can be of a type having a primary winding W1 disposed between the terminal 10 of the choke Dr and the collector of switch S1, the current converter having a secondary winding W2 which is connected, by way of a rectifier D1, with the current measuring resistance RS. Such circuitry includes state of art knowledge, e.g. disclosed in European Patent No. 0027847.

Therefore, as shown in the above equation, the maximum amplitude U.sub.SV is dependent on the respective negative value of the varying input voltage U.sub.E. The equation for the value of the conductive ratio D determined at the pulse width modulator PBM is given as follows: ##EQU2##

In the equation, I.sub.a is the minimum current through the choke Dr, and U.sub.KO is the value of the voltage between the non-inverting input 14 of the comparator PBM and the negative terminal 5 of the switch controller 1. The value of U.sub.SZ is obtained by the equation U.sub.SZ =U.sub.SK +U.sub.SV.

The following applies for the maximum choke current I.sub.e : ##EQU3##

The choke current I.sub.L, flowing to the output end 40, has an arithmetic mean I.sub.ar which is determined as follows: ##EQU4##

In order to keep this arithmetic mean I.sub.ar constant, i.e., in particular, independent of the varying input voltage U.sub.E, the signal fed to the non-inverting input 14 of the pulse width modulator PBM must be composed of certain signal components which will be derived as indicated below. With the above equations, the arithmetic mean I.sub.ar can be expressed as follows: ##EQU5## If U.sub.SZ =K.sub.A .multidot.U.sub.A +K.sub.E .multidot.U.sub.E, it follows that: ##EQU6## the following applies: ##EQU7##

If U.sub.KO =U.sub.K1 +K.sub.1 U.sub.E, the following applies: ##EQU8## For K.sub.1 =-K.sub.A, the equation becomes: ##EQU9## If U.sub.K1 =U.sub.H +U.sub.KV, the following applies: ##EQU10## If U.sub.H =K.sub.A .multidot.U.sub.A, the following applies: ##EQU11## wherein K.sub.D represents a proportionality constant and U.sub.F (described in detail in the following) represents an amplified error signal of the output voltage U.sub.A, it follows that: ##EQU12##

Therefore, it is possible, by selecting the constants and the signals according to the above relationships, to cause the arithmetic mean I.sub.ar flowing to the output end 40 to be independent of the input voltage U.sub.E and to be, furthermore, independent of noise in input voltage U.sub.E. The sole remaining free parameter K.sub.A is selected in such a manner that the switching controller 1 is stable.

The condition for stability is the following: ##EQU13## If K.sub.E is selected to be ##EQU14## and, since U.sub.SZ =K.sub.A .multidot.U.sub.A +K.sub.E .multidot.U.sub.E, the following must be true: ##EQU15## Thus, K.sub.A becomes: ##EQU16##

The signals supplied to the non-inverting input 14 of the pulse width modulator PBM are produced by circuit elements shown in the figure which together produce the signals necessary to obtain the above-described advantageous results, as explained in the following. An adder ADD, whose output is connected with the non-inverting input 14 of the pulse width modulator PBM, receives the following signals at its input:

that is, a signal proportional to the negative value of input voltage U.sub.E ;

an auxiliary direct voltage which is approximately constant; and the signal ##EQU17## which is inversely proportional to the input voltage U.sub.E and is proportional to the amplified error signal U.sub.F. The signal U.sub.KV supplied to the adder ADD is produced by a multiplier MU which receives the signals U.sub.F and K.sub.D /U.sub.E (which are produced as discussed in the following). The intermediate signal U.sub.K1 is constituted as follows:

The intermediate signal U.sub.K1 is present explicity only if the signal addition is performed in two stages. The signal K.sub.D /U.sub.E can be derived relatively easily from the input voltage U.sub.E by means of a divider DV connected to a terminal 15 which is at the terminal voltage U.sub.E, wherein the divider DV has a division signal which is weighted by the factor K.sub.D. In this manner, the factor K.sub.D is divided by the voltage U.sub.E, and the resulting signal, representing the value K.sub.D /U.sub.E, is supplied to the multiplier MU. The error signal U.sub.F is obtained by means of an error amplifier FV. The error amplifier FV has a noninverting terminal 17 which receives the output of a direct reference voltage source Ur, and an inverting terminal 16 which is connected to a terminal 18 located between a pair of resistors R1 and R2. The resistors R1 and R2 constitute a voltage divider such that, at the terminal 18, a signal is obtained which is proportional to the output voltage U.sub.A. A commonly used two terminal network as feedback network having an impedance Z is provided in a feedback branch of the error amplifier FV. As can be easily derived in FIG. 1: ##EQU18## The auxiliary voltage U.sub.H can be derived directly from the output voltage U.sub.A, for example by way of a voltage divider shown in FIG. 2. The amplitudes of the respective sawtooth signals U.sub.SK(t) and U.sub.SV(t) from the sawtooth generators SZ1 and SZ2 are dependent upon U.sub.SK and U.sub.SV, and the amplitudes of these signals can be derived in a straightforward manner using circuit elements which implement the relationships based on the equations discussed in the above from the input voltage U.sub.E and the output voltage U.sub.A, respectively.

The pulse width modulator which is configured as a comparator is followed by a flip-flop, being reset at the beginning of every switching cycle. Such pulse width modulators are available as integrated circuits, e.g. the SG1524B.

FIG. 2 shows the circuitry to derive the other control signals. Auxiliary voltage U.sub.H is derived from the output voltage U.sub.A via a voltage divider consisting of the resistances R1, R2. The common connection of resistors R1, R2 is connected to an operational amplifier OP1 via its non-inverting input. Operational amplifier OP1 has a feedback resistance R3 connected to a grounding resistance R4. The output signal U.sub.H of operational amplifier OP1 is proportional to output voltage U.sub.A. The way of deriving the signal U.sub.N is quite similar, using an operational amplifier OP2. The difference here is that signal U.sub.N is derived from the input voltage U.sub.E via resistor R5 connected to the inverting input of operational amplifier OP2. A feedback resistor R6 is also connected to the inverting input of operational amplifier OP2.

FIG. 2 also shows the means for combining the first and second sawtooth generators. Output voltage U.sub.A is fed to a capacitor CL via a load resistor R7. A transistor TS in parallel to capacitor CL determines discharging periods of capacitor CL. Transistor TS is controlled via its base electrode by a clock signal generator CSG, which resets capacitor CL with every clock pulse. The signal period of clock signal generator CSG is T thus producing an output signal:

This signal proportional to output voltage U.sub.A is combined with the signal whose amplitude is proportional to the negative value of the input voltage U.sub.E. For this purpose input voltage U.sub.E is fed via resistor R8 to the inverting input of operational amplifier OP3. This operational amplifier OP3 has a feedback resistor R9. The output signal of this operational amplifier OP3, negative proportional to the input voltage U.sub.E is fed via resistor R10 to the capacitor CL. The charging amplitude of capacitor CL is therefore determined by the output voltage U.sub.A and the output signal of operational amplifier OP3.

It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.