Sensing Structure for Single Ended Input

This invention relates generally to a sensing circuit for a memory or microprocessor, and more particularly, to single-ended sense amplifiers.

Single-ended sense amplifiers are widely used in memory and microprocessor circuits for reading (sensing) the logic state of memory cells. In a conventional memory circuit, the memory cells are configured as an array of rows and columns, wherein the presence or absence of a transistor in a memory cell represents the stored bit at the respective memory cell location. The sense amplifier, coupled to the column of the memory cell to be read, detects whether the memory is in a conducting or non-conducting state. If the selected memory cell in the column is in a conducting state, the sense amplifier detects a logic "0", and conversely, the sense amplifier detects a logic "1" when the memory cell is in a non-conducting state.

High-performance microprocessors, utilizing on-chip ROMs for storage of operational information, require high-speed sense amplifiers for fast sensing of data. In many cases, these high-performance microprocessor designs use on-chip ROMs with numerous output lines. While fast sensing is particularly desirable in these microprocessor environments, efficient utilization of chip area and reduction of the power consumption attributable to the amplifier are also design goals. Some amplifiers designed for use in microprocessor circuits employ double-ended, differential amplifiers for fast sensing of data. These double-ended sense amplifiers typically require more devices than single-ended amplifiers, and consequently the chip area required is larger. Moreover, the double-ended amplifiers generally require more DC current for their operation. Consequently, double-ended sense amplifiers are often infeasible for use in high-performance microprocessor circuits.

The implementation of single-ended sense amplifiers typically requires less chip area, therefore these amplifiers are generally more suitable for use in microprocessor circuits with on-chip memory. In the prior art there are single-ended sense amplifiers which require precharge/discharge circuitry for their operation. The precharge/discharge scheme may consume a significant amount of power, and conceivably degrades the performance of the microprocessor circuit. Furthermore, these sense amplifier designs have required depletion devices, which require additional processing steps for their fabrication.

An object of the present invention is to provide an improved sense amplifier.

Another object of the invention is to provide an improved self-biasing high-speed sense amplifier.

Yet another object of the invention to provide an improved single-ended sense amplifier which does not require depletion devices for its operation.

These and other objects of the invention are achieved in a memory circuit with a plurality of memory cells and a decoder for coupling an output of a selected memory cell to a sense node, a sense amplifier for sensing the logic state of said output, comprising a precharger for precharging the sense node to a power supply terminal; a buffer for detecting the logic state at the sense node, and providing an output signal which corresponds to the logic state at the sense node; a charger, having an impedance for coupling the sense node to a second power supply terminal in response to the precharge signal being in a second logic state; a feedback circuit coupled to the charger, and to the buffer for adjusting the impedance on the charger, in response to the output signal.

Shown in FIG. 1 is a single-ended sense amplifier 10, according to a preferred embodiment of the present invention, comprised generally of a precharge portion 11, and a sensing portion 13. Precharge portion 11 comprises p-channel transistors 12, 16, and 22, n-channel transistors 14, 18 and 20. Sensing portion 13 comprises inverters 24 and 26. Inverter 24 comprises a p-channel transistor 19 and an n-channel transistor 21. Inverter 26 comprises a p-channel transistor 23 and an n-channel transistor 25. Sense amplifier 10 is coupled to a matrix of memory cells, represented by n-channel transistors 30, 60, 61, and 62. N-channel transistors 28 and 63 function as decoders to determine which memory cell in the matrix is accessed.

Transistor 12 has a source connected to a positive power supply terminal V.sub.DD, a drain connected to node a 42, and a gate for receiving an input sense amplifier enable signal (SAE). Transistor 14 has a source connected to the drain of transistor 12, a gate connected to node 44, and a drain. Transistor 16 has a source connected to the drain of transistor 12, a gate connected to node 44, and a drain connected to a node 46 which is an input of inverter 24. Transistor 18 has a drain connected to the drain of transistor 14, a gate for receiving input signal *SAE, and a source connected to ground. Transistor 19 has a source connected to V.sub.DD, a gate connected to node 46, and a drain. Transistor 21 has a source connected to ground, a gate connected to node 46, and a drain connected to the drain of transistor 19, for providing the output of inverter 24. Transistor 20 has a drain connected to node 44, a gate connected to V.sub.DD, and a source connected to ground. Transistor 22 has a drain connected to a node 44, a source and a gate. Transistor 23 has a source connected to V.sub.DD, a gate connected to node 48, and a drain. Transistor 25 has a source connected to ground, a gate connected to node 48, and a drain connected to the drain of transistor 23, for providing the output of inverter 26.

Amplifier 10 is designed to sense data from read only memory (ROM) arrays. In a typical ROM cell, where the absence or presence of a transistor represents a stored bit, a sense amplifier is coupled to the column of the memory cell to detect whether the memory cell is in a conducting or non-conducting state. When the memory cell is in a non-conducting state, the sense amplifier will detect a logic "1", and when the memory cell is in a conducting state, the sense amplifier will detect a logic "0". Accordingly, the absence of a transistor denotes a logic "1", and the presence of a transistor a logic "0". In the present invention, charge node 46 is an input of amplifier 10. During a pre-charge phase, signal *SAE is a logic high, therefore charge transistor 12 is non-conductive and precharge transistor 18 is conductive. Node 46, an input to inverter 24, is thus discharged to ground by transistor 18. Inverter 24 serves as a buffer driver for the load on node 48. Inverter 24 provides an output of essentially V.sub.DD, therefore the voltage level at node 48 is a logic high during the precharge phase. Inverter 26 serves as a buffer driver for the load on node 50, and controls the logic state of transistor 22. Similarly, inverter 26 provides an output of essentially ground, therefore the voltage level at node 50 is a logic low. Consequently, p-channel feedback transistor 22 becomes conductive. Feedback transistor 22 couples the logic high output of inverter 24, at node 48, to node 44. A voltage (V.sub.44) at node 44 is at a voltage between V.sub.DD and ground. By selecting the relative gains of transistor 20, 22, and the p-channel transistor 19 of inverter 24, voltage V.sub.44 can be set to a selected value between V.sub.DD and ground. During precharge, the optimum voltage (V.sub.46) at node 46 is achieved if the conductivity of n-channel transistor 14 is relatively high and the conductivity of p-channel transistor 16 is relatively low. The optimum condition is achieved when the threshold voltage of the n-channel transistor 20 (V.sub.tn) equals the threshold voltage of the p-channel transistor 22 (V.sub.tp). Accordingly, the voltage at node 44 is set to be .vertline.V.sub.DD -V.sub.tn .vertline., by the division of transistors 19 and 20. Under the above conditions, transistor 14 is highly conductive, whereas, transistor 16 is slightly conductive.

After the completion of the row and column selection of the addressed memory cell, signal *SAE switches to a logic low. The relatively high voltage at V.sub.44 causes transistor 14 to rapidly supply a substantial amount of current to charge node 46. Charge transistor 14 charges node 46 to a voltage just below the switchpoint of inverter 24. Depending upon whether there is an additional pull down on node 46, the voltage at node 46 will either remain below or increase beyond the switchpoint of inverter 24. In the case where the ROM cell is programmed to be non-conductive, there is no current drain through pass transistor 28, due to the absence of a transistor in the selected memory cell, therefore the voltage at node 46 will approach the switchpoint of inverter 24. Once inverter 24 switches, it will provide an output at node 48 which is a low voltage level. Due to the time delay between inverter 24 and inverter 26, the voltage level at node 50 remains a logic low for a short time while node 48 is switching to a logic low, therefore, transistor 22 also remains on for this short delay time. Consequently, transistor 22 passes the low voltage from node 48 to node 44, thereby causing transistor 14 to become less conductive, and charge transistor 16 more conductive. Accordingly, transistor 16 supplies current to node 46, causing the voltage at node 46 to approach V.sub.DD. Meanwhile, inverter 26 switches the low level voltage at node 48, providing an output at node 50 which is a high-voltage level. Due to the high voltage at node 50, transistor 22 becomes less conductive. As transistor 16 supplies more current, the voltage at node 46 will continue to rise, which in turn will cause inverter 24 to switch, thereby producing a low-level voltage at node 48 and a high-level voltage at node 50. This process will continue until the voltage at node 46 is essentially V.sub.DD while the voltage at node 44 is essentially ground. Once the voltage at node 46 is essentially V.sub.DD, inverter 24 will have switched, causing a low-level voltage output at node 48. Similarly, inverter 26 will have switched the low-level voltage, thereby causing node 50, the output of amplifier 10 to be a high-level voltage (essentially V.sub.DD), indicating the detection of a logic "1" state.

In the case where the selected ROM cell, such as transistor 30 in FIG. 1, is programmed to be conductive, node 46 will be discharged to ground, due to the current drain through pass transistors 28, and the transisto at cell 30. Once the voltage level at node 46 becomes sufficiently low, inverter 24 will switch, causing a high-level voltage output at node 48. Similarly, inverter 26 will switch the high-level voltage, thereby causing node 50, the output of amplifier 10 to be a low-level voltage (essentially ground), indicating the detection of a logic "0" state.

By selecting the size ratios of transistors 14, 16, 20, and 22, while taking into account the ROM load and output load on node 50, the sizes and respective switchpoints of inverters 24 and 26 are determined. Moreover, the voltage at node 44 may be adjusted, which facilitates the control of the gate to source voltage (V.sub.gs) of transistor 14. Transistor 14 is important to the operation of amplifier 10 because initially, transistor 14 is the only device supplying current to node 46. If transistor 14 does not provide enough current, the voltage at node 46 will increase slowly, thereby causing slower sensing of the memory cell. Consequently, the gate control on transistor 14 is essential for the optimization of sensing speed.

While the invention has been described in a preferred embodiment, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.