Apparatus and Method for Prohibiting Access in a Multi-Cache Data Processing System to Data Signal Groups Being Processed by a Data Processing Subsystem

1. Related Applications

Apparatus and Method for Data Copy Consistency in a Multi-Cache Data Processing Unit invented by Stephen J. Shaffer and Richard A. Warren, Ser. No. 06/698,364, filed on Feb. 5, 1985 and assigned to the assignee named herein.

Apparatus and Method for Improving System Bus Performance in a Data Processing System having a Plurality of Data Processing Units by Stephen J. Shaffer, Richard A. Warren, Thomas W. Eggers and William D. Strecker, Ser. No. 06/698,399, filed on Feb. 5, 1985 and assigned to the assignee named herein.

2. Field of the Invention

This invention relates generally to data processing systems and, more particularly, to data processing systems having a plurality of data processing units. In the data processing systems with a plurality of data processing units, the multiple copies of data signal groups stored in the cache memory units associated with each data processing unit provide increased opportunity for accessing a data signal group that is being manipulated simultaneously by at least one other data processing unit. In order to prevent inconsistent results from being obtained by the simultaneous manipulation, selected data signal groups are prevented from simultaneous manipulation by the data processing system.

3. Discussion of the Related Art

In data processing subsystems, a plurality of the system units such as data processing units and/or one or more peripheral subsystems, can attempt to access simultaneously a data signal group stored in the main memory unit. The simultaneous or overlapping access of the selected data signal groups by a plurality of data processing subsystems can result in inconsistent, ambiguous and erroneous data signal groups obtained that can impact the operation of the data processing system unless appropriate mechanisms are embedded in the data processing system.

One such mechanism is the use of a register position in the main memory that, once set, prevents further access of the main memory. This register position is set once access to the main memory is acquired, and further of the data signal group access is prohibited until the current access is complete and the register position signal is removed. This mechanism is sometimes described as an interlock mechanism.

However, a mechanism, that prevents access to the main memory unit for the duration of an operation by a data processing unit involving the selected data signal group, can impact the performance of the data processing system. In a data processing system having a plurality of data processing units, the continuing attempts of the data processing units to gain access to the main memory unit can cause non-productive bus traffic, comprising the performance of the data processing system.

A need has therefore been felt to prevent simultaneous use of selected data signal groups by a plurality of data processing units and to reduce system bus activity resulting from continuing attempts to access the prohibited data signal group.

It is therefore an object of the present invention to provide a method and apparatus for an improved data processing system.

It is another object of the present invention to provide a method and apparatus to prevent the manipulation of selected data signal groups simultaneously by two subsystems of a data processing system.

It is yet another object of the present invention to provide a method and apparatus for an improved data processing system having a plurality of data processing units.

It is a more particular object of the present invention to provide an apparatus and method resulting in both a hardware and a software mechanism for preventing simultaneous access to reserved data signal groups.

It is another particular object of the present invention to provide an apparatus and method for reducing the system bus activity normally resulting from attempts to access selected data signal groups that are already in the process of being manipulated, and are therefore unavailable to the requesting data processing unit.

It is a more particular object of the present invention to provide apparatus either in a cache memory unit or in a main memory unit to prevent simultaneous manipulation of selected data signal groups.

It is another more particular object of the present invention to reduce unnecessary bus traffic by providing apparatus in the cache memory units for prohibiting simultaneous manipulation of selected data signal groups.

It is yet another more particular object of the present invention to provide apparatus in the main memory unit for minimizing system bus traffic while prohibiting simultaneous manipulation of selected data signal groups.

The aforementioned and other objects are accomplished, according to the present invention, by providing a data processing system having a plurality of data processing units in which all the copies of a data signal group are identical, and wherein selected individual data signal groups are protected from manipulation by other portions of the data processing system by means of a control signal having a predetermined relationship with the data signal groups, and wherein files of data signal groups can be protected by a control signal having a pre-selected relationship with the data signal group files. The protection of the data signal group can be accomplished by a storage cell capable of storing a control signal associated with the data signal group. The storage cell can be located in the main memory unit and/or in the cache memory unit. Each time the signal in the storage cell is present, the data signal group is protected from further manipulation. This signal is used to prevent any subsystem of the data processing system, except requesting subsystem setting the signal, from accessing or performing any operations in this selected data signal group while the subsystem is currently actively manipulating this data signal group. Another control signal can be associated with a file of data signal groups, and this file is unavailable to the subsystems as long as the subsystem program using the data signal groups of the file maintains the active signal. Thus, two methods of protecting the data signal groups against possible conflicting manipulation are provided, each capable of reducing system bus traffic. When the data signal group file are to be protected, the subsystem requesting the file retrieves a selected data signal group prior to the actual use of the file. The data group retrieved has a position for a control signal identifying when the file is in current use. If the file is in use, this information will be understood by the program and the program will periodically interrogate the selected data group until the data signal location indication of current usage has been changed to a file available designation by the program, i.e., upon completion of its use of the files. If the file is free, the program requiring the file data signal groups will, when the control signal group is retrieved, set the control signal in the location in the file indicating that the file is currently unavailable for manipulation by other data processing units. In this manner, the system bus does not need to be utilized for establishing a file usage during manipulation of the selected data signal group. The second method of protecting a data signal group against simultaneous manipulation is to set a register position when the data signal group is unavailable.

These and other features of the instant invention will be understood by reading of the following description along with the drawings.

FIG. 1 is a representation of the possible conflict arising when two processes attempt to use the same data group simultaneously.

FIG. 2 is a block diagram of a data processing system capable of utilizing the present invention.

FIG. 3a is a schematic block diagram of a cache memory unit capable of implementing the present invention.

FIG. 3b is a diagram demonstrating the address signal sub-groups for an address signal group.

FIG. 4 is a block diagram of a main memory unit capable of utilizing the present invention.

FIG. 5 is a schematic diagram of data signal groups being manipulated by data processing unit.

FIG. 6 is a block diagram of a procedure using a file protect signal for a plurality of data signal groups.

Referring to FIG. 1, a pair of processes are shown that require the same data group for manipulation. At time To, process A retrieves 110a DATA group from address X. The process A manipulates 110b the DATA group and the result of the manipulation is a DATA' group. During the manipulation by process A, process B retrieves 120a the data group from the memory address x, and the process B manipulates 120b the DATA group. The result of this manipulation is a DATA" group. During the manipulation of the DATA group by process B, process A stores 110c the result of the manipulation, DATA' group, in the memory address X. At the end of the manipulation by process B, the resulting DATA" group is stored 120c in the memory address X, replacing the DATA' group stored at that location by process A.

Referring to FIG. 2, a block diagram of a data processing system having a plurality of data processing units is shown. A plurality of data processing units, data processing unit #1, 11, through data processing unit #n, 13, perform the manipulation of data signal groups under control of at least one system program. Cache memory unit #1, 16, is coupled to data processing unit #1, 11, and cache memory unit #n, 17, is coupled to data processing unit #n, 13. Similarly, all of the other data processing units, not shown, are coupled to cache memory units. All of the cache memory units are coupled to a system bus 15 and the system bus 15 is in turn coupled to main memory unit 19.

Referring to FIG. 3a, the system bus is shown as including three sub-buses, a data signal bus 151, an address signal bus 152 and a control signal bus 153. The cache memory unit 16 is coupled to the system bus 15 and to the data processing unit 11 as follows. Control signal input register 168 receives signals from control signal bus 153, and applies signals to cache memory control unit 161. Cache memory control unit 161 applies signals to control signal output register 175 and to state signal input register 171. State signal input register 171 applies signals to state signal memory unit 162. State signal memory unit 162 applies signals to cache memory control unit 161. Control signal output register 175 applies signals to control signal bus 153. Address signal input selector 179 receives signals from address signal bus 152 and from data processing unit 11 and applies signals to address signal input register 167. Address signal input register 167 applies signals to state signal memory unit 162, to y-address memory unit 163, to data signal memory unit 164, to address signal output selector 173, to comparator 165 and to address signal output register 177. Address signal output selector 173 and comparator 165 also receive signals from y-address signal memory unit 163. Address signal output register 177 also receives signals from address signal output selector 173 and applies signals to address signal bus 152. Data signal input selector 178 receives signals from data signal bus 151, and data processing unit 11. Data signal unit register 166 receives signals from data signal input selector 178 and applies signals to data signal memory unit 164. Data signal output selector 174 receives signals from data signal memory unit 164 and from data processing unit 11 and applies signals to data signal output register 176. Data signal output register 176 applies signals to data processing unit 11 and to data signal bus 151. The cache memory control unit 161 is coupled to data processing unit 11, to control signal out register 175, to control signal input register 168, to comparator 165, to address signal output selector 173, to address signal output register 177, to state signal input register 171, to address signal input selector 179, to address signal input register 167, to data signal input selector 178, to data signal input register 166, to data signal output selector 174, and to data signal output register 176.

Referring to FIG. 3b, the structure of the address signal groups is defined. For purposes of description of the present invention, the address signal group is divided into three subgroups; an x-address signal group 201 having q logic signal positions, a y-address signal group 202 having r logic signal positions, and a z-address signal group 203 having s logic signal positions. The x-address signal group 201 defines a physical location of signal groups in the cache memory signal storage components. The y-address signal group 202 is the portion of the address signal group stored in address signal group memory unit 163 at the x position when the data signal group corresponding to the address (x+y) is stored in the data signal group memory unit 164. The z-address group 203 is an address signal group portion that is redundant when multiple basic data signal groups are transferred on the system bus simultaneously and identified by a single address signal group.

Referring to FIG. 4, the main memory unit 60 has a main memory control unit 61 coupled to control signal bus 153 forming part of the system bus 15. Address signal register 62 is coupled to address signal bus 152, while data in signal register 63 is coupled to write data signal bus 151a of the system bus 15 and data out signal register 64 is coupled to read data signal bus 151b. Signals from the address signal register 62 establish a location in main memory storage cell array 65. Data in signal register 63 applies data signal groups to a location in the main memory storage cell array 65 determined by the address signal group in the address signal register 62 and applies data signal signal groups to signal combining unit 66. Data signal groups from a main memory storage cell array 65, determined by the address signal group in address signal register 62, are applied to signal combining unit 66. The data signal groups in signal combining unit 66 are applied to data out signal register 64. Data out signal register 64, signal combining unit 66, data in signal register 63, address signal register 62 and main memory storage cell array 65 are controlled by main memory control unit 61. Control signal memory unit 68 receives address signals from address signal register 62 and is coupled to main memory control unit 61. The section 69 of main memory storage cell array 65 illustrates additional storage cells associated with the cells storing the data signal groups.

Referring next to FIG. 5, an example of the relevant contents of various data signal storage units are shown for a data signal file that is currently being manipulated under control of a first data processing unit and to which a second data processing unit is attempting to gain access. Associated with cache memory unit #1 is a multiplicity of data signal storage cells 50. The data signal storage cells are arranged in a multiplicity of groups of data storage cells 59 and associated with each group of data storage cells is a control signal storage cell from the plurality of data signal storage cells 58. Similarly, in cache memory unit #n, a multiplicity of data signal storage cells 51 is divided into a multiplicity of groups of data signal storage cells 59' and associated with each data signal storage cell group is a control signal storage cell from the group of control signal storage cell 58'. In the main memory unit, a multiplicity of data signal storage cells 52 is divided into groups of data signal storage cells 59" and associated with each data signal storage cell group is a control signal storage cell from the group of control signal storage cells 58". In the example shown in FIG. 5, the group of data signal storage cell groups 53 contains a data signal file. The data signal file has a file header (which may contain more than the one data file signal group shown) for a file of data signal groups and the header contains at least one data signal storage position 55 having a predefined interpretation. The signal in the position 55 can be referred to as a file protect signal. In the example shown, the data processing unit associated with cache memory unit #1 is currently manipulating the data signal file. In every occurrence of the data signal file header 54 in the data processing system (i.e. in cache memory unit #n and in the main memory unit), the data signal storage cell has a predefined data signal stored therein indicating current usage by a component of the data processing system. In the example of FIG. 5, data signal file header 54 has been replaced in cache memory unit #1, and is no longer present. However, the data signal group in current execution 56 is present and because that particular signal group is being currently manipulated by a data processing unit associated with cache memory unit #1, the associated control signal storage cell 57 as well as all control storage cells 57 associated with the data signal group in current execution 56 have the pre-selected control signal stored therein.

Referring next to FIG. 6, the process for using the file protect signal (i.e. the predefined signal in memory cell 55) is described. In step 610, the data processing unit has a requirement for the data signal group with the file protect signal position. The data processing unit applies the address signal group associated with the data signal group to the system bus and retrieves that data signal group from the cache memory unit in step 611. In step 612, the data group is examined to determine if the file protect signal is present. If the file protect signal is not present, then the data processor unit sets the file protect signal and manipulates the data signal group as determined by the program in current execution in the data processing unit in step 613. The setting of the file protect signal is reflected in all copies of the data signal group. If, in step 612, the file protect signal is set, then step 614 is executed in which the data signal group is retrieved from the cache memory unit storage cells after a predetermined delay. If the file protect signal is still set in step 615, the data processing unit then executes step 614 and continues in this loop until retrieval of the data signal group from the cache memory unit indicates that the file protect signal is no longer present. The process than returns to step 611 and proceeds as previously described. At the end of usage of the file, the data processing system using the file removes the file protect signal permitting usage by other data processing systems.

The use of a single storage cell in the main memory control unit that prohibits access to the main memory unit while a selected data signal group is being manipulated can cause a large amount of unproductive traffic on the system bus as other data processing units attempt to gain access to the main memory unit. Another storage cell can be added to the main memory control unit and each cell can be used to prohibit access to half of the main memory. As will be clear, a decrease in unproductive bus traffic will result because half the main memory data signal groups can be available for access by a requesting cache memory unit. To minimize the unproductive bus traffic, the instant invention provides either a control signal memory unit 68 or additional main memory storage cells 69 in array 65. With respect to the additional main memory storage cells 69, the granularity of the unavailability of the data signal groups of the main memory can be diminished even to the point of prohibiting access to a single data signal group when sufficient additional storage cells are added. Viewed in another way, the available portion of the main memory unit can be increased as additional storage cells are provided. When a selected data group is being manipulated, the associated storage cell in control signal memory unit 68 or main memory storage cell array 65 can have a logic signal stored therein prohibiting access to the associated data signal group of the main memory unit by other data processing units or peripheral subsystems. The control signal memory unit 68 can be described as main memory cache memory, comprised of an array of single storage cells, each storage cell associated with a region of the main memory. The control signal memory unit 68 can store a signal associated with each region and is immediately accessed when an address is applied to the main memory unit. Thus, the resulting indication of inaccessibility of the data signal group can be returned immediately to the requesting data processing unit and the data retrieval can be aborted.

System bus traffic can also be reduced by placing the storage cells associated with each cache memory unit storage location, for example, in the state signal memory unit 162 in FIG. 3a. In this embodiment, the signal groups of the address signal bus and the control signal bus are continuously monitored. When a selected data signal group is being manipulated by a data processing unit, a logic signal can be set in the state signal memory unit 162 when the data signal group is stored in the cache memory unit and the corresponding address signal group and control signals are applied to the system bus 15. This control signal can prohibit manipulation of the related data signal group by the associated data processing unit. When the manipulation of the selected data signal group is complete, the manipulating data processing unit can communicate the fact, via the system bus, by applying the address signal group and appropriate control signals to the system bus, and the logic signal will be removed from the state signal memory unit 162 of the cache memory unit of a different processing unit. It will be clear that utilizing the storage cells in the cache memory unit reduces the bus traffic because the inaccessibility of the selected data signal group can be determined in the immediate environment of the cache memory unit and associated data processing unit without accessing the system bus.

Referring once again to FIG. 5, the mechanisms for maintaining consistency in selected data signal files while minimizing the utilization of the system bus 15, are shown. The mechanisms require two constraints. The first constraint is that all data signal groups and associated control signal groups associated with an address signal group are identical in the data processing system. Second, the header of each file of data signal groups either includes a sub-routine or activates a mechanism in the data processing unit that permits the data processing unit to address the associated cache memory unit without having the address signal group applied to the address bus. Thus, a data processing unit, seeking access to a data signal file, will identify the predefined control signal in file header and will engage in a process loop involving the repeatedly addressing the data signal file header and the control signal in the cache memory unit by the coupled data processing unit without interaction with the system. However, when data processing unit #1 completes the manipulation of the data signal file, a routine will set the predefined signal in the data signal file header to the opposite value permitting usage by other systems. Because of the first constraint, i.e. the identity of data signal group identified by a given address, the predefined data signal in location 55 in the data signal file header will be set to an opposite binary value in all copies of the data. The next access of the data processing unit associated with the cache memory unit #n, the data processing unit will equality the absence of the predefined signal and can access the data signal file header in the previously described manner. The control signals of data signal cells 58, 58' etc. provide a hardware mechanism preventing access to that data signal group by any data processing unit in the data processing system. The pre-selected signal is transmitted on the system bus when each data processing unit accesses the data signal group at that address.

It will be clear that a procedure similar to the file protect signals can be implemented for the logic signals stored in the storage cells in the main memory unit indicating inaccessibility of the associated data signal group. In this procedure, the fact that a logic signal is stored in the main memory unit can be communicated throughout the data processing system. By appropriate procedures that prohibit attempts by the data processing unit to access the data until the logic signal of the main memory has been removed, the data processing system can continue internal activity. The activity on the system bus including an address signal group and appropriate control signals communicates to the data processing system the availability of the data signal group.

The above description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the foregoing discussion, many variations will be apparent to one skilled in the art that would yet be encompassed by the spirit and scope of the invention.