Dynamic Memory Cell Using Silicon-on-Insulator Transistor With Trench Capacitor

This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to construction of one-transistor dynamic read/write memory cells.

Dynamic read/write memory cells made by the double-level polysilicon N-channel self-aligned process commonly used in the industry for 16K and 64K DRAMs are shown in U.S. Pat. No. 4,388,121, issued to G. R. Mohan Rao, assigned to Texas Instruments. A contactless metal gate cell is shown in U.S. Pat. No. 4,345,364, issued to David J. McElroy, also assigned to Texas Instruments; this contactless cell can be made in higher density, such as needed for 256K and 1-Mbit DRAM devices.

Although these double-level polysilicon cells and contactless cells have proved to be quite successful and many hundreds of millions of memory devices have been made using such prior methods, there is nevertheless a continuing necessity to reduce the cell size, and increase the ratio of the storage capacitance per unit of cell area in dynamic memory cells, especially for the next generation 4-Mbit DRAMs. One improvement to this end has been to form the storage capacitor in a groove or trench so that the surface area of the capacitor is increased without increasing the cell area on the face of the chip; examples of this concept are shown in U.S. Pat. No. 4,225,945, issued to Kuo, or pending application Ser. No. 627,371, filed Jul. 3, 1984 by Baglee, Doering, & Armstrong, both assigned to Texas Instruments.

It is the principal object of this invention to provide an improved dynamic read/write memory cell, particularly of smaller cell size. An additional object is to provide a dense array of dynamic memory cells, made by a more efficient method. A further object is to provide an improved way of making dynamic memory cells.

In accordance with an illustrative embodiment of the invention a dynamic read/write memory cell of the one transistor type employs a trench capacitor, and a silicon-on-insulator transistor stacked on top of the capacitor. A very small cell size is provided. The bit line is formed by siliciding the polysilicon which forms the transistor. Field plate isolation isolates one cell from another in an array.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a greatly enlarged plan view of a small portion of a semiconductor chip showing the physical layout of a part of a dynamic memory cell made according to the invention;

FIG. 2 is an electrical schematic diagram of the cell of FIG. 1;

FIGS. 3a-3c are elevation views in section of the cells of FIG. 1, taken along the lines a--a, b--b, and c--c, respectively, in FIG. 1; and

FIGS. 4a-4d are elevation views in section of the cell array of FIGS. 1 and 3a-3c, at successive stages in the manufacturing process, taken generally along the line a--a in FIG. 1.

Referring to FIGS. 1, 2 and 3a-3c, a one-transistor dynamic read/write memory cell constructed according to the invention is illustrated. This cell includes an access transistor 10 and a storage capacitor 11, wherein the transistor is a silicon-on-insulator type that is positioned on top of the capacitor, and the capacitor is created in a trench 12 etched into a silicon substrate 13. The transistor 10 has a channel region 14 formed in a layer of polycrystalline (or single-crystalline) silicon which also is silicided to form a bit line 15, a drain region 16, a source region 17 and a contact area 18. A word line 20 extends across the top of the transistor and forms a gate 21 separated from the channel region 14 by thin gate oxide 22. The capacitor 11 includes an N type region 23, diffused into the sidewalls and bottom of the trench 12 to form the lower plate, and uses a thermal oxide coating 24 as a capacitor dielectric. The trench is filled with polycrystalline silicon 25 which also extends across the face of the silicon substrate to create a grounded field plate 26 for isolating one cell from adjacent cells along the face. The contact 18 is formed in a hole 27 etched through the polysilicon field plate 26 and oxide 24, as well as through an interlevel oxide insulator 28 that separates the polysilicon 26 from the overlying transistor. The field plate 26 has a thermal silicon dioxide layer 29 separating it from the silicon substrate 13.

A method of making the memory cell of FIGS. 1 and 3a-3c will be described with reference to FIGS. 4a-4d. A slice of silicon (containing the substrate 13 as a very small part of it) first has the field oxide 29 grown to a thickness of about 3000 A, then is coated with a masking material 30 as seen in FIG. 4a and an opening 31 is formed where the trench 12 is to be created. An anisotropic etch is performed using a method such as RIE to create the trench 12 to a depth of perhaps 3 microns; the width is about one micron, so the Figures are distorted in the vertical direction, i.e., the trench is much deeper than it is wide. The slice is next exposed to a phosphorus diffusion source at high temperature to create the N type region 23, still using the masking material 30 and oxide 29 to limit the diffusion to only within the trench.

Turning to FIG. 4b, the masking material 30 is removed and the thin oxide coating 24 is grown to about 200 A by exposing an oxidizing atmosphere at high temperature. Then, the polycrystalline silicon 25 and field plate 26 is deposited by a CVD deposition which tends to fill the trench. The next step is growing of the oxide 28, again by thermal oxidation of the polysilicon.

Referring now to FIG. 4c, the hole 27 is now etched for the contact 18. To this end, a photoresist mask is formed to cover the face of the slice except where the hole 27 is to be created. Then a dry etch is performed to remove the exposed oxide 28, then to remove the polysilicon 26. At this point the etch is stopped, and a thermal oxidation performed to oxidize the edges of the polysilicon around the hole, to avoid shorting the contact 18 to the field plate 26. Then an anistropic etch is used to remove the oxide 29 in the bottom of the hole but not in the sidewall. Note that the alignment of the hole 27 is not very critical because if it extends into the polysilicon 25 of the trench it is of no consequence; indeed this is preferred because contact to the region 23 is assured in this manner. Next, an N+ diffusion is performed to create the region 34 which makes connection to the N region 23; this diffusion is masked by the oxide 29.

With reference to FIG. 4d, a coating 35 of polycrystalline silicon is deposited over the oxide 28 and into the hole 27, and patterned by photolithographic steps to leave the bit line 15, transistor and contact 18. Since the transistor 10 is to be created in this layer 35, it may be preferable to subject the layer to laser anealing or the like to crystallize the material, resulting in better transistor characteristics. Layer 35 is doped with material of opposite impurity-type than that of capacitor region 23. The layer 35 is thermally oxidized at this point to create the gate oxide coating 22 over the entire surface. A masking material such as silicon nitride is now applied over the oxide 22, then patterned by photolithography to leave only a strip mask crossing the channel area 14 where the gate 21 is to be later formed. The exposed oxide 22 is etched away, then the polysilicon 35 is doped with phosphorous or other material of similar impurity-type as that of capacitor region 23 and is silicided by depositing a material such as titanium and heating to react the titanium with the silicon to create titanium silicide where not masked by nitride. This is needed to make the bit lines and contact areas of low resistance. The channel of the transistor is protected by the silicon nitride.

As seen in FIGS. 1 and 3a-3c, the fabrication is completed by depositing the oxide 38, removing the oxide and nitride from the gate area of the transistor, then depositing metal over the top surface and patterning to leave the word line, 20 and gate 21.

The area occupied by one cell in an array of cells made according to the invention is about 2.5.times.4 microns, so the cell size fits within the requirements for feaqsible manufacture of 1-Mbit DRAMs using 1 microns as a minimum width.

While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications to the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.