Semiconductor Device With Parallel Multiplier Using at Least Three Wiring Layers

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a parallel multiplier using at least three wiring layers.

2. Description of the Related Art

High-performance and high-speed data processing devices are in increasing demand. To realize high-speed multiplication, LSIs adapted for parallel-multiplication or LSIs which incorporate parallel-multiplication macrocells (functional blocks subjected to design verification test) have been in wide use recently. By significant advances in hardware technology, an LSI may incorporate a large-scale parallel multiplier. For instance, a parallel multiplier for two 32-bit numbers has already been implemented.

Such a parallel multiplier forms the product of a multiplicand and a multiplier in accordance with the following process: (1) Partial products are generated, and (2) The resulting partial products are summed to provide the product. Such an arithmetic operation is described in an article entitled "Outlook on circuit systems of parallel multipliers which are now in progress of LSI version", NIKKEI ELECTRONICS in Japanese, May 29, 1978.

For instance, let us consider parallel multiplication of two 8-bit numbers as shown in FIG. 1. In this Figure, A.sub.1 to A.sub.8 represent the bits of a multiplicand, while B.sub.1 to B.sub.8 the represent multiplier bits. a.sub.1 to a.sub.8, b.sub.1 to b.sub.8, c.sub.1 to c.sub.8, d.sub.1 to d.sub.8, e.sub.1 to e.sub.8, f.sub.1 to f.sub.8, g.sub.1 to g.sub.8 and h.sub.1 to h.sub.8 represent sets 10.sub.1, 10.sub.2, 10.sub.3, 10.sub.4, 10.sub.5, 10.sub.6, 10.sub.7 and 10.sub.8 of partial products and p.sub.1 to p.sub.15 represent the product bits. The sets of partial products result from multiplying the multiplicand by a specific bit of the multiplier.

The addition of the partial products described above is generally carried out in the two following ways.

(1) Carry save method: FIG. 2 illustrates that portion of an array circuit for performing parallel multiplication of two 4-bit numbers which corresponds to the partial products 10.sub.1 -10.sub.8 of FIG. 1. That is, partial products 12.sub.1, resulting from multiplying a multiplicand by respective bit of a multiplier, are applied to full adders 14.sub.1 to 14.sub.3 and a q.sub.8 (product bit) output. The most significant bit of next partial products 12.sub.2 is applied to a next-stage full adder 14.sub.4, while the remaining bits thereof are applied to full adders 14.sub.1, 14.sub.2, 14.sub.3 together with the three high-order bits of the preceding partial products 12.sub.1. As a result, the carries (C) of full adders 14.sub.1, 14.sub.2 and 14.sub.3 are supplied to next-stage full adders 14.sub.4, 14.sub.5 and 14.sub.6, respectively, and the sums (S) thereof are applied to full adders 14.sub.5 and 14.sub.6 and q.sub.7 (product bit) output. Similarly, in full adders 14.sub.4, 14.sub.5 and 14.sub.6, the carries (C) from full adders 14.sub.1, 14.sub.2 and 14.sub.3 are added to corresponding bits of partial products 12.sub.3 and the results are applied to full adders 14.sub.7, 14.sub.8 and 14.sub.9 and q.sub.6 output. Furthermore, full adders 14.sub.7, 14.sub.8 and 14.sub.9 add the carries (C) from full adders 14.sub.4, 14.sub.5 and 14.sub.6 to corresponding bits of partial products 12.sub.4 and then provide the resulting bits to high-speed adder 16 and q.sub.5 output. High-speed adder 16 provides high-order bits q.sub.1 -q.sub.4 of the product.

(2) Tree method: Unit blocks for performing an addition of a predetermined number of inputs are properly combined to perform addition for each digit of a product. FIG. 3 shows an 8-input adder for a set 20 of specific bits, for example, a.sub.1, b.sub.2, c.sub.3, d.sub.4, e.sub.5, f.sub.6, g.sub.7 and h.sub.8 included in partial products 10.sub.1 to 10.sub.8 shown in FIG. 1. In this example, a 3-input, 2-output full adder is used as the unit block. In FIG. 3, among the specific bits of the partial products 10.sub.1 -10.sub.8 of FIG. 1 a.sub.1, b.sub.2 and c.sub.3 are added together in full adder 22.sub.1, d.sub.4, e.sub.5 and f.sub.6 in full adder 22.sub.2, and g.sub.7 and h.sub.8 in full adder 22.sub.3. The carry outputs of full adders 22.sub.1 -22.sub.3 are applied to the higher order bits not shown, while the partial sums 24.sub. 1, 24.sub.2 and 24.sub.3 are directed to full adder 22.sub.4. The partial sum 24.sub.4 from full adder 22.sub.4 is applied to full adder 22.sub.6 together with the partial sum 24.sub.5 from full adder 22.sub.5 receiving carries from the lower order bits not shown. On the other hand, the carry from full adder 22.sub.4 is output to a higher order bit together with the carry from full adder 22.sub.5. Full adder 22.sub.6 adds together the partial sums 24.sub.4 and 24.sub.5 from full adders 22.sub.4, 22.sub.5 and a carry from a lower bit to provide the partial sum 24.sub.6 to full adder 22.sub.7. Full adder 22.sub.7 adds together the partial sum 24.sub.6 from full adder 22.sub.6 and a carry from the lower order bit to provide the carry and sum to a high-speed adder not shown. Such an adder circuit as described above is provided for each digit of the partial product sets 10.sub.1 -10.sub.8 to obtain the product (answer).

FIG. 4 shows the basic circuit arrangement of the full adder of 3-input, 2-output AND-OR form in the prior art described above.

In this Figure, an A input is applied to AND circuits 26.sub.1, 26.sub.4, 26.sub.5 and 26.sub.6, a B input to AND circuits 26.sub.2, 26.sub.4, 26.sub.5 and 26.sub.7, and a CO input to AND circuits 26.sub.3, 26.sub.4, 26.sub.6 and 26.sub.7. The A input is further applied to AND circuits 26.sub.2 and 26.sub.3 via an inverter 28.sub.1. Likewise the B input is applied to AND circuits 26.sub.1 and 26.sub.3 via an inverter 28.sub.2, and the C input to AND circuits 26.sub.1 and 26.sub.2 via an inverter 28.sub.3. AND circuits 26.sub.1 to 26.sub.4 feed their computational results to an OR circuit 30.sub.1, while AND circuits 26.sub.5 - 26.sub.7 provide their operational results to an OR circuit 30.sub.2. To the next stage (higher order bit), the output of OR circuit 30.sub.1 as the sum (S) and the output of OR circuit 30.sub.2 as the carry (C) are applied.

According to the carry save method described above, LSIs can implement the parallel multiplication by the use of a highly regular layout of circuit components. However, an array of (n-1) full adders is needed to add together n partial products. Hence problems associated with the above approach lie in the need of long signal transmission paths. The long signal transmission paths will slow the computing speed.

According to the tree method, on the other hand, the number of full adders to path through may be small. In this respect the computation can be speeded up. However, since the blocks in the prior art are wired by the use of first and second metal wiring layers formed on a semiconductor substrate, an increase in wiring in number between the blocks will result in the complication of wiring of blocks and the need of a large number of steps in pattern layout. In addition, the increase of wiring in number will increase the area of an LSI chip as well, resulting in a problem that high-speed processing is impeded.

It is accordingly an object of the present invention to provide a semiconductor device with a parallel multiplier using at least three wiring layers, which permits the speeding up of computation without increasing the area of an LSI chip and avoids the need for a large number of steps in pattern layout.

According to an aspect of the present invention, there is provided a semiconductor device with a parallel multiplier comprising: a plurality of partial product producing means for forming partial products by multiplying one of a multiplier and a multiplicand by a specific bit of the other of the multiplier and multiplicand; a plurality of first connection and wiring means having at least two sets of ends, a first set of ends connected to said plurality of partial product producing means to receive the partial products formed by said partial product producing means; at least two partial sum producing means connected to a second set of ends of said first connection and wiring means for adding specific bits of said partial product producing means in blocks; at least two second connection and wiring means having at least two sets of ends, a first set of ends connected to said first partial sum producing means to receive results of addition obtained from said first partial sum producing means; and second partial sum producing means connected to a second set of ends of said second connection and wiring means for adding together the results of addition in blocks obtained from said first partial sum producing means, said first and second connection and wiring means being formed of a first metal wiring layer for transmitting results obtained from said plurality of partial product producing means in a first direction and a second metal wiring layer formed above said first metal wiring layer for transmitting said results in a second direction nonparallel to said first direction, and at least one of said first and second connection and wiring means further comprising a third metal wiring layer formed above said second metal wiring layer.

According to another aspect of the present invention, there is provided a semiconductor device with a parallel multiplier comprising: a plurality of partial product producing means for forming partial products by multiplying one of a multiplier and a multiplicand by a specific bit of the other of the multiplier and multiplicand; a plurality of first connection and wiring means having at least two sets of ends, a first set of ends connected to said plurality of partial product producing means to receive the partial products formed by said partial product producing means; at least two first partial sum producing means connected to a second set of ends of said first connection and wiring means for adding specific bits of said partial product producing means in blocks; at least two second connection and wiring means having at least two sets of ends, a first set of ends connected to said first partial sum producing means to receive results of addition obtained from said first partial sum producing means; and second partial sum producing means connected to a second set of ends of said second connection and wiring means for adding together the results of addition in blocks obtained from said first partial sum producing means, one of said first and second connection and wiring means being formed of a first metal wiring layer for transmitting data in a first direction and a second metal wiring layer formed above said first metal wiring layer for transmitting data in a second direction nonparallel to the first direction, and the other of said first and second connection and wiring means being formed of a third metal wiring layer formed above said second metal wiring layer for transmitting data in a third direction nonparallel to at least said second direction.

According to still another aspect of the present invention, there is provided a semiconductor device with a parallel multiplier comprising: a plurality of partial product producing means for forming partial products by multiplying one of a multiplier and a multiplicand by a specific bit of the other of the multiplier and multiplicand; a plurality of connection and wiring means having at least two sets of ends, a first set of ends connected to said plurality of partial product producing means to receive the partial products formed by said partial product producing means, said connection and wiring means comprising a first metal wiring layer for transmitting results obtained from said plurality of partial product producing means in a first direction, a second metal wiring layer formed above said first metal wiring layer for transmitting said results in a second direction nonparallel to said first direction, and a third metal wiring layer formed above said second metal wiring layer for transmitting said results in a third direction nonparallel to at least the second direction; at least two partial sum producing means connected to a second set of ends of said first connection and wiring means for adding specific bits of said partial product producing means in blocks.

The aforementioned aspects and other features of the present invention are explained in the following description, taken in connection with the accompanying drawings in which:

FIG. 1 illustrates the process of parallel multiplication in a prior art;

FIG. 2 is a schematic diagram of a prior art parallel multiplier for the carry save method;

FIG. 3 is a schematic diagram of a prior art parallel multiplier for the tree method;

FIG. 4 is a basic circuit diagram of a prior art full adder of AND-OR type;

FIG. 5 is a schematic plan view of the main portion of a semiconductor device according to an embodiment of the present invention;

FIG. 6 is a sectional view of the semiconductor device of FIG. 5;

FIG. 7 schematically illustrates a circuit arrangement according to an embodiment of the present invention;

FIG. 8 is a plan view showing a partial sum producing circuit arrangement according to another embodiment of the present invention; and

FIG. 9 is a schematic plan view of the main portion of a semiconductor device according to still another embodiment of the present invention.

Preferred embodiments of the present invention will now be described with reference to the drawings in which like reference characters are used to designate corresponding parts in the prior arts described above and the description thereof will be omitted.

FIG. 5 illustrates an arrangement for implementing adder 20 for the specific bits of the partial product sets in the prior art shown in FIG. 1. The device of this embodiment is adapted for the tree method of FIG. 3. In FIG. 5, 32.sub.1, 32.sub.2 and 32.sub.3 designate unit blocks each serving as a partial sum producing circuit for specific bits. For example, partial sum producing circuit 32.sub.1 is adapted to add together specific bits a.sub.1, b.sub.2 and c.sub.3 in full adder 22.sub.1, the resulting partial sum 24.sub.1 being output to full adder 22.sub.4 and the carry to the higher order bit not shown.

Likewise partial sum producing circuit 32.sub.2 is adapted to add together specific bits d.sub.4, e.sub.5 and f.sub.6 in full adder 22.sub.2, the resulting partial sum 24.sub.2 being output to full adder 22.sub.4 and the carry to the higher order bit not shown. Partial sum producing circuit 32.sub.3 is adapted to add together specific bits g.sub.7 and h.sub.8 in full adder 22.sub.3, the resulting partial sum 24.sub.3 being output to full adder 22.sub.4 and the carry to the higher order bit not shown.

Referring now to FIG. 6, bit adder section 20 includes a first metal wiring layer 36 formed on a substrate 34. A first insulating layer 38 is formed on substrate 34 with first metal wiring layer 36 formed thereon. A contact hole 40 is formed in a desired position of first insulating layer 38 to expose first metal wiring layer 36. A second metal wiring layer 42 is then formed on first insulating layer 38 normally vertical to first metal wiring layer 36. First and second metal wiring layers 36 and 42 are formed to intersect each other, thus contact each other through contact hole 40. A second insulating layer 44 is formed on second metal wiring layer 42. Subsequently on second insulating layer 44 is formed a third metal wiring layer 48 which is adapted to contact second metal wiring layer 42 through a contact hole 46. Third metal wiring layer 48 is formed normally vertical to second metal wiring layer 42.

For connections of bits a.sub.1, b.sub.2 and c.sub.3 to full adder 22.sub.1 in partial sum producing circuit 32.sub.1, bits d.sub.4, e.sub.5 and f.sub.6 to full adder 22.sub.2 in partial sum producing circuit 32.sub.2 and bits g.sub.7 and h.sub.8 to full adder 22.sub.3 in partial sum producing circuit 32.sub.3, first and second metal wiring layers 36 and 42 are utilized. For connections 50.sub.1, 50.sub.2 and 50.sub.3 of partial sums 24.sub.1, 24.sub.2 and 24.sub.3 output from full adders 22.sub.1, 22.sub.2 and 22.sub.3, to full adder 22.sub.4, third metal wiring layer 48 is utilized. The same is true of connections among full adders 22.sub.4 to 22.sub.7. Therefore, the connections among inputs and outputs of full adders 22.sub.1 to 22.sub.7 are each made by third metal wiring layer 48 or a metal layer not shown which may extend over the third metal wiring layer.

As described above, third metal wiring layer 48 is used for connecting wires 50.sub.1, 50.sub.2 and 50.sub.3. Likewise third metal wiring layer 48 may also be used for connection wires 50.sub.4, 50.sub.5 and 50.sub.6 between full adders 22.sub.4 and 22.sub.6, 22.sub.5 and 22.sub.6, and 22.sub.6 and 22.sub.7, for wires for connecting carries from lower order bits not shown to full adder 22.sub.5, and for wires for connecting carries from lower order bits not shown to full adders 22.sub.6 and 22.sub.7. The same is true of connection of the carry output from each of full adders 22.sub.1 to 22.sub.7.

FIG. 7 shows one example of an arrangement for implementing an adder for set 20 of partial products a.sub.1 to h.sub.8. In this example, an array 54 of full adders serving as partial sum producing circuits is used for adding together partial products obtained from partial product producing circuits 52.sub.1, 52.sub.2 and 52.sub.3. Likewise an array 56 of full adders is used for adding together partial products obtained from partial product producing circuits 52.sub.4, 52.sub.5 and 52.sub.6, while an array 58 of full adders is used for adding together partial products obtained from partial product producing circuits 52.sub.7 and 52.sub.8. Partial product producing circuits 52.sub.1 to 52.sub.8 correspond to partial products 10.sub.1 to 10.sub.8, respectively. Reference numeral 60 designates a full adder for adding the result of full adders 54, 56, 58, while 62 a high-speed adder serving as a final adder. A portion 64 enclosed with dotted lines represents the whole of specific-bit adder 20 shown in FIG. 5. That portion of full adder 60 which is included in portion 64 involves full adders 22.sub.4 to 22.sub.7 described above.

As shown in FIG. 7, partial product producing circuits 52.sub.1 to 52.sub.3 and full adder array 54; partial product producing circuits 52.sub.4 to 52.sub.6 and full adder array 56; and partial product producing circuits 52.sub.7 and 52.sub.8 and full adder array 58 are grouped in block units. Circuits within each block unit are connected together by first and second metal wiring layers 36 and 42 shown in FIG. 6. Specific bit partial sum producing circuit 32.sub.1 of FIG. 5 corresponds to specific bits of each of these blocks, for example, specific bits of partial product producing circuits 52.sub.1 to 52.sub.3 and full adder array 54 within the portion 64. Connections of full adder arrays 54, 56 and 58 to full adder 60 are made by the use of third metal wiring layer 48.

By arranging as described above, the partial products produced by the partial product producing circuits are properly input to full adders 22.sub.1 to 22.sub.3, the outputs (partial sums) of full adders 22.sub.1 to 22.sub.3 are added together in full adders 22.sub.4 to 22.sub.7 and then the product (answer) is obtained through high-speed adder 62.

According to the present embodiment, by utilizing third metal wiring layer 48 for connections of inputs and outputs of full adders, jumping wiring is made possible to block units. This can decrease the area of a tree-type parallel multiplier and facilitate high-speed processing. In addition, the use of the third metal wiring layer reduces constraints imposed on the layout design of the partial products producing circuits and partial sum producing circuits, thus permitting flexibility in design. Furthermore, the partial product producing circuits and partial sum producing circuits can be implemented in a regular pattern.

FIG. 8 schematically shows a partial sum producing circuit of another embodiment of the present invention.

For example, first and second metal wiring layers 36 and 42 shown in FIG. 6 are used for connecting partial products a1' and c3' output from partial product producing circuits 66 and 70 to full adder 72, while third metal wiring layer 48 is used for connecting partial product b2' output from partial product producing circuit 68 to full adder 72. This will facilitate the layout of wiring and connection between full adder 72 and partial product producing circuit 68.

FIG. 9 shows still another embodiment of the present invention, in which the output of partial sum producing circuit 80 and the input of partial sum producing circuit 82 are connected together by a wire 84. In this case third metal wiring layer 48 is used for wire 84. The third metal wiring layer may be used for wiring and connections within partial sum producing circuit 80. Alternatively, only the first and second metal wiring layers may be used in 80. Although a partial product producing circuit or circuits may be placed between partial sum producing circuits 80 and 82, it is necessary only that the third metal wiring layer be used at least for wiring and connections between partial sum producing circuits. For this reason, even if another circuit or circuits are placed between circuits to be connected together, the use of the third metal wiring layer will facilitate the layout of wiring and connections.

With the above embodiments, the metal wiring layers are described as being composed of three layers. However, the number of the metal wiring layers need not be limited to three, and three or more metal wiring layers may be used. The way of dividing the partial product and partial sum producing circuit blocks is not limited to those described in connection with the above embodiments and may be carried out variously.