US 4,979,006 AGrant
Reverse Staggered Type Silicon Thin Film Transistor
Issue Date:1990-12-18
•1 Claims
•3 Drawing Sheets
Abstract
A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; and n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.
Metadata
Assignees
- Seikosha Co., Ltd.
- Nippon Precision Circuits Ltd.
Inventors
- Sakae Tanaka
- Yoshiaki Watanabe
- Katsuo Shirai
- Yoshihisa Ogiwara
Application Information
Application Number:US 3580350
Filing Date:1989-05-26
Priority Date:1988-05-30
Art Unit:253
Classifications
IPC:
H01L 2978
Field of Search:
35723.7;4.234;23.1;2
Patent Drawings (3 sheets)
Description
Background of the Invention
The present invention relates to a reverse staggered type silicon thin film transistor.
Research and development of a silicon thin film transistor as an active matrix type liquid crystal display device and a photosensor has been widely carried out.
FIG. 4 shows the above-described silicon thin film transistor, which includes an insulating substrate 1, a gate electrode 2 thereon, a gate insulating layer 3 thereon, a silicon film 4 thereon, an n-type silicon film 5 thereon and containing a suitable amount of n-type impurities, and a source electrode 6 and a drain electrode 7 thereon.
The transistor is formed such that gate electrode 2, and source electrode 6 and drain electrode 7, have gate insulating layer 3 and silicon film 4 between them. Moreover, gate electrode 2 is formed at a side or portion of insulating substrate 1, in relation to source electrode 6 and drain electrode 7, which side is denoted as a reverse staggered type silicon thin film transistor.
FIGS. 5 and 6 show two different static characteristics which vary as to the time of light illumination of the reverse staggered type silicon thin film transistor having the above-described structure. In the abscissa is shown a gate voltage Vg, and in the ordinate, a drain current Id, and the drain voltage Vd is 7.5 (V). In both instances, the silicon films 4 are made of amorphous silicon formed by the plasma CVD method, and the film forming temperatures T of the silicon films 4 are 250.degree. C. (FIG. 5) and 350.degree. C. (FIG. 6). The film thickness in either case is 150 (nm).
As is evident from a review of both figures, in the case where the silicon film was formed at 350.degree. C. (FIG. 6), both the on-current and off-current are higher. In a usual thin film transistor, it is preferable that the ratio of the on-current and off-current is as large as possible. However, in the case of the transistor shown in FIG. 5, the on-current is small, and in the case of the transistor shown in FIG. 6, the off-current is large, so that the characteristics of either transistor are not satisfactory.
Summary of the Invention
The present invention takes into account the above-described problems and has the object of providing a reverse staggered type silicon thin film transistor in which the on-current is large, but the off-current is small.
Brief Description of the Drawings
FIG. 1 is a cross-sectional view of a reverse staggered type silicon thin film transistor according to one embodiment of the present invention;
FIG. 2 is a graphical diagram showing the static characteristics of the above-described reverse staggered type silicon thin film transistor of FIG. 1;
FIG. 3 is a cross-sectional view of a reverse staggered type silicon thin film transistor according to another embodiment of the present invention;
FIG. 4 is a cross-sectional view of a conventional reverse staggered type silicon thin film transistor; and
FIGS. 5 and 6 are graphical diagrams showing the static characteristics of the conventional reverse staggered type silicon transistor of FIG. 4.
Description of the Preferred Embodiments
Referring to the drawings in detail, and initially to FIG. 1, a reverse staggered type silicon thin film transistor according to the present invention includes an insulating substrate 1, a gate electrode 2 thereon, a gate insulating film 3 thereon, a lower layer silicon film 4a contacting and formed on the above-described gate insulating film 3, an upper layer silicon film 4b contacting and formed below an n-type silicon film 5, and formed at a lower temperature than the film forming temperature of the above-described lower layer silicon film 4a, and a source electrode 6 and a drain electrode 7 formed thereon.
FIG. 2 shows the static characteristics which vary as to the time of light illumination of the reverse staggered type silicon thin film transistor having the above-described structure. The lower layer silicon film 4a and upper layer silicon film 4b are made of amorphous silicon formed by the plasma CVD method, and the film forming temperatures T.sub.1 and T.sub.2 and the film thickness t.sub.1 and t.sub.2 are respectively as shown below.
In the lower layer silicon film 4a,
and in the upper layer silicon film 4b,
A reverse staggered type silicon thin film transistor formed under the above-described conditions, in contrast to the conventional reverse staggered type silicon thin film transistor shown in FIGS. 5 and 6, has its on-current approximately equal to that shown in FIG. 6 (T=350.degree. C.), and its off-current to that shown in FIG. 5 (T=250.degree. C.). That is, the on-current depends on the film forming temperature of lower layer silicon film 4a in contact with gate insulating film 3, and the off-current to the film forming temperature of upper layer silicon film 4b in contact with n-type silicon film 5.
Therefore, by making the film forming temperature of upper layer silicon film 4b to be lower than the film forming temperature of lower layer silicon film 4a, as in the case of the above-described reversed staggered silicon thin film transistor, the ratio of the on-current to the off-current can be made large.
Also, in general, the silicon film can be made into a film of uniform thickness when the film forming temperature is as low as possible. Specifically, by making the film thickness of lower layer silicon film 4a of the high film forming temperature thinner, as described above, and by making the film thickness of upper layer silicon film 4b of the low film forming temperature thicker, it becomes possible to make the film thickness of the silicon film uniform and to increase the uniformity of the element characteristics.
FIG. 3 shows another embodiment of the present invention.
In this embodiment, as shown in FIG. 3, an intermediate silicon film 4c is provided between lower layer silicon film 4a and upper layer silicon film 4b. Although it is preferable that the above-described intermediate silicon film 4c is formed as the film forming temperature gradually lowers from the film forming temperature of lower layer silicon film 4a to the film forming temperature of upper layer silicon film 4b, there may be a region where the film is formed at a higher temperature than the film forming temperature of lower layer silicon film 4a, or at a lower temperature than the film forming temperature of upper layer silicon film 4b.
In the second embodiment, advantages similar to those described with respect to the first above-described embodiment can also be obtained.
Further, in the reverse staggered silicon thin film transistor shown in FIGS. 1 and 3, it is preferable with respect to the characteristics thereof that the film forming temperature of n-type silicon film 5 is lower than the film forming temperature of upper layer silicon film 4b, and further, that lower layer silicon film 4a, upper layer silicon film 4b, and so on are continuously formed without breaking the vacuum.
Also, lower layer silicon film 4a, upper layer silicon film 4b, and intermediate silicon film 4c may be formed by the use of polysilicon or the like rather than amorphous silicon, and as the film forming method thereof, an optical CVD method, or the like, rather than the plasma CVD method can be used.
According to the present invention, since it is possible to obtain a reverse staggered type silicon thin film transistor having a high on-current and low off-current, that is, having a large current ratio thereof, the element characteristics are improved with respect to application of the transistor.
Further, by making the film thickness of lower layer silicon film 4a of the high film forming temperature thin, and by making the film thickness of upper layer silicon film 4b of the low film forming temperature thick, the film thickness of the whole silicon film becomes uniform, and an increase in uniformity of the element characteristics can be achieved.
Having described specific preferred embodiments of the invention with reference to the accompanying drawings, it will be appreciated that the present invention is not limited to those specific preferred embodiments, and that changes and modifications can be made by one of ordinary skill in the art without departing from the spirit or scope of the invention as defined by the appended claims.
Claims
What is claimed is:
1. A reverse staggered type silicon thin film transistor, comprising: a gate electrode on a substrate; a gate insulating layer on said substrate and said gate electrode, said gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, said lower layer silicon film being formed at a first temperature; an upper layer silicon film formed on said lower layer silicon film at a second temperature which is lower than said first temperature, said lower layer silicon film having a first thickness of approximately 30 nm and said upper layer silicon film having a second greater thickness of approximately 120 nm; an n-type silicon layer on said upper layer silicon film and in contact therewith; a source electrode on said n-type silicon layer; and a drain electrode on said n-type silicon layer.
Patent Citations (5)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4746961 | 1988-05-01 | Konishi et al. | |
| JPX60-66864 | 1985-04-01 | ||
| JPX60-117781 | 1985-06-01 | ||
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