Analog-to-Digital Converter With Non-Linear Error Correction

FIGS. 1a through 12 illustrate A/D converters and associated circuitry used in the invention.

The error term expressed in equation (4) can be reduced by eliminating the coefficient of the C.sub.1 /2 term. Elimination of this term occurs by setting voltage V.sub.T =V.sub.REF /2. Equation (4) reduces to the following: ##EQU5##

FIG. 3 illustrates a schematic drawing of the circuit accomplishing the elimination of the linear error coefficient contribution as discussed above. This circuit is similar to the circuit of FIG. 2a with the following exceptions. As shown, a resistor divider 8 is used to derive the common mode input signal from differential inputs V.sub.IN+ and V.sub.IN-. During sampling, the top plates of both capacitor arrays are charged to this common mode voltage, causing v.sub.IND /2 (V.sub.IND =V.sub.IN+ -V.sub.IN-) to appear across the upper array and -V.sub.IND /2 to appear across the lower array. An optional unity gain buffer can be connected as shown to increase sampling speed. Switches connected to each capacitor in the arrays are labeled S, 1 and 1, with a corresponding subscript for capacitor association indication. Switch S is operable to connect to an input voltage for sampling while switches 0 and 1 connect either to reference voltage, Vref, or ground. Note that 0 and 1 can correspond to a multiplier of each array capacitor value. Successive approximation begins when all switches, O.sub.K (K being an integer) are closed and the most significant bit (sign bit) is determined. Notice that the 0.sub.N and 1.sub.N (MSB) switches are connected to the V.sub.REF and ground buses differently than all other 0.sub.K and 1.sub.K switches. This allows bipolar input signals and adds V.sub.REF /2 common-mode signal to the top plates. This common-mode level remains for the duration of the conversion, leaving V.sub.T =V.sub.REF /2 as desired. The circuit of FIG. 3, in addition to its cancellation of the error associated with the linear voltage coefficient, also offers another important advantage in that the common-mode voltage presented to comparator 6 remains independent of the input common-mode voltage of the converter. This relaxes the common-mode rejection requirement of the comparator.

When the sampling method of elimination of linear voltage error coefficient effects, as discussed above, is used, converter linearity to 15 bits can be achieved. Greater than 15 bit linearity will generally require quadratic voltage coefficient correction. Stated another way, the quadratic term in equation (3) must be canceled. This can be accomplished by subtracting the following component from equation (3): ##EQU6##

Removal of the quadratic error term involves the addition of a correction term which can be produced in part by a non-linear function generator. The non-linear function generator produces an output signal, Vo, proportional to V.sub.IN (V.sub.REF.sup.2 -V.sub.IN.sup.2). A gain factor produced, for example, by an array of capacitors having an adjustable gain multiplies the non-linear function generator output in order to achieve the necessary correction term. FIG. 4 illustrates a schematic diagram of an A/D converter similar to that shown in FIG. 3 with the addition of two non-linear function generators (a positive sign non-linear function generator for correcting negative error and a negative sign non-linear function generator for correcting positive error), a correction capacitor array CA for each generator, and switches between comparators 6, the generators, correction capacitor arrays and the main arrays of capacitors. The diagram of FIG. 4 also shows registers for use in carrying out successive approximation functions.

Assuming a predetermined non-linear function generator output, a method follows, for use with an A/D converter (specifically directed to the A/D converter of FIG. 4), which determines (adjusts/calibrates) the necessary gain factor used in error correction. A calibration circuit is used in connection with the gain factor calculation. FIG. 5 illustrates a possible part of this calibration circuit and shows two resistors, R.sub.1 and R.sub.2 in series connected to and between V.sub.REF and ground. Reference voltage V.sub.REF is selected as equal to the maximum input voltage V.sub.IN for the A/D converter of FIG. 4. An input voltage V.sub.1, which is lesser in value than V.sub.REF, results across resistor R.sub.1 and an input voltage V.sub.2 =V.sub.REF -V.sub.1 results across resistor R.sub.2. Voltages V.sub.1, V.sub.2 and V.sub.REF are input separately into the A/D converter and the digital outputs resulting therefrom are noted. With reference to FIG. 6, which illustrates a graph of the A/D transfer curve (digital words vs. voltage), it is seen that the ideal transfer characteristic (straight line) and the transfer characteristic with error (bowed line) are labeled. Note, that depending on the sign of the error that the bow in the characteristic DV1, DV2, and DVREF represent the digital word outputs (note that digital words are simply the digital representation, i.e. 10001001 and etc., of an analog signal) resulting from the inputs of the voltages V.sub.1, V.sub.2, and V.sub.REF respectively, to the converter. V.sub.1 ' and V.sub.2 ' are the digital outputs that would be produced if the converter operated ideally. Thus V.sub.1 '+V.sub.2' =V.sub.REF. However, assuming that the A/D converter introduces error, the error characteristic shown in FIG. 5 illustrates that DV1=(V.sub.1' +delta 1) and that DV2=(V.sub.2' +delta 2), where the deltas represent the deviation from the ideal characteristic. The addition of DV1 and DV2 equals DV.sub.REF +delta 1+delta 2. Subtracting DV.sub.REF from this quantity reveals the error of the converter such that the error=delta 1+delta 2=(DV1+DV2-DVREF). The sign of the capacitor array gain factor must be chosen. First, the gain of the adjustable capacitor CA is set equal to zero. If DV1+DV2-DVREF is greater than zero, then the sign of the needed gain factor is negative. Otherwise the gain factor is positive. If the gain factor is negative, then the negative sign non-linear function generator is required for error correction. On the other hand, if the gain factor is positive, then the positive sign non-linear function generator is required for error correction. After the proper sign of the capacitor array gain factor is chosen, the magnitude of the capacitor array gain factor is adjusted iteratively using binary search or other search techniques. Note that the negative non-linear correction array will output only zero to negative value outputs while the positive non-linear correction array will output only zero to positive value outputs. Assuming that the gain can be digitally represented and adjusted, one such binary search method is as follows:

(1) Set the gain G of the correction capacitor array at one half the maximum gain of the correction capacitor array.

(2) The most significant bit of gain factor G will be determined.

(3) Compute (DV1+DV2-DVREF) and subtract the (DV+DV2-DVREF) quantity used in determining the gain of the correction capacitor array. If the magnitude of the difference is increased, then the present bit of gain factor G is set equal to zero. Otherwise, if the magnitude of the difference is decreased, set the present bit of the gain factor equal to one. (Binary representations are assumed)

(4) Repeat step (3) for each bit of gain factor G.

With this method, the correction capacitor array gain factor is determined. Assuming on-chip correction circuitry, gain factor G must be adjusted/calibrated in the foregoing described manner each time the chip is powered up or every time out of tolerance temperature changes occur. This adjustment/calibration can easily be accomplished by digital control circuitry which may exist on the same chip.

A description of the non-linear function generator follows.

FIG. 7 illustrates a block diagram of the non-linear function generators discussed above and shown in FIG. 4. As shown, two squarer function circuits are connected to two multiplier circuits. A resistor R.sub.S is connected to and between each squarer/multiplier connection and ground. One squarer receives differential inputs V.sub.IN+ and V.sub.IN- from an input sampling network (not shown), while the other squarer receives differential inputs V.sub.REF+ and V.sub.REF- from another input sampling network (not shown). Likewise, the multiplier circuits receive differential inputs V.sub.IN+ and V.sub.IN- from a common input sampling network (not shown). The multipliers are connected together at two common nodes and each multiplier outputs two signals which result in a function generator differential output V.sup.D.sub.OUT existing between the common nodes and across two resistors R.sub.M and ground. Voltages V1 and V2 are shown as the voltage at the R.sub.S connection to the respective multipliers and squarers. Currents into the squarers and out of the multipliers are labeled. Plus and minus signs in connection with the letter D following a symbol represent differential signals. The symbol h.sub.S represents the squarer gain constant and the symbol h.sub.M represents the multiplier gain constant. I.sub.BO represents bias current. V.sub.REF.sup.D represents a differential reference voltage. The differential output of the non-linear function generator is as follows.

FIG. 8 illustrates a schematic drawing of the input sampling network referenced in the preceding paragraph which receives the inputs of an associated squarer or multiplier. The particular input sampling network is specifically directed to the input sampling network connected to the squarer circuits. As shown, the input sampling network comprises two capacitors C.sub.1 and two switches, S1 and S2, which are operable to close their connections in response to clock phases O.sub.1 and O.sub.2. The input sampling network of FIG. 1 is biased by voltage V.sub.B1. The sampling network is additionally biased by ##EQU7## after clock phase O.sub.2. The characteristic of a clock phase versus time is also illustrated in FIG. 8b.

FIG. 9 illustrates a schematic drawing of the squarer circuit. As shown, two N-channel transistors M.sub.1 and M.sub.2 are connected together at the respective source and drain regions of each as shown. The expressions for the drain currents for each transistor M.sub.1 and M.sub.2 are noted on FIG. 9. V.sub.TH represents transistor threshold voltage. Additionally note, on the Figure, the gate voltage of each transistor. Gain factor K.sub.1 can be expressed by the following: ##EQU8## where u is the channel mobility, C.sub.ox is the oxide capacitance per unit area, W the channel width, and L is the channel length.

FIG. 10 illustrates a schematic drawing of the multiplier circuit. The multiplier circuit comprises P-channel transistors M.sub.11, M.sub.12, M.sub.8, and M.sub.7 connected as shown with input voltages and currents as shown and discussed previously. Voltage V.sub.B3 is a bias voltage input to the non-linear function generator and voltage V.sub.DD serves as the supply voltage to the multiplier. Beta is the ratio of C.sub.2 to the quantity C.sub.2 plus C.sub.1 /2 where the subscripted Cs are from the input sampling network connected to the multiplier.

FIG. 11 represents the full blown non-linear function generator connected between voltages V.sub.DD and V.sub.SS. P-channel transistors M.sub.15 through M.sub.18 are also illustrated and serve to produce differential output V.sup.D.sub.OUT. The various transistors to the multipliers are labeled differently in each multiplier for easier identification. Additionally, other transistors and voltages are marked as shown, which contribute to the overall connection of the non-linear function generator, which was not shown in the block diagram of FIG. 7. As noted on FIG. 11, the differential output is as follows:

where K is equal to

Although the foregoing function generator has been described capable of producing the proper output, note that other function generators having entirely different structures are contemplated as being within the true scope and spirit of the invention when used for the purposes heretofore set forth.

FIG. 12 illustrates a schematic drawing of a differential capacitor array A/D converter using a single non-linear function generator. The generator can be connected to the appropriate capacitor array CA to correct for positive or negative errors. During A/D conversion, in the sampling mode the main array capacitors sample the input signal along with a correction circuit which comprises the correction capacitor arrays and the non-linear function generator. The correction circuit generates a correction proportional to the input voltage multiplied by the quantity of the reference voltage squared minus the input voltage squared. Coupled with the proper value of gain factor through the correction capacitor array, the signal from the correction circuit is introduced into the top plate of the main capacitor array during the hold operation or after sampling in order to eliminate the quadratic term error previously discussed.

Although the invention has been described in detail herein, with reference to its preferred embodiment, it is to be understood that this description is by way of an example only, and is not to be construed in the limiting sense. It is to be further understood that numerous changes in the details of the embodiments of the invention, and additional embodiments of the invention, will be apparent to, and may be made by persons of ordinary skill in the art having reference to this description. Note that N-channel transistors disclosed in the foregoing can be substituted with P-channel transistors and vice versa. Additionally, bipolar transistors can be substituted for the field effect transistors shown. Although metal oxide semiconductor MOS (where oxide in its commonly accepted meaning with reference to the term MOS generally encompasses all insulative material) are implicitly assumed throughout, other types of field effect transistors are contemplated as being within the scope of the invention. Note that A/D converters using successive approximation techniques having resistors instead of capacitors is additionally contemplated as being within the scope of the invention. Moreover, other A/D converter operation which simulates the weighted order of the capacitors can also benefit from the invention. Additionally, other A/D converter architecture can be used in connection with the invention and the foregoing specific examples of A/D converters using the invention were given for example only. It is contemplated that all such changes and additional embodiments are within the true scope and spirit of the invention as claimed below.