US 4,975,596 AGrant
Automatically Stabilized Latched Differential Comparator With Single Clock
Issue Date:1990-12-04
•6 Claims
•2 Drawing Sheets
Abstract
A differential comparator, working with microwaves and using only one clock, is disclosed. This comparator has a differential amplifier and a divergence circuit in which are included two voltage level translators. The coupling between the amplifier and the divergence circuit is made at the gates of the load transistors of the divergence circuit. Two insulation transistors, working in either saturated mode or resistive mode, are used to provide the amplifier with an automatic control loop which stabilizes all the rest voltages. The clock signal, applied to two transistors which short circuit the two feedback transistors of the divergence circuit, controls the passage from the measuring phase to the divergence phase.
Metadata
Assignee
- Thomson Hybrides et Microondes
Inventors
- Francois Thomas
- Bertrand Campagnie
Application Information
Application Number:US 2755149
Filing Date:1988-11-23
Priority Date:1987-11-27
Art Unit:254
Classifications
IPC:
H03K 3356H03K 524
Field of Search:
307350;530;355;362;279;291
Patent Drawings (2 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention concerns an electronic circuit which is an automatically stabilized, latched differential comparator with pre-amplification and with a single clock. This comparator is designed to work at very high speeds (with microwaves of up to several gigahertz): its single clock, its automatically stabilized rest voltages and its architecture are such that it is affected very little by technological variations in the manufacture of transistors which cause measuring errors or instability.
This comparator has been designed to be made in integrated circuit form using III-V group materials such GaAs but, of course, it can also be made of silicon without going beyond the scope of the invention: only its working speed is lower.
2. Description of the Prior Art
Differential latched comparators use the mechanism of positive feedback the difference in voltages between inputs is found again, after amplification, at the outputs (measurement phase). It is then that these signals are re-injected into the inputs (divergence phase). The fact of looping the outputs back to the inputs leads to a fast amplification of the voltage differences
A structure of this type, provided with a balance-resetting circuit, becomes very valuable since it enables the making of comparators with a very small flip-over time.
FIG. 1 gives an example of an electrical diagram of a latched comparator with imbricated differential stages, according the prior art.
The input signals, E.sub.1 and E.sub.2, addressed to the gates of the transistors T.sub.6 and T.sub.7, are coupled with the output signals S.sub.1 and S.sub.2, taken at the gates of the transistors T.sub.8 and T.sub.9, namely also at the drains of the transistors T.sub.6 and T.sub.7. In this architecture, it is necessary to have two complementary clocks, H.sub.1 and T.sub.2, the pulses of which are applied to the gates of the transistors T2 and T3.
This comparator has two imbricated differential stages: an internal stage T.sub.2 +T.sub.4 +T.sub.5 +T.sub.8 +T.sub.9 and an external stage T.sub.3 +T.sub.6 +T.sub.7 +T.sub.8 +T.sub.9. In this structure, the passage from the measuring phase to the divergence phase is achieved by switching over the current of the external differential stage to the internal differential stage by means of clocks and transistors, T.sub.2 +T.sub.3, whereupon the divergence starts.
The voltage level translators (T10, D1, D2, D3, T12) and (T11, D4, D5, D6, T13) are indispensable to compensate for the difference in resting levels existing between the inputs and the outputs.
The drawbacks related to this structure are chiefly:
the need for complementary clocks H.sub.1 and H.sub.2 without overlapping,
the lack of sensitivity, due to the injection of charges during switching-over operations,
the absence of stabilization of resting levels to cope with technological imperfections, because it is not always verified that:
the instability of the output signals due to switching-over of current when going from the external stage to the internal stage and vice versa.
A comparator according to the invention makes it possible to overcome these drawbacks through:
compensation for technological variations, due to the stabilization of voltages,
operation with a single clock,
high sensitivity of elimination of the transfer of current between the internal circuit and the external circuit.
The invention uses circuit elements known per se, such as a differential amplifer at input, a divergence circuit and voltage level translators at output, but the coupling between the differential amplifier and the divergence circuit is achieved by means of two voltage followers which isolate the amplifer from the divergence circuit. The rest voltage at the outputs of the amplifier may then be imposed by a automatic control loop. The coupling between the differential amplifier and the divergence circuit is achieved on the gate of the load transistors of this circuit, said transistors being themselves mounted in series, each with an insulation transistor which can work either in resistive mode or in saturated mode.
Summary of the Invention
More precisely, the invention concerns a latched, differential comparator working at very high frequencies, comprising a differential amplifier, to the inputs of which are applied the signals to be compared, and a divergence circuit in two arms which are symmetrical with the outputs of the amplifier, said divergence circuit comprising, for each arm, three series-mounted transistors, namely a feedback transistor, an insulating transistor and a load transistor, and one voltage level translator, the outputs of the comparator being taken at the outputs of the voltage level translators; a latched differential comparator wherein the coupling between the outputs of the differential amplifier and the divergent circuit is made at the gates of the load transistors of the divergence circuit.
Brief Description of the Drawings
The invention will be better understood and its operation and advantages will emerge more clearly from the following more detailed description, made with reference the appended figures, of which:
FIG. 1 shows an electrical diagram of a prior art latched comparator which has already been described,
FIG. 2 shows an electrical diagram of an automatically stabilized, latched comparator with a single clock, according to the invention.
Description of a Preferred Embodiment
The differential comparator according to the invention, shown in FIG. 2, has the following groups of elements:
a pre-amplification circuit which receives the input signals at its inputs, El and E2. It is formed by a known type of cascaded amplifier which groups together the transistors T.sub.14 to T.sub.20.
an automatic control loop T.sub.21, D.sub.1 to D.sub.6, T.sub.22 which enables the stabilizing of the rest voltages at the outputs S.sub.1 and S.sub.2 of the pre-amplifier,
a divergence circuit which is formed by the coupling transistors, T.sub.23 and T.sub.24, the insulation transistors, T.sub.25 and T.sub.26, and the differential feedback transistors, T.sub.27, T.sub.28 and T.sub.29, and is complemented by two voltage level translators, T.sub.30, D.sub.8, D.sub.9, T.sub.32 and T.sub.31, D.sub.10, D.sub.11, T.sub.33,
the transistors for resetting the balance of the unit, namely the transistors, T.sub.34 and T.sub.35 which are parallel mounted with the feedback transistors, T.sub.27 and T.sub.28, the signal of the single clock H being applied to the gate of these transistors T.sub.34 and T.sub.35.
The output O.sub.1 of the comparator is taken at the drain of the transistor 33 of the voltage level translator, and is simultaneously looped to the gate of the feedback transistor T.sub.27, and the output O.sub.2, taken at the drain of the transistor T.sub.32, is looped to the gate of T.sub.28.
The unit is supplied between two analog voltages, V.sub.DD and V.sub.SS : these voltages are not all shown in FIG. 2, solely in order to avoid burdening this figure.
The number of diodes, which is six in this automatic control loop and two in each voltage level translator, does not limit the scope of the invention: it corresponds to a technology using GaAs, but may differ according to the technology implemented. These diodes may be replaced by resistors or transistors in technologies having no diodes.
Let SIA and SIB designate the intermediate outputs, between the coupling and insulation transistors T.sub.23 and T.sub.25, T.sub.24 and T.sub.26, and let SA and SE the intermediate outputs applied to the voltage level translators T.sub.30 and T.sub.31.
The transistors used in this assembly are all of the normally on type, i.e. they are conductive if no voltage is applied to their gates.
In brief, this comparator works as follows
The pre-amplification circuit amplifies the voltage difference between the two inputs, E1 and E2. The signals present at the outputs, S1 and S2, of the pre-amplification differential circuit are sent to the divergence stage by means of an original coupling mode, by the load transistors, T.sub.23 and T.sub.24, of the divergence stage If the clock H is at the low logic level, T.sub.27 and T.sub.28 are on, T.sub.34 and T.sub.35 are off, and the divergence starts since the output signals are sent to the inputs of the divergence stage (the gates of T.sub.27 and T.sub.28). After the divergence of SA and SB, the circuit is restored to balance by placing the clock H at the high logic level, following which a divergence cycle can be started again.
In a more detailed way, a comparison has to be made between the voltage at El and the voltage at E2. The voltage difference V (E1)-V (E2) is then amplified by a factor G which is the gain of the amplifier. We then have:
Thereafter, it is necessary to consider two phases of operation:
phase 1: the clock H is in the high logic state: the transistors T.sub.34 and T.sub.35 are on; T.sub.27 and T.sub.28 are therefore short-circuited. The insulation transistors T.sub.25 and T.sub.26 are not saturated because the width of their gates is between that of the gate of the current source T.sub.29 and that of the gate of the coupling transistors T.sub.23 and T.sub.24. As a non-restrictive example, T.sub.23 and T.sub.24 have a gate width of 5 microns, T.sub.25 and T.sub.26 have a gate width of 7.5 microns, and T.sub.29 has a gate width of 10 microns. For, since the intensity imposed by a current source (a transistor having a null gate/source voltage) is proportionate to the size of the transistor, and since 2.times.7.5=15>10, T.sub.25 and T.sub.26 cannot both be simultaneously saturated. T.sub.25 and T.sub.26 therefore work in resistive mode.
Consequently, the two symmetrical sets formed by the coupling, insulation and balance-resetting transistors, PG,10 T.sub.23 +T.sub.25 +T.sub.34 and T.sub.24 +T.sub.26 +T.sub.35, form two follower/shifter circuits. For the gate/source voltage of T.sub.34 is equal to that of T.sub.35 and the current in the left-hand arm is equal to that in the right-hand arm. The gate-source voltages of T.sub.23 and T.sub.24 are therefore equal. Thus, the difference VS1-VS2 is carried over to between the points SIA and SIB.
Since T.sub.25 and T.sub.26 are identical, crossed by one and the same current and working in resistive mode, their drain/source voltages are equal. We thus deduce therefrom that:
It is after this pre-amplification that the divergence phase can start.
Phase 2: in the divergence phase, the clock H is at the low logic level: T.sub.34 and T.sub.35 are off and no longer play a role in the operation of the circuit. T.sub.27 and T.sub.28 are thereafter no longer short-circuited. We are dealing here with a standard type of latched differential circuit. The voltage difference V(SA)-V(SB) is reinjected into the gates of T.sub.27 and T.sub.28 by means of two voltage level translators. There is then a divergence between the voltages at SA and SB. This is a very fast phenomenon. In this case, one of the transistors, T.sub.25 or T.sub.26, works in a saturated mode.
In short, a small difference between the voltages at E1 and E2 quickly leads to a big difference between the output voltages O.sub.1 and O.sub.2.
The originality of this architecture lies in:
the coupling mode between the pre-amplification stage and the divergence stage by the load transistors, T.sub.23 and T.sub.24, of this divergence stage,
the presence of the insulation transistors T.sub.25 and T.sub.26 which can work, sometimes in resistive mode and sometimes in saturated mode, and the role of which shall be explained further below,
the automatic control loop, which is permitted by the insulation of the pre-amplifier due to the coupling mode and which stabilizes the rest voltages.
the single clock,
the stabilization and single clock being advantages created by the coupling mode.
With respect to the stabilization of all the rest voltages, the automatic control loop, T.sub.21, D.sub.1 to D.sub.6, T.sub.22, has the role of stabilizing the rest voltages at S1 and S2 by automatic control of the current in T.sub.14, and by means of the coupling mode used between the pre-amplification circuit and the divergence circuit. Since it has been shown that, in the measuring phase (with the clock at the top state), the elements T.sub.23, T.sub.25, T.sub.34 as well as T.sub.24, T.sub.26, T.sub.35 form two voltage followers, the rest voltages at SA and SB are imposed. Furthermore, since the elements T.sub.30, D.sub.8, D.sub.9, T.sub.32 and T.sub.31, D.sub.10, D.sub.11, T.sub.33 also form voltage followers, the resting levels of O1 and O2 are also imposed. In short, the above-described automatic control loop stabilizes all the rest voltages of the circuit.
The need for a single clock H, which is easier to make than two complementary clocks, to pass from the measuring phase to the divergence phase warrants the presence of the insulation transistors T.sub.25 and T.sub.26.
In the standard latched comparators, there have to be complementary clocks to make it possible to send, alternately, to the inputs, the voltages to be measured (measuring phase) and those obtained at the differential outputs (divergence phase).
These two phases can be achieved with a single clock. When the clock H is the low logic state, the comparator is in the divergence phase. When the clock is in the high logic state, the difference V(SA)-V(SB) is equal to G(V(E1)-V(E2)). In the divergence phase, the inputs El and E2 no longer have any effect on the direction of the divergence if the input signals can no longer make the comparator change its decision: this is made possible by the insulation transistors, T.sub.25 and T.sub.26. Let us consider the operation steps:
step 1: let us assume that V(S1)-(V(S2) is small. Then V(SA)-V(SB) is also small during the measuring phase.
step 2: the divergence phase begins The voltages SA and SB will diverge greatly from their resting levels Let us also assume that the sign of V(E1)-V(E2) is positive while V(S1)>V(S2) and V(SA)>V(SB), and during the divergence phase, V(SA) increases while V(SB) decreases greatly.
It is deduced therefrom that the difference in voltage between S2 and SB increases. This tends to cause an increase in the current in T.sub.23. However, this current is limited by T.sub.25 which gets into saturated mode Thereupon, the voltage S2 no longer has any influence on V(SB) since these two nodes are connected by a current source.
As for the right-hand arm, the voltage between S1 and SA decreases and T.sub.26 gets into resistive mode.
step 3: if a sudden variation in the input voltages leads to the fact that V(S1)-V(S2) changes its sign (V(S1)<V(S2)) during the divergence phase, hence before the system is in the measurement phase, it has been seen earlier that S2 no longer influences SB and that, therefore, owing to the differential nature of the circuit, V(S1)-V(S2) no longer acts on the sign of V(SA)-V(SB).
In short, when the divergence phase has begun, the input signals can no longer make the system change its decision before returning to the measurement phase.
Claims
What is claimed is:
1. A latched, differential comparator operating at high frequencies for comparing a first signal and a second signal, said comparator comprising: a differential amplifier having a first input and a second input for receiving said first and second signals respectively and for providing first and second amplified output signals; a divergence circuit having a first portion and a second portion for respectively receiving said first amplified output signal and said second amplified output signal of said differential amplifier, said divergence circuit comprising, for each portion, three series-mounted gated transistors including a feedback transistor, an insulating transistor, and a load transistor, and a voltage level translator, wherein the output of each of said voltage level translators of said first portion and said second portion provide the output of said comparator; said latched differential comparator being characterized in that a coupling between said first amplified output signal and said second amplified output signal of said differential amplifier and the divergence circuit occurs at the gates of said load transistors of said divergence circuit.
2. A latched, differential comparator according to claim 1 further including a gated current transistor acting as a current source and wherein, in each portion of the divergence circuit, the insulation transistors have a gate width which is smaller than the gate width of said current transistor which is the current source of the divergence circuit, but is greater than the gate width of the load transistors of the divergence circuit, and consequently work either in resistive mode or in saturated mode.
3. A latched, differential comparator according to claim 1, wherein the insulation and load transistors insulate the differential amplifier from high amplitude signals present in the divergence circuit.
4. A latched, differential comparator according to claim 1, further comprising two gated balance resetting transistors, each mounted in parallel with one of the feedback transistors of the divergence circuit wherein a single clock signal is applied to the gates of said two resetting transistors.
5. A latched, differential comparator according to claim 1, wherein all the transistors of the circuit are of the normally on type.
6. A latched, differential comparator according to claim 1, made in integrated circuit form with a material of the III-V group such as GaAs.
Patent Citations (9)
Non-Patent Literature (2)
- IEEE Journal of Solid State Circuits, vol. SC-12, No. 5, Oct. 1977, pp. 497-501; T. R. O'Connel, et al.
- IEEE 1983, International Symposium on Circuits and Systems, May 2-4, 1983, vol. 3, pp. 1286-1289; P. E. Allen, et al.