Arrangement for Generating an SSB Signal

The present invention relates to an arrangement for generating an SSB signal and has applications in both the analogue and conventional digital implementations single sideband modulators constructed in accordance with what is termed Weaver's method. Such modulators are used in SSB generation in speech and data transmission for mobile radios.

Weaver's method is disclosed in Proceedings of the IRE "A Third Method of Generation and Detection of Single-Sideband Signals" Donald K. Weaver, Jr., pages 1703 to 1705. FIG. 1 of the accompanying drawings illustrates a modulator made in accordance with Weaver's method. An analogue input signal at an input 10 is band limited in a bandpass filter 12 and then is applied to balanced mixers 14, 16 where it is mixed with quadrature related carrier signals cos (.omega..sub.o t) and sin (.omega..sub.o t), where .omega..sub.o t is a carrier frequency corresponding to the centre of the passband of the signal from the filter 12. As a result of these mixing operations quadrature related signals I and Q are produced which have single sideband components at base band and unwanted components at high frequencies. The wanted components of the I and Q signals are selected by low pass filters 18, 20 and then frequency up-converted to their carrier frequency (.omega..sub.c t) in balanced mixers 22, 24. The signals from these mixers are combined in a summing circuit 25 to provide an output on a terminal 26.

In data transmission a similar arrangement to that shown in FIG. 1 is used to frequency up-convert the baseband I and Q modulated signals corresponding to the data. Weaver's method may also be used to generate constant envelope signals suitable for mobile radio digital transmission.

A drawback to Weaver's method is that it is difficult to implement the frequency up-converting or RF section as an integrated circuit. Reasons for this difficulty include the fact that matching of the mixers 22, 24 (FIG. 1) is complicated and it may be necessary to run the mixers at a high power level to achieve the desired performance. Also it is necessary to make a pair of quadrature local oscillators capable of generating a wide range of frequencies. Any mismatch in the mixers or any imperfection in the quadrature RF signal generation may cause the unwanted signal levels to increase.

Mismatch problems mentioned above can be overcome by generating digital samples of the RF local oscillators and using digital multipliers instead of the RF mixers. This is shown in FIG. 2 of the accompanying drawings which illustrate a conventional digital implementation of Weaver's method. In FIG. 2 the output of the bandpass filter 12 is digitised in an analogue-to-digital converter 28 which is sampled at a clock frequency f.sub.s1. The digitised signals are applied to mixers 14, 16 which respectively receive digitised local oscillator signals cos [(2.pi.f.sub.1.(m/f.sub.s1)] and sin (2.pi.f.sub.1.m/f.sub.s1). The I and Q signals from the mixers are low pass filtered in digital filters 18, 20 which are clocked at the frequency f.sub.s1 which satisfies the Nyquist sampling rate. The output signals which have been sampled at f.sub.s1 are applied to respective interpolators 30, 32 operating at a sampling frequency N.sub.fs. The outputs of the interpolators 30, 32 are frequency up-converted in digital multipliers 34, 36 to which are supplied quadrature carrier signals cos [2.pi.f.sub.c.(n/Nf.sub.s)] and sin [2.pi.f.sub.c.(n/Nf.sub.s)], respectively. The outputs from the digital multipliers 34, 36 are combined in the summing circuit 25 and the R.F. output appears on the terminal 26. This digital implementation of Weaver's method enables a performance improvement to be achieved at the expense of increased power consumption as digital multipliers require more power than the equivalent analogue mixers. The generation of RF quadrature signal samples raises another problem for radio transmitter integration when constant frequency sampling is required at RF. The sine and cosine samples can be generated by using either look-up tables or on-line processing but neither method is attractive for integration.

An object of the present invention is to provide an integratable SSB generator which is economical in its use of power.

According to a first aspect of the present invention there is provided an SSB generator comprising means for providing quadrature related digitised first and second input signals at baseband frequencies, interpolating means for frequency up-converting said first and second signals, and multiplexing means coupled to the interpolating means for multiplexing the frequency up-converted first and second input signals to provide a digitised SSB signal having a desired carrier frequency.

The interpolating means may comprise first and second interpolating means, the first interpolating means serving to sample respectively the first and second signals at a frequency (f.sub.s) greater than the digitising frequency and the second interpolating means serving to sample the signals from the first interpolating means at a multiple of the first mentioned sampling frequency. The multiplexing means may be arranged to multiplex the samples at the sampling frequency of the second interpolating means.

Implementing the interpolating means as first and second interpolating means enables each to be adapted to the task required of it. The first interpolating means operates as a digital filter and serves to increase the repetition rate of the signal from a digital low pass filter to make it suitable for linear interpolation in the second interpolating means. The second interpolating means operates as a linear interpolator which lifts the frequency up to RF.

In an embodiment of the present invention the sampling frequency used in the second interpolation operation is 4N times the sampling frequency (f.sub.s) used in the first interpolation operation, that is 4Nf.sub.s, and the multiplexing operation is carried out at a clock frequency of 4Nf.sub.s to provide the SSB signal at Nf.sub.s.

The multiplexed output may be interpolated for a third time in order to shift the sampling frequency 4Nf.sub.s to a higher frequency outside the bandwidth of a low pass filter connected to a digital to analogue converter coupled to the multiplexing means.

The second interpolation means may be adapted to calculate the values of all the samples of the frequency up-converted first and second digitised signals. Alternatively power can be saved by only calculating the values of those samples which after multiplexing will contribute to the final signal. In order to do this only the odd-numbered samples in one of the first and second interpolated signals are calculated and only the even-numbered samples in the other of the first and second interpolated signals are calculated.

The present invention will be explained and described, by way of example, with reference to the accompanying drawing.

FIG. 1 is a block schematic diagram of an analogue modulator constructed in accordance with Weaver's method,

FIG. 2 is a block schematic diagram of a digitised modulator constructed in accordance with Weaver's method,

FIG. 3 is a block schematic diagram of an embodiment of an SSB modulator made in accordance with the present invention,

FIG. 4 shows the impulse response of an interpolating filter,

FIG. 5 shows the frequency response of an interpolating filter,

FIG. 6 shows the impulse response of an interpolating filter,

FIG. 7 shows two samples taken from the impulse response shown in FIG. 6, which samples are separated in time by 1/f.sub.s,

FIG. 8 is a block schematic diagram of a linear interpolation filter,

FIG. 9 is a block schematic diagram of an embodiment of a SSB modulator including the linear interpolation filter shown in FIG. 8, and

FIG. 10 is a block schematic diagram of another embodiment of an SSB modulator including an alternative linear interpolation filter to that shown in FIGS. 8 and 9.

In the drawings, the same reference numerals have been used to indicate corresponding features.

Referring to FIG. 3, the SSB modulator shown is essentially the same as that shown in FIG. 2 as far as the interpolators 30, 32 which are operating at a sampling frequency, f.sub.s, which is of the order of 30 times higher than the frequency at the top end of the bandwidth of the low pass filters 18, 20. The outputs from the interpolators 30, 32 are applied to second interpolators 38, 40 operating at a higher sampling frequency, Nf.sub.s, than f.sub.s. The outputs from the second interpolators 38, 40 are multiplexed in multiplexer 42 to provide an output comprising the SSB signal centred on Nf.sub.s /4 plus the sampling frequency component in the output from the multiplexer, the output is applied to a third interpolator 44 which has a sampling frequency which is an integer multiple of Nfs. A digital to analogue converter 46 is connected to the third interpolator 44 and provides an output on the terminal 26. By this technique the frequency band of the SSB signal is maintained around f.sub.s whilst the Nf.sub.s component is frequency up-converted to a frequency which lies outside the pass bandwidth of a filter in the DAC 46. If desired a superhet stage may be connected to the output 26 to increase the frequency of the SSB signal which in such a situation represents an IF signal.

FIG. 4 shows the impulse response of an interpolating filter which may comprise the second interpolator 38 or 40. The ordinate represents amplitude and the abscissa time. The filter's response lasts two bit periods .+-.T.sub.s, where T.sub.s =1/f.sub.s, and has a sin .sup.2 x/x.sup.2 type of transfer function. The response shape is sampled at N times the sampling frequency f.sub.s, that is at Nf.sub.s. As shown in FIG. 5, the frequency response of the interpolating filter has zero crossings at each integer multiple of f.sub.s, but the signal at Nf.sub.s will not be attenuated.

Thus when the signal samples, sampled at f.sub.s, are applied to the interpolating filter, the filter as a consequence will eliminate all the signals between f.sub.s and Nf.sub.s. The output produced comprises an interpolated version of the input signal having a new sampling frequency of Nf.sub.s.

A simplified way of realising an interpolating filter will now be described with reference to FIGS. 6, 7 and 8. The value of N is determined by the highest required integer number used to increase the sampling frequency f.sub.s. When using the interpolating filter having an impulse response as shown in FIG. 6, the filter response length is -T.sub.s to T.sub.s which equals 2/f.sub.s. Furthermore at any given time there will be only two samples x.sub.1 and x.sub.2 in the interpolating filter which will appear at instances separated by T.sub.s =1/f.sub.s. Therefore in realising the interpolating filter as a transversal filter only two multipliers at a time are required together with an addition circuit to sum the multiplied signal samples. The resultant signal, y, appearing at the output of the filter will be given by:

where a and b are the coefficients of the convolution of the filter at the nth and (n+N)th taps. Since the impulse response of the filter as shown in FIG. 6 has a triangular shape, the coefficients of a and b are given by:

where N is the integer multiple used to increase the sampling frequency.

Substituting equations (2) and (3) into equation (1) leads to:

This means that if the sampling frequency f.sub.s is to be increased by a factor of N, then one obtains the difference between adjacent samples, x.sub.1 and x.sub.2, at the sampling frequency f.sub.s and divide the result by the interpolation factor, N. The resulting quotient is then taken as an increment and added to the sample x.sub.2 at every instant n to produce the interpolated samples of the input signal at the new sampling frequency Nf.sub.s.

FIG. 8 illustrates an embodiment of the incrementing filter realised to implement

The signal sampled at f.sub.s is applied to a shift-register or tapped delay line 48. Samples x.sub.1 and x.sub.2 separated by 1/f.sub.s seconds are tapped off and applied to a subtractor 50 which produces the difference or increment (x.sub.1 -x.sub.2) which is applied to a divider 52 in which the increment is divided by N. The quotient from the divider is added to the sample x.sub.2 in an accumulator 54 to produce the interpolated samples of the input signal at the new sampling frequency Nf.sub.s.

FIG. 9 is a block schematic diagram of an SSB modulator made in accordance with the present invention. The front end portion corresponds to that described with reference to and as shown in FIG. 3 and in the interests of brevity will not be described again. The second interpolators 38, 40 are based on the circuit as shown in FIG. 8 with some modifications. In the case of the second interpolator 40, the circuit stages which correspond to those used in the second interpolator 38 have been referenced using primed reference numerals, that is 48', 50', 52' and 54'. However the differences are divided by 4N in the dividers 52 and 52' and the accumulators 54, 54' are clocked at 4Nf.sub.s. The effect of doing this is that the increment is obtained by dividing the difference by 4N. The increment is then accumulated on the delayed signal sample x.sub.2 at regular clocking points. The accumulation starts every time a new sample is loaded into the shift register or tapped delay line 48, 48' and continues for 4N clock periods until a new sample is loaded into the shift register so that the process is repeated for a new value of x.sub.2.

The clock signal 4Nf.sub.s is derived from a master clock 56 operating at a higher frequency than 4Nf.sub.s and divided down in a divider 58. This divided down signal at 4Nf.sub.s is divided by 4N in another divider 60 to provide clock signals at f.sub.s, where f.sub.s has a value of the order of 100 KHz, to the interpolators 30, 32. The clock signal f.sub.s1 for the A to D converter 28 and the digital low pass filters 18, 20 is derived by dividing f.sub.s by m, where m is of the order of 8, in a divider 62.

The multiplexer 42 provides an SSB signal at a nominal carrier frequency Nf.sub.s sampled at 4Nf.sub.s. The multiplexer 42 comprises the electronic equivalent of four pole switch 64 operating at 4Nf.sub.s. Proceeding from top to bottom in FIG. 9, the first and second poles are respectively connected to addition stages 66, 66' of the second interpolators 38, 40 which stages provide digital values of the samples. The third and fourth poles provide inverted forms of the signals on the first and second poles, respectively. The output from the multiplexer 42 comprises a digitised form of the SSB signal at the nominal carrier frequency Nf.sub.s and the unwanted sampling frequency at 4Nf.sub.s. In order to eliminate the unwanted sampling frequency the multiplexer output is applied to the third interpolator 44 in which it is sampled at the clock frequency of the master clock 6, which frequency is above the bandwidth of a low pass filter 68 connected to the output of the D to A converter 46. By this operation the sampling frequency .sub.4 Nf.sub.s is eliminated by interpolation so that it is outside the bandwidth of the low pass filter 68.

The operation of the circuit shown in FIG. 9 will now be summarised. In order to produce the desired SSB signal, the required quadrature oscillator samples will be 1, 0, -1, 0, 1, 0 and 0, 1, 0, -1, 0,1 in the I and Q channels, respectively. In order to realise the RF section, these I and Q signal samples appearing at the outputs of the base band filters 18, 20 are interpolated to a sampling frequency 4Nf.sub.s in the interpolators 30, 38 and 32, 40. These samples are multiplied with the RF oscillator samples (see above) so that the alternate products of the multiplication in the I and Q channels become equal to zero. The multiplexer 42 selects samples alternately from the I and Q channels, which samples after D to A conversion and filtering form the SSB signal on the output 26.

In order for the SSB modulator to be able to operate at a range of carrier frequencies it is necessary to vary the sampling frequencies used. In order to do this then for a certain carrier frequency f.sub.c, the SSB signal sampling frequency 4Nf.sub.s is selected to be 4 times higher than f.sub.c. The sampling frequency f.sub.s for the interpolators 30, 32 is chosen by dividing 4Nf.sub.s by 4N in the stage 60. The frequency f.sub.s1 is produced by dividing f.sub.s by m in the stage 62. The master clock frequency is generated using a phase locked loop. The local oscillator frequency f.sub.1 is kept constant.

Two numerical examples of how the frequencies are calculated will now be given. It will be assumed that it is desired to cover SSB generation over the frequency range 0 to 10 MHz and in consequence the bandwidth of the low pass filter 68 is 10 MHz. In the first numerical example it will be assumed that the SSB signal is to be transmitted at a frequency

f.sub.s should be of the order 100 kHz and therefore

As 4Nf.sub.s =20 MHz is outside the bandwidth of the low pass filter 68 it will be attenuated to an acceptable level. In this situation there is no need to use the third interpolator 44.

In the second numerical example it will be assumed that the SSB is to be transmitted at a frequency

so that 4Nf.sub.s =4 MHz, f.sub.s is maintained at 100 kHz and therefore

N=1000/100=10 (and 4N=40). The values of m and f.sub.s1 are maintained at 8 and 12.5 kHz, respectively.

As 4Nf.sub.s =4 MHz which is within the 10 MHz bandwidth of the low pass filter 68, the interpolation factor and the sampling frequency of the third interpolator 44 are set to 3 and 12 MHz, respectively. Thus the divider 58 divides the 12 MHz by 3 to obtain the desired 4Nf.sub.s.

If a new carrier frequency is chosen then the calculations are repeated and the master clock frequency and the respective divisors are determined accordingly.

By operating the multiplexer 42 at 4Nf.sub.s odd numbered samples are selected from say the I channel and even numbered samples are selected from the other, Q channel. As a result the non-selected samples are not used. Consequently there is no need to calculate the even numbered samples in the I channel and the odd numbered samples in the Q channel. Thus the interpolation equation given in the description of FIG. 8 can be modified to form equations for y.sub.I and y.sub.Q where

As a result of this modification the second I and Q interpolators 38, 40 are operated at 2f.sub.s and the signals are multiplexed at 4Nf.sub.s.

An embodiment of the invention in which the modified equations are implemented is shown in FIG. 10. In the interests of brevity only the differences between the embodiments of FIGS. 9 and 10 will be discussed. The master clock 56 is connected to the divider 58 which produces an output signal at 2NF.sub.s. The multiplexer 42 is still clocked at 4Nf.sub.s. The signal at 2Nf.sub.s is supplied firstly to the divider 60 where it is divided down by 2N to provide the clock signal f.sub.s to the interpolators 30, 32 and secondly to increment a counter 70 two steps at a time. The counter 70 is reset at the instants when data is loaded into the shift registers 48, 48'. The output of the counter 70 is applied to a multiplier 54' and to an adder 74 in which it is added to +1 provided by a stage 72. The sum 2n+1 is supplied to the multiplier 54. In the multiplier 54 the number obtained from the divider is multiplied by 2 n+1 to produce the increments for the I channel. Similarly in the multiplier 54' the output of the divider 52' is multiplied by 2n to produce the increments for the Q channel.

The SSB modulators shown in FIGS. 9 and 10 are capable of being fabricated as integrated circuits. If desired a signal processor may be used to realise the base band mixers 14, 16 and the interpolators 30, 32, 38 and 40.