Running Character Display

This invention relates to a display device for use in a wide variety of electronic devices such as electronic calculators, and more particularly to a display device suitable for providing a visual display of a message including letters, symbols, numbers, etc., and having a length more than the capacity of a display panel.

In the past, when it was desired to display a message of a length more than the capacity of a display panel, the message should be split into more than one group in advance and displayed by groups. However, the prior art did not appreciate the difficulty in understanding such a fragmented message on the display panel.

It is therefore an object of the present invention to provide a new and effective display device for facilitating recognition of character messages even when these messages are longer than a display panel.

For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a front view of an electronic dictionary to which a display device according to the present invention is applied;

FIG. 2 is a schematic block diagram of a display device constructed according to one preferred form of the present invention;

FIG. 3 is a block diagram showing display control circuitry DSC in more detail;

FIGS. 4, 4A, 4B, 4C and 4D are schematic block diagrams of a typical central processor unit (CPU);

FIGS. 5A and 5B depict a typical display state with a display panel of a 5.times.7 dot matrix;

FIG. 6 shows a storage area in a display data store station DRM;

FIG. 7 shows the development of a display method according to the present invention;

FIG. 8 is a flow chart illustrating events occurring within the display method shown in FIG. 7;

FIG. 9 is a flow chart showing the steps n.sub.8 and n.sub.15 in FIG. 8;

FIG. 10 is a flow chart showing details of the steps n.sub.11 and n.sub.13 in FIG. 8; and

FIG. 11 is a flow chart showing details of the steps n.sub.2, n.sub.4 and n.sub.6 in FIG. 8.

Attention is first called to FIG. 1, there is illustrated a front view of an electronic dictionary with a display device DSP constructed according to the present invention which provides a visual display of words introduced via a keyboard K.

FIG. 2 is a schematic block diagram of the electronic dictionary shown in FIG. 1. The keyboard K, the display panel DSP, display control circuitry DSC and an external memory unit MU are all operatively connected to a central processor unit CPU. By supplying key strobe signals from key strobe output terminals W1-W8 electric representations of selected ones of keys on the keyboard K are derived from the keyboard K and fed into key input terminals K1-K4 of the CPU. The display panel DSP is typically a 12-digit dot matrix type liquid crystal display panel each digit having a given number of segment electrodes and a common opposite electrode. The display panel DSP receives opposite electrode select signals from output terminals H1-H7 of the central processor unit CPU and segment select signals from output terminals S1-S126 of the display control circuitry DSC for displaying purposes. As will be more clear hereinafter, signals developing at memory address output terminals BM1 and BL1 of the CPU are fed into memory digit address input terminals BL2 and BL3 of the display control circuitry DSC and the external memory unit MU and memory file address input terminals BM2 and BM3, respectively. Lines leading from these terminals BM1-BM3 and BL1-BL3 are shown as buses in FIG. 2 for the sake of simplicity only. A display/disable signal DIS from a display/disable signal output terminal DIS1 of the CPU is applied to a display/disable signal input terminal DIS2 of the display control circuitry DSC. The effect of the display/disable signal is to control the display operation of the display panel DSP. The central processor unit CPU, the display control circuitry DSC and the external memory unit MU are coupled together through data input and output terminals generally designated DIO for the sake of simplicity only. These circuit components are further coupled together through a read/write signal terminal generally designated RW. Signals at specific bit cells F1 and F2 of an output buffer register F within the central processor unit CPU are fed into a chip select signal input terminal CE1 of the display control circuitry DSC and the counterpart CE2 of the external memory unit MU so that either the display control circuitry DSC or the external memory unit MU may be made operative depending on the contents of the specific bit cells F1 and F2 of the output buffer register F (see FIG. 4). The external memory unit MU may comprise a well known random access memory. The display control circuitry DSC includes a display data storage DRM set up of a random access memory.

The display control circuitry DSC is best shown in FIG. 3, wherein the display data storage DRM is connected to an address decoder DC6 which decodes information sent from the memory digit address output terminal BL1 and the memory digit address output terminal BM1 of the central processor unit CPU to its input terminals BL2 and BM2 via an address buffer AB A read/write control circuit RWC allows information to be read from or written in the display data storage DRM via the data input and output terminals DIO in response to a read/write signal from the read/write terminal RW. The display data storage DRM has a display store segment of a up to 12 digit capacity which permits the display panel to display 12 digits of information at the same time. The contents of the display segment DM are supplied to a segment driver SED The respective digit positions of the display panel DSP are enabled with signals appearing at the output terminals S1-S126. The segment driver SED delivers so-called enable waveform signals to enable the display panel DSP when the display/disable control signal DIS assumes a logic "1" level, and so-called disable waveform signals to disable the the display panel DSP when the same assumes a logic "0" level.

FIG. 4, a composite diagram of FIGS. 4A-4D, shows a logic wiring diagram of a typical example of the CPU sheme in the dictionary whereby the display operation of the present invention is effected. It is understood that the illustrated CPU architecture is designed for general purposes and some of its functions are not concerned with the present invention.

A random access memory RAM is of a 4 bit input and output capacity and accessible to any specific digit position thereof as identified by a digit address and a file address. The RAM includes a digit address counter with its output terminal BL1, a digit address decoder DC.sub.1, a file address counter BM with its output terminal BM1, a file address decoder DC.sub.2 and an adder AD.sub.1 which serves as an adder and a subtractor respectively in the absence and presence of a control instruction 14. It further includes a second adder AD.sub.2 and a gate G.sub.1 for providing either a digit "1" or an operand I.sub.A to an input to the adder/subtractor AD.sub.1 and delivering 1 or I.sub.A when a control instruction 15 or 16 is developed, respectively. The memory digit address counter BL has a countdown circuit SB. An input gate G.sub.2 is provided for the memory digit address counter BL, which enables the output of the adder/subtractor AD.sub.1, the operand I.sub.A, the other operand I.sub.B and the output of the countdown circuit SB to pass therethrough respectively when control instruction 10, 11, 12 and 74 are developed. A gate G.sub.3 is disposed to provide a digit "1" or the operand I.sub.A to an input to the adder/subtractor AD.sub.2, the former being provided upon the development of an instruction 5 and the latter upon the development of an instruction 6. A circuit EO supplies to a gate G.sub.4 an exclusive OR sum of the both counts of the memory file address counter BM and the accumulator ACC. The gate G.sub.4 is an input gate to the memory file address BM which enables the output of the adder AD.sub.2, the operand I.sub.A, the contents of an accumulator ACC and the output of EO to pass upon the development of instructions 7, 8, 9 and 85. A file selection gate G.sub.5 is further provided for the memory RAM. A decoder DC.sub.3 translates the operand I.sub.A and supplies a gate G.sub.6 with a desired bit specifying signal. The gate G.sub.6 is an input gate to the memory RAM and contains a circuit arrangement for introducing a binary code "1" into a specific bit position of the memory RAM identified by the operand decoder DC.sub.3 and a binary code "0" into a specific bit position of the memory RAM identified by DC.sub.3, respectively, when a control instruction 2 or 3 is developed. Upon the development of an instruction 4 the contents of the accumulator ACC are read out. There are further provided display controlling flags N.sub.1 and N.sub.2. An input gate G.sub.46 to N.sub.1 and N.sub.2 is enabled with 69. A read/write circuit RWA with an output terminal RW directs read and write operations in response to 70 and 71, respectively.

A read only memory ROM has its associated program counter PL which specifies a desired step in the read only memory ROM. The read only memory ROM further contains a step access decoder DC.sub.4 and an output gate G.sub.7 which shuts off transmission of the output of the ROM to an instruction decoder DC.sub.5 when a judge flip flop F/F J is set. The instruction decoder DC.sub.5 is adapted to decode instruction codes derived from the ROM and divide them into an operation code area I.sub.O and operand areas I.sub.A and I.sub.B, the operation code being decoded into any one of the control instruction 1-75. The decoder DC.sub.5 is further adapted to output the operand I.sub.A or I.sub.B as it is when sensing an operation code accompanied by an operand. An adder AD.sub.3 increments the contents of the program counter PL by one. An input gate G.sub.8 associated with the program counter PL provides the operand I.sub.A and transmits the contents of a program stack register SP when the instructions 20 and 61 are developed, respectively. When the instructions 20, 61 and 60 are being processed, any output of the adder AD.sub.3 is not transmitted. Otherwise the AD.sub.3 output is transmitted to automatically load "1" into the contents of the program counter PL. A flag flip flop FC has an input gate G.sub.9 therefor which introduces binary codes "1" and "0" into the flag flip flop FC when the instructions 17 and 18 are developed, respectively. A key signal generating gate G.sub.10 provides the output of the memory digit address decoder DC.sub.1 without any change when the flag F/F FC is in the reset state (0), and renders all outputs I.sub.1 -I.sub.n "1" whatever output DC.sub.1 provides when FC is in the set state (1). There are further provided a clock generator CG, a divider DV, a displaying counter H and an opposite electrode select signal generator BP for the liquid crystal display panel with opposite electrode signal output terminals H.sub.1 -H.sub.7. The accumulator ACC is 4 bits long and a temporary register X is also 4 bits long. An input gate G.sub.11 for the temporary register X transmits the contents of the accumulator ACC and the stack register SX respectively upon the development of the instructions .circle.29 and .circle.59 .

An adder AD.sub.4 executes binary addition on the contents of the accumulator ACC and other data. The output C.sub.4 of the adder AD.sub.4 assumes "1" when the most significant bit or fourth bit binary addition yields a carry. A carry F/F C has its associated input gate G.sub.12 which sets "1" into the carry F/F C in the presence of "1" of the fourth bit carry C.sub.4 and "0" into the same in the absence of C.sub.4 (0). "1" and "0" are set into C upon the development of .circle.21 and .circle.22 , respectively. A carry (C) input gate G.sub.13 enables the adder AD.sub.4 to perform binary addition with a carry and thus transmits the output of the carry F/F C into the adder AD.sub.4 in response to the instruction .circle.25 . An input gate G.sub.14 is provided for the adder AD.sub.4 and transfers the output of the memory RAM and the RAM and the operand I.sub.A upon the development of .circle.23 and .circle.24 , respectively. An output buffer register F has a 4 bit capacity and an input gate which enables the contents of the accumulator ACC to enter into F upon the development of .circle.31 . An output decoder SD decodes the contents of the output buffer F into display segment signals SS.sub.1 -SS.sub.n. An output buffer register W has a shift circuit SHC which shifts the overall bit contents of the output buffer register W one bit to the right at a time in response to .circle.32 or .circle.33 . An input gate G.sub.16 for the output buffer register W leads "1" and "0" into the first bit position of W upon .circle.32 and .circle.33 , respectively. Immediately before "1" or "0" enters into the first bit position of W the output buffer shift circuit SHC becomes operative.

An output control flag F/F NP has an input gate G.sub.17 for receiving "1" and "0" upon the development of .circle.34 and .circle.35 , respectively.

The buffer register W is provided with an output control gate G.sub.18 for providing the respective bit outputs thereof at one time only when the flag F/F NP is in the set state (1). The outputs of the output buffer register W are available as key strobe signals. There are further provided a judge F/F J. inverters IV.sub.1 -IV.sub.4 and an input gate G.sub.19 to the judge F/F J for transferring the state of an input KN.sub.1 into J upon the development of .circle.36 . In the case where KN.sub.1 =0, J=1 because of intervention of the inverter IV.sub.1. An input gate G.sub.20 to the judge F/F J is adapted to transfer the state of an input KN.sub.2 into J upon .circle.37 . It is noted that, when KN.sub.2 =0, J=1 via the inverter IV.sub.2. An input gate G.sub.21 to the judge F/F J is adapted to transfer the state of the input KF.sub.1 into J upon .circle.38 . When KF.sub.1 =0, J=1 because of intervention of the inverter IV.sub.3. An input gate G.sub.22 to the judge F/F J is adapted to transfer the state of the input KF.sub.2 into J upon .circle.39 . When KF.sub.2 =0, J=1 because of the intervened inverter IV.sub.4. An input gate G.sub.23 is provided for the judge flip flop J for transmission of the state of an input AK into J upon the development of .circle.40 . When AK=1, J=1. An input gate G.sub.24 is provided for the judge flip flop J to transmit the state of an input TAB into J pursuant to .circle.41 . When TAB=1, J=1. A gate G.sub.28 is provided for setting the judge F/F J upon the development of .circle.46 . A comparator V.sub.1 compares the contents of the memory digit address counter BL with preselected data and provides an output "1" if there is agreement. The comparator V.sub.1 becomes operative when .circle.43 or .circle.44 is developed. The data to be compared are derived from a gate G.sub.26 which is an input gate to the comparator V.sub.1. The data n.sub.1 to be compared are a specific highter address value which is often available in controlling the RAM. A comparison input gate G.sub.26 provides n.sub.1 and n.sub.2 for comparison purposes upon the development of .circle.43 and .circle.44 , respectively.

An input gate G.sub.27 is provided for the decision F/F J to enter "1" into J when the carry F/F C assumes "1" upon the development of .circle.45 .

A decoder DC.sub.6 decodes the operand I.sub.A and helps decisions as to whether or not the contents of a desired bit position of the RAM are "1". A gate G.sub.28 transfers the contents of the RAM as specified by the operand decoder DC.sub.6 into the judge F/F when .circle.46 is derived. When the specified bit position of the RAM assumes "1", J=1. A comparator V.sub.2 decides whether or not the contents of the accumulator ACC are equal to the operand I.sub.A and provides an output "1" when the affirmative answer is provided. The comparator V.sub.2 becomes operative according to .circle.47 . A comparator V.sub.3 decides under .circle.48 whether the contents of the memory digit address counter BL are equal to the operand I.sub.A and provides an output "1" when the affirmative answer is obtained. A comparator V.sub.4 decides whether the contents of the accumulator ACC agree with the contents of the RAM and provides an output "1" in the presence of the agreement. A gate G.sub.29 transfers the fourth bit carry C.sub.4 occurring during addition into the judge F/F J. Upon the development of .circle.50 C.sub.4 is sent to F/F J. J=1 in the presence of C.sub.4. A flag flip flop FA has an input gate G.sub.31 which provides outputs "1" and "0" upon the development of .circle.52 and .circle.53 , respectively. An input gate G.sub.32 is provided for setting the judge F/F J when the flag flip flop FA assumes "1". A flag flip flop F.sub.B also has an input gate G.sub.33 which provides outputs "1" and "0" upon .circle.55 and .circle.56 , respectively. An input gate G.sub.34 for the judge flip flop J is adapted to transfer the contents of the flag flip flop F.sub.B into the F/F J upon the development of .circle.52 . An input gate G.sub.44 to the judge F/F J is enabled to transfer an input .alpha. in response to .circle.68 . To An input gate G.sub.35 associated with the judge F/F J is provided for transmission of the contents of the input .beta. upon .circle.19 . When .beta.=1, J=1. An output gate G.sub.45 from the accumulator ACC transfers the contents of the accumulator ACC to the data input output terminals DIO of the display data storage DRM in response to .circle.73 . An input gate G.sub.35 associated with the input of the accumulator ACC is provided for transferring the output of the adder AD.sub.4 upon .circle.26 and transferring the contents of the accumulator ACC after inverted via an inverter IV.sub.5 upon .circle.27 . The contents of the memory RAM are transferred upon .circle.28 , the operand I.sub.A upon .circle.13 , the 4 bit input contents k.sub.1 -k.sub.4 upon .circle.57 , the contents of the stack register SA upon .circle.59 and the data from the data storage DRM via DIO upon .circle.72 . A stack register SA provides the output outside the present system. A stack register SC also provides the output outside the system. An input gate G.sub.37 associated with the stack register SA transfers the contents of accumulator ACC upon .circle.58 . An input gate G.sub.38 associated with the stack register SX transfers the contents of the temporary register upon X .circle.58 . A program stack register SP has an input gate G.sub.39 for loading the contents of the program counter PL plus "1" through the adder into the program stack register, upon .circle.60 .

An illustrative example of the instruction codes contained within the ROM of the CPU structure, the name and function of the instruction codes and the control instructions developed pursuant to the instruction codes will now be tabulated in Table 1 wherein A: the instruction codes, B: the instruction name, C: the instruction description and D: the CPU control instructions.

SKIP: Only the program counter PL is incremented without executing a next program step instruction, thus skipping a program step.

AD: A binary addition is effected on the contents of the accumulator ACC and the contents of the RAM, the addition results being loaded back into the accumulator ACC.

ADC: A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry F/F C, the results being loaded back to the accumulator ACC.

ADCSK: A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry flip flop C, the results being loaded into the accumulator ACC. If the fourth bit carry C.sub.4 occurs in the results, then a next program step is skipped.

ADI: A binary addition is achieved upon the contents of the accumulator ACC and the operand I.sub.A and the results are loaded into the accumulator ACC. If the fourth bit carry C.sub.4 is developed in the addition results, then a next program step is skipped.

DC: The operand I.sub.A is fixed as "1010" (a decimal number "10") and a binary addition is effected on the contents of the accumulator ACC and the operand I.sub.A in the same way as in the ADI instruction. The decimal number 10 is added to the contents of the accumulator ACC, the results of the addition being loaded into ACC.

SC: The carry F/F C is set ("1" enters into C).

RC: The carry F/F C is reset ("0" enters into C).

SM: The contents of the operand I.sub.A are decoded to give access to a desired bit position of the memory specified by the operand ("1" enters).

RM: The contents of the operand I.sub.A are interpreted to reset a desired bit position of the memory specified by the operand ("0" enters).

COMA: The respective bits of the accumulator ACC are inverted and the resulting complement to "15" is introduced into ACC.

LDI: The operand I.sub.A enters into the accumulator ACC.

L: The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the file address counter BM.

LI: The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the memory file address counter BM. At this time the memory digit address counter BL is incremented. If the contents of BL agree with the preselected value n.sub.1, then a next program step is skipped.

LD: The contents of the memory RAM are exchanged with the contents of ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is decremented. In the event that the contents of BL agree with the preselected value n.sub.2, then a next program step is skipped.

X: The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is loaded into the memory file address counter BM.

XI: The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is incremented. In the event that BL is equal to the preselected value n.sub.1, a next program step is skipped.

XD: The contents of the memory RAM replaces the contents of the accumulator ACC, the operand I.sub.A being sent to the memory file address counter BM. The memory digit address counter BL at this time is incremented. If the contents of BL are equal to n.sub.2, then a next program step is skipped.

LBLI: The operand I.sub.A is loaded into the memory digit address counter BL.

LB: The operand I.sub.A is loaded into the memory file address counter BM and the operand B to the memory digit address counter BL.

ABLI: The operand I.sub.A is added to the contents of the memory digit address counter BL in a binary addition fashion, the results being loaded back to BL. If the contents of BL are equal to n.sub.1, then no next program step is carried out.

ABMI: The operand I.sub.A is added to the contents of the memory file address counter BM in a binary fashion, the results being into BM.

T: The operand I.sub.A is loaded into the program step counter PL.

SKC: If the carry flip flop C is "1", then no next program step is taken.

SKM: The contents of the operand I.sub.A are decoded and a next program step is skipped as long as a specific bit position of the memory specified by the operand I.sub.A assumes "1".

SKBI: The contents of the memory digit address counter BL are compared with the operand I.sub.A and a next succeeding program step is skipped when there is agreement.

SKAI: The contents of the accumulator ACC are compared with theoperand I.sub.A and if both are equal to each other a next program step is skipped.

SKAM: The contents of the accumulator ACC are compared with the contents of the RAM and if both are equal a next program step is skipped.

SKN.sub.1 : When the input KN.sub.1 is "0", a next program step is skipped.

SKN.sub.2 : When the input KN.sub.2 is "0", a next program step is skipped.

SKF.sub.1 : When the input KF.sub.1 is "0", a next program step is skipped.

SKF.sub.2 : When the input KF.sub.2 is "0", a next program step is skipped.

SKAK: When the input AK is "1", a next program step is skipped.

SKTAB: When the input TAB is "1", a next program step is skipped.

SKFA: When the flag F/F F/A assumes "1" a next program step is skipped.

SKFB: When the flag F/F F.sub.B assumes "1", a next program step is skipped.

SKFD: When the flag F/F F.sub.D assumes "1", a next program step is skipped.

SKFE: When the flag F/F F.sub.E assumes "1", a next program step is skipped.

WIS: The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position) receiving "1".

WIR: The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position being loaded with "0").

NPS: The output control F/F N.sub.p for the buffer register W is set ("1" enters).

NPR: The buffer register output control flip flop N.sub.p is reset ("0" enters therein).

ATF: The contents of the accumulator ACC are transferred into the output buffer register F.

LXA: The contents of the accumulator ACC are unloaded into the temporary register X.

XAX: The contents of the accumulator ACC are exchanged with the contents of the temporary register X.

SFA: The flage F/F FA is set (an input of "1").

RFA: The flag F/F FA is reset (an input of "0").

SFB: The flag flip flop F.sub.B is set (an input of "1").

RFB: The flag flip flop F.sub.B is reset (an input of "0").

SFC: An input testing flag F/F F.sub.C is set (an input of "1").

RFC: The input testing flag F/F F.sub.C is reset (an input of "0").

SFD: The input testing flag F/F F.sub.D is set (an input of "1").

RFD: The input testing flag F/F F.sub.D is reset (an input of "0").

SFE: The input testing flag F/F F.sub.E is set (an input of "1").

RFE: The input testing flag F/F F.sub.E is reset (an input of "0").

SKA: When an input .alpha. is "1", a next program step is skipped.

SKB: When an input .beta. is "1", a next program step is skipped.

KTA: The inputs k.sub.1 -k.sub.4 are introduced into the accumulator ACC.

STPO: The contents of the accumulator ACC are sent to the stack register SA and the contents of the temporary register X to the stack register SX.

EXPO: The contents of the accumulator ACC are exchanged with the stack register SA and the contents of the temporary register X with the stack register SX.

TML: The contents of the program counter P.sub.L incremented by one are transferred into the program stack register SP and the operand I.sub.A into the program counter P.sub.L.

RIT: The contents of the program stack register SP are transmitted into the program counter P.sub.L.

LN.sub.1 : The operands I.sub.A and I.sub.B enter the display and key input controlling flag F/Fs N.sub.1 and N.sub.2, respectively.

READ: Data externally applied to D.sub.I/O are introduced into the accumulator ACC.

STOR: The contents of the accumulator ACC are unloaded into D.sub.I/O.

EX: The contents of the memory RAM are exchanged with that of the accumulator ACC and an exclusive-OR'ed output of the operand I.sub.A and the contents of the memory file address counter B.sub.M is supplied to B.sub.M.

DECB: The memory digit address counter B.sub.L is decremented by "1". When the contents of B.sub.L are equal to the preset value n.sub.2, a next instruction is skipped.

Table 2 sets forth the relationship between the operation codes contained within the ROM of the CPU structure and the operand.

Taking an example wherein the output of the read only memory ROM is 10 bit long, the instruction decoder DC.sub.5 decides whether the instruction AD or COMA (see Table 1) assumes "0001011000" or "0001011111" and develops the control instructions .circle.23 , .circle.26 , or .circle.27 . SKBI is identified by the fact that the upper six bits assume "000110", the lower 4 bits "0010" being treated as the operand I.sub.A and the remaining ninth and tenth bits "11" as the operand I.sub.B. The operand forms part of instruction words and specifies data and addresses for next succeeding instructions and can be called an address area of an instruction. Major processing operations (a processing list) of the CPU structure will now be described in sufficient detail.

(I) A same numeral N is loaded into a specific region of the memory RAM (NNN.fwdarw.X)

(II) A predetermined number of different numerals are loaded into a specific region of the memory (N.sub.1, N.sub.2, N.sub.3, . . . .fwdarw.X)

(III)The contents of a specific region of the memory are transferred into a different region of the memory (X.fwdarw.Y)

(IV)The contents of a specific region of the memory are exchanged with that of a different region (X.fwdarw.Y)

(V) A given numeral N is added or subtracted in a binary fashion from the contents of a specific region of the memory (X.+-.N)

(VI) The contents of a specific region of the memory are added in a decimal fashion to the contents of a different region (X.+-.Y)

(VII)The contents of a specific region of the memory are one digit shifted (X right, X left)

(VIII) A one bit conditional F/F associated with a specific region of the memory is set or reset (F set, F reset)

(IX) The state of the one bit conditional F/F associated with a specific region of the memory is sensed and a next succeeding program address is changed according to the results of the state detection.

(X) It is decided whether the digit contents of a specific region of the memory reach a preselected numeral and a next succeeding program step is altered according to the results of such decision.

(XI) It is decided whether the plural digit contents of a specific region of the memory are equal to a preselected numeral and a program step is altered according to the results of the decision.

(XII) It is decided whether the digit contents of a specific region of the memory are smaller than a given value and a program step to be next executed is changed according to the decision.

(XIII) It is decided whether the contents of a specific region of the memory are greater than a given value and the results of such decision alter a program step to be next executed.

(XIV) The contents of a specific region of the memory are displayed.

(XV) What kind of a key switch is actuated is decided.

(XVI) The external memory is shifted digit by digit within the same memory file address.

The above processing events in (I)-(XVI) above are executed according to the instruction codes step by step in the following manner.

The foregoing is the description of the respective major processing events in the CPU architecture.

By reference to FIG. 5 an example of the display operation implementing the present invention will now be decribed in detail. For example, if the displaying of a character "I" is desired, each display panel digit being of a 7.times.5 dot matrix is divided into an upper half and a lower half and encoded information is defined as "11F1144744" in the descending order. This is accomplished by sending selected ones of the segment signals S1-S126 and selected ones of the opposite electrode signals H1-H7 to dot positions necessary for the displaying of the character "I". As indicated in FIG. 5(b), each digit 0, 1, 2, . . . 9, A, B, . . . F of the encoded information consists of their unique combination of 4 bits. The enabling waveform signals and disabling waveform signals are provided when the respective bits have "1" and "0", respectively.

The display data storage section DRM as shown in FIG. 6 is for temporarily storing those display encoded data. The respective segments (1)-(21) store independently the encoded information characteristic of characters to be displayed. In the illustrated example, the segment (1) stores the encoded information "11F1144744" associated with the character "I".

The display data storage section DRM has a 21 digit capacity.

Of those digits the 12 digit long data contained within the segments (1)-(12) in FIG. 6 may appear on the display panel DSP at a time. Additionally, 21 digit long data may be stored in the external memory unit MU in the same manner as in FIG. 6. It is therefore possible to display a total of 42 digits on the display panel DSP with accompanying shift operation through a combination of the display data storage section DRM and the external memory unit MU.

FIG. 7 is a typical display state of the display panel DSP. In order to display of a full message consisting of multi characters longer than the maximum possible display of 12 digits, "MAY I ASK YOU TO POST THIS LETTER ?", the maximum possible digits are first displayed at a time as depicted in FIG. 7(1) and held for a given length of time as depicted in FIGS. 7(1) to 7(2). Thereafter, the characters are shifted digit by digit as depicted in FIGS. 7(3)-7(7).

To repeat the displaying of this sentence, the state of FIG. 7(7) is held for a limited period of time as shown in FIG. 7(8). The final characters of the sentence are held in this manner so that it becomes easier to appreciate the end of the message. As indicated in FIG. 7(9) the overall message then disappears from the display panel for a time and the displaying of the sentence resumes.

FIG. 8 is a flow chart for achieving the display operation in FIG. 7. The steps n.sub.1 -n.sub.4 are executed to place the leading portion of the sentence to be displayed in alignment with the left extremity of the display in the shifting direction. The steps n.sub.7 and n.sub.8 or n.sub.10 or n.sub.8 are to perform display operation. The effect of the steps n.sub.9, n.sub.11, n.sub.12 and n.sub.13 is to place the end of the sentence in alignment with the right extremity of the display in FIG. 7 in the shifting direction. Likewise the steps n.sub.14 and n.sub.15 the steps n.sub.7 and n.sub.8 have the same effect of holding the display contents for the limited period of time.

During the step n.sub.1 the contents of the display data storage section DRM in the display control circuitry DSC and those of the external memory unit MU are shifted by one digit or 6 dots. The step n.sub.2 decides whether the segment (1) in the display data storage section DRM in FIG. 6 corresponding to the leading digit position is vacant. The steps n.sub.3 and n.sub.4 do the same job.

Each sentence has a total number of characters and spaces no greater than 40. Each space is no more than one character long. If the vacant space lasts for more than one character, the display operation proceeds with the steps n.sub.5 and n.sub.6. Provided that the step n.sub.6 senses a character after one vacant space, the step n.sub.7 would be in effect whereby a given value Na is fed into the register X. The step n.sub.8 holds this stage of operation for the length of time corresponding to the given value Na. In this manner, the display states as depicted in FIGS. 7(1) and 7(2) are ensured.

The effect of the steps n.sub.11 and n.sub.13 is to determine the contents of segment (13) of the display data storage section DRM corresponding to the second last digit position along the shifting direction. A chain of the steps n.sub.9, n.sub.11, n.sub.12 and n.sub.13 senses if the vacant space persists for at least two digit positions. If not, the step n.sub.10 is executed to supply the given value Nb to the register X. The present display state is held only for the limited period corresponding to the given value Nb and then shifted. This results in the display operation starting from FIG. 7(2) and ending at FIG. 7(7).

When the space lasts for two digit positions or more, the steps n.sub.14 and n.sub.15 hold the display state as shown in FIGS. 7(7) and (8) for the length of time as determined by the value Na. The display data then disappear from the panel for a while before execution of the steps n.sub.1 through n.sub.7. This is depicted in FIG. 7(9). The above mentioned procedure completes a cycle of the display operation according to the present invention.

FIG. 9 details the steps n.sub.8 and n.sub.15 of FIG. 8 wherein the display operation is triggered by supplying the display/disable signal DIS to the display control circuitry DSC during the step m.sub.1. At the next succeeding step m.sub.2 the register X already loaded with the given value is decremented. The steps m.sub.2 and m.sub.3 are carried out repeatedly until X=0 at the step m.sub.3. When X=0, the display/disable control signal DIS disables the display panel at the step m.sub.4. The steps m.sub.2 and m.sub.3 correspond to the processing events (V) and (X).

FIG. 10 details the steps n.sub.11 and n.sub.13 of FIG. 8 for deciding if the addresses BMBL: 8A and 9A of the display data storage section DRM are zero. It will be noted that BMBL: 8A means that the memory file address BM is "8" and the memory digit address BL is "A". BMBL:8A and BMBL:9A contain data corresponding to the intermediate longitudinal 8 dots of a chatacter to be displayed at the last digit position along the shifting position. All of the characters consisting of the 5.times.7 dot matrix except for special symbols may be displayed by actuating at least a dot in the intermediate longitudinal 7 dots. It can be regarded as vacant unless at least one of the intermediate longitudinal 7 dots of the 5.times.7 dot matrix are actuated.

FIG. 11 shows the steps nhd 2, n.sub.4 and n.sub.6 of FIG. 8 in more detail. Those steps are to decide if the contents of the display data storage section DRM at the addresses BLBM: 02 and 12 are zero. These addresses correspond to the foremost digit position in the shifting direction. Those steps are carried out in the same manner as shown in FIG. 10.

It is appreciated that the steps n.sub.1, n.sub.3, n.sub.5 and n.sub.12 of FIG. 8 are effected based upon the processing events (22) and (3) of type 4 and the steps n.sub.7, n.sub.10 and n.sub.14 based upon the processing event (2).

While the characters are shifted digit by digit in the above illustrated embodiment, they may be shifted dot by dot along the shifting direction as an alternative. In the case where a train of characters is displayed only once, the steps n.sub.14 and n.sub.15 of FIG. 8 may be eliminated.

Whereas the present invention has been described with respect to a specific embodiment, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.