Spread Spectrum Communication System Employing Composite Spreading Codes With Matched Filter Demodulator

The present invention relates in general to communication systems and is particularly directed to a modulation, demodulation mechanism employing composite (multiple length) spreading codes that allows for the use of practical sized matched filters (e.g. surface acoustic wave devices) in the demodulator to despread the signal and keep power consumption low.

High performance portable communication systems commonly employ some form of spreading sequence both as a security measure and to provide robustness against multipath fades. Although the despreading and data recovery mechanism in the receiver could be implemented using a high speed digital signal processing architecture, the required hardware would be impractical in terms of power required, size and weight. On the other hand, using strictly analog passive signal processing components, such as surface acoustic wave (SAW) devices, would require a complex matched filter design of prohibitive size, particularly where very long spreading sequences are used.

In accordance with the present invention, the excessive power requirements of purely digital processing systems and the impractical size (length) that would be required to implement a SAW transversal filter for an analog signal processor are significantly reduced by means of a hybrid despread and demodulation receiver for low symbol rate communications. At the transmitter a composite coding mechanism is used to spread the data signal. This composite, or compound, spreading mechanism is formed by multiplying different length coding sequences, thereby obtaining an overall signal processing operator the duration or symbol span of which is sufficient to maintain a high signal processing gain, but is considerably longer than can be processed using a practical sized passive (e.g. SAW) filter design. The design of the receiver takes advantage of the fact that the relatively short sequence can be despread using a practical SAW structure and is comprised of a hybrid signal processor, the front end of which contains a compact SAW matched filter and the downstream end of which is implemented using digital processing components. The matched filter removes the relatively short spreading sequence from the received signal and feeds its output to a mixer, which combines the output of the matched filter with the longer coding sequence to complete the despreading process. The despread signal is then differentially decoded and coupled to an integrate and dump circuit, which measures the energy in successive symbol intervals in order to determine the value of the respective data bits.

Preferably, the bit period of the data is a first integral multiple of the length of the short coding sequence, and the length of the relatively long coding sequence is a second integral multiple of the length of the short coding sequence, longer than the bit period. In addition, the first and second integers are relatively prime numbers.

FIG. 1 diagrammatically illustrates a composite encoding/spreading scheme in accordance with an embodiment of the present invention;

FIG. 2 shows the timing relationships among data and a pair of ("long" and "short") spreading sequences; and

FIG. 3 diagrammatically illustrates an embodiment of a demodulator for despreading and decoding a composite spreading code.

Before describing in detail the particular improved composite code spread spectrum communication system in accordance with the present invention, it should be observed that the present invention resides primarily in a novel structural combination of conventional communication circuits and components and not in the particular detailed configurations thereof. Accordingly, the structure, control and arrangement of these conventional circuits and components have been illustrated in the drawings by readily understandable block diagrams which show only those specific details that are pertinent to the present invention, so as not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the block diagram illustrations of the Figures do not necessarily represent the mechanical structural arrangement of the exemplary system, but are primarily intended to illustrate the major structural components of the system in a convenient functional grouping, whereby the present invention may be more readily understood.

Referring now to FIG. 1, an encoding/spreading scheme for the composite code transmitter terminal in accordance with an embodiment of the present invention is diagrammatically illustrated as comprising a data input signal line 11, over which digital data is coupled to a data encoder 13. For purposes of the present description the encoding mechanism will be assumed to be an M-ary PSK encoder, such as a differential BPSK encoder. It should be understood however, that the encoding mechanism is not limited to M-ary encoding but may be any of a variety of other types of encoding techniques customarily used in digital communication systems. In the present example, BPSK encoder 13 operates on the input data stream to produce a prescribed multi-bit pattern the bit rate of which is a multiple of (e.g. eight times) the rate of the binary data on input link 11. For a clock signal on link 15 at the representative eight times the bit rate of the data on input link 11, BPSK encoder 13 generates the output sequence 11111111 (or 00000000, depending upon the previous output) when the input data bit on link 11 is a binary "1 ", and the alternating one-zero sequence (01010101) when the input data bit on link 11 is a binary "0".

The multibit (X8) encoded data stream produced by encoder 13 is coupled to one input 19 of a mixer 21, to a second input 22 of which the output of a "long" spreading sequence generator 23 is applied. Like encoder 13, "long" spreading sequence generator 23 is driven by the (X8) clock on link 15, so that the pseudo random bits of its output code stream are of the same duration as the bits of the encoded differential BPSK bit stream. Mixer 21 multiplies the (BPSK) encoded data by pseudo random code of the "long" spreading sequence and supplies a first spread modulation output bit stream to a first input 31 of a downstream mixer 33, which multiplies the "long" code sequence by a "short", multichip sequence to produce a composite sequence that is applied to a downstream RF modulator (not shown) for transmission. By "long" spreading sequence is meant that the period or duration of the "long" code sequence is considerably longer (e.g. an order of magnitude or more) than the "short" spreading sequence produced by a "short" spreading sequence generator 35, the output of which is coupled to a second input 37 of mixer 33. In addition, the length of the "long" spreading sequence is equal to or longer than the period of a data bit.

More particularly, as illustrated in FIG. 2, which shows the timing relationships among the data and the two ("long" and "short") spreading sequences, in the course of the BPSK encoding process, each bit period Tb of the data is effectively subdivided into a plurality of M (eight in the present example) "short" intervals Ts. Using a 16 kbps data rate as an illustrative example, each short interval Ts has a duration on the order of 62.5/8=7.813 microseconds. The "short" spreading sequence produced by generator 35 is comprised of a sequence of N pseudo random spreading chips, e.g. 127 chips per interval Ts, which is multiplied by each of the bits of the first spread modulation output bit stream produced by mixer 21, so that during each bit interval Tb, mixer 21 produces NXM (8X127=1016) chips. In accordance with the present invention, the length of the "long" spreading sequence is fractionally longer than the bit period Tb, e.g. seven-eighths of a bit time longer than a data bit, so that the duration of the "long" sequence is fifteen times the duration of the "short" sequence. As a result, the "long" spreading sequence repeats at intervals that are incrementally offset, or delayed, by the length of a "short" sequence for successive bit periods Tb, so that the bits of the "long" sequence occur at different times for successive data bits. Consequently, the composite, or compound, sequence produced by mixer 33 has reduced spectral ripple and does not produce spectral lines that are exhibited by a repetitive short code alone. In addition, because the bit period Tb (eight "short" code intervals Ts) and the length (15Ts) of the relatively "long" coding sequence are relatively prime, bit starts will occur at all chips of the "long" code with equal frequency, so that the auto correlation function of the long code may be considered approximately implied on the autocorrelation function of the composite spread signal.

Referring now to FIG. 3, an embodiment of a demodulator for despreading and decoding the composite code produced by the output of mixer 33 in the transmitter terminal unit of FIG. 1 is diagrammatically illustrated as comprising an IF input line 41, over which a composite signal from an associated RF downconverter of the receiver terminal is coupled. As explained above, the design of the demodulator takes advantage of the fact that the relatively "short" sequence (one-eighth of a bit time) within the received composite code can be despread using a practical-sized passive device. In accordance with a preferred embodiment of the invention, despreading of the "short" sequence is accomplished by applying the composite spread signal on link 41 to a conventional surface acoustic wave matched filter 43, the electrode pattern of which effectively corresponds to the 127 chip sequence of the "short" code and thereby produces over an output line 45 a first despread signal comprised of the product of the "long" sequence and the BPSK-encoded data. The output of matched filter 43 is fed to a first input 47 of a mixer 51, which combines the first despread output signal with a replica of the "long" coding sequence produced by a "long" code generator 53, the output of which is coupled to a second input 55 of mixer 51. Long code generator is driven by a local pseudo noise clock signal on clock link 57 and is controlled by the receiver's control processor 61. Mixer 51 produces a second despread output signal on output line 59, corresponding to the BPSK encoded data absent both the "long" and the "short" sequences of the composite code, and couples the despread signal to a DPSK decoder 63, comprised of multiplier 65 and an associated delay line 67. Like matched filter 43, delay line 67 is preferably implemented as an SAW device, in order to simplify the hardware. Its delay period corresponds to the subdivision of the bit period used in the differential PSK encoding process at the transmitter which, in the present example, is one-eighth of a bit period (i.e. Tb/8). The output of multiplier 65 is a series of positive or negative pulses corresponding to the channel multipath response which repeats at a periodic rate equal to the long code chip rate (eight times the bit rate).

These decoded output pulses are coupled to an integrate and dump circuit 71, diagrammatically illustrated in FIG. 3 as a cascaded gate, or switch, 73 and an integrator 75, which gates and integrates the pulses over the eight long code chips of a bit so as to perform combining of the multipath energy. The output of integrator 75 is coupled to a hard-limiter 81, which makes a data bit decision by comparing the accumulated contents with a reference value (zero). Thus the data bit is determined to be a "0" if the energy is less than the reference, and a "1" if the accumulated energy is greater than the reference. After each bit decision, the contents of integrator 75 are cleared or dumped.

As pointed out previously, and as will be appreciated from the foregoing description, simplification of the hardware configuration of a spread spectrum demodulator is obtained in accordance with the present invention by the use of a composite spreading mechanism that permits part of the signal despreading process to be carried out by means of a practical sized, passive matched filter, thereby reducing processing complexity and power consumption. The digital hardware intensity of the demodulator may be further reduced by using analog components for other portions of the signal processor, such as mixer 51 which performs a despread multiply function, an SAW structure for delay line 67 employed in the DCPSK decoder and by using RC components for the integrate and dump circuit.

While we have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is suspectible to numerous changes and modifications as known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.