Laser Printer Controller Flexible Frame Buffer Architecture Which Allows Offsetting Different Input/Output Data Widths

The present invention is intended to be utilized with a printer controller for a laser printer engine which has, for example, 400 Dots Per Inch (DPI) with 20 pages per minute (ppm) speed. Because such an engine has higher speed and higher resolution, the printer controller requirements are more severe than 300 DPI and 8 ppm engines.

One of the key components to achieve higher speed and higher resolution is the control of a frame buffer used to buffer raster image information to be sent to the printer engine through a video interface.

In order to print through a laser printer, each pixel (picture element) must be defined as either black or white. A pixel is processed by the CPU (Central Processing Unit) of a controller and sent to the laser printer engine through video interface line(s). One major problem in this process of defining pixels of a page and sending the information to the printer engine is that the CPU is much slower in the processing time required to define the pixels than the printer engine needing them. One solution of this asynchronous process is to use a frame buffer for the synchronization.

There are two approaches in the prior art to construct a frame buffer. One approach is to create an entire page pixel definition by using a full bit map.

For example, if the printer engine is 300 DPI and handles only a letter size document, the buffer requires 2550.times.3300 pixels. The first number denotes the X dimension of the scanning (the number of pixels per scan line) and the second number denotes the number of scan lines (the Y dimension).

The other prior art approach is to receive an entire page description from a host computer and to create a display list. Under this approach, the frame buffer can be smaller than the full bit map depending upon the speed of creating the raster data from the display list. The frame buffer, which is smaller than full page bit map, is referred to as a band buffer.

The prior art approach of data width to and from the frame buffer is defined by the data width of the CPU. For example, if the CPU is one in the art known as a Motorola 68000, the data width is 16 bits. One problem of this approach is that when a band buffer is employed, the CPU may not have sufficient time to fill the buffer before the transfer of the data to the priner engine catches up. The critical factor for the use of the band buffer is the amount of time available for CPU to fill the buffer relative to the amount of time required to read out data from the band buffer. The CPU must have sufficient time to process input data and to quickly fill the band buffer.

It is an object of the present invention to provide an improved laser printer control system.

According to one aspect of the present invention, the output data width of the frame buffer can be wider than the data width of the CPU which allows less time for reading out from the frame buffer to the printer engine and more time for CPU processing. Typical data widths are 16 bits, 32 bits, 64 bits, and so on. Higher speed engines are likely to require wider data width to allow more time to be used by the CPU rather than data read-out to the printer engine.

Additional objects, advantages and novel features of the present invention will be set forth in part in the description which follows and in part become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations which are pointed out in the appended claims.

The accompanying drawings which are incorporated in and form a part of this specification illustrate an embodiment of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 depicts a block diagram of a control system for controlling a laser printer.

FIG. 2 depicts a block diagram of a laser printer controller system.

FIG. 3 depicts a variable frame buffer block diagram which forms a portion of FIG. 2.

FIG. 4 depicts a DMA (Direct Memory Access) control block diagram which forms a portion of FIG. 3.

FIG. 5 depicts a DMA timing and address generator circuit diagram which forms a portion of FIG. 4.

FIGS. 6A and 6B depict a frame buffer and surrounding circuit diagram which forms a portion of FIG. 4.

FIG. 7 depicts a DMA timing diagram.

FIG. 8 depicts a software flow chart for initialization of the X, Y and linear counters which form a portion of FIG. 3.

Reference will now be made in detail to the preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiment, it will be understood that it is not intended to limit the invention to that embodiment. On the contrary, it is intended to cover alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Referring now to FIG. 1, a block diagram of a control system 10 controlling a laser printer is depicted. In FIG. 1, a laser printer controller 12 is connected to a host CPU 16 via host communication bus 14. Laser printer controller 12 is also connected to a laser printer engine 20 via a main controller communication bus 18.

The printer engine 20 could be any suitable type printer engine. In a preferred embodiment, printer engine 20 is one manufactured by Ricoh Company, Ltd., known as Imagio, which has 400 dots per inch (DPI) with 20 pages per minute (PPM) speed. Other types of printer engines, however, could be utilized with a laser printer controller according to the present invention.

FIG. 2 shows an implementation of the laser printer controller according to the present invention. In FIG. 2, the laser printer controller 10 includes a CPU 22 (typically a TMS/34010 manufactured by Texas Instruments) for controlling the operation of the frame buffer.

The laser printer controller 12 of FIG. 2 also includes a host communication bus connection 24 to host CPU 16 of FIG. 1. Controller 12 includes a main controller communication bus connection 26 to the printer engine 20 of FIG. 1. Controller 12 includes a laser printer interface connection bus 18 to provide video data to printer engine 20 of FIG. 1. The laser printer interface bus 18 also includes the VCLOCK, LSYNC, LGATE and FGATE timing signals from printer engine 20 of FIG. 1.

The laser printer interface 40 of FIG. 2 is connected to the frame buffer 34 via bus 51 (MA0-9), bus 53 (MDI0-15), and bus 55 (M0-63).

The system 12 of FIG. 2 further includes a FONT ROM 46 and PROGRAM EPROM 48 and a bus extension circuit 28 to provide for future expansions such as additional memory and the like.

The system 12 of FIG. 2 also includes various data and address buses, such as data bus 23 (D0-15), address bus 43 (EPA0-15), and the like. Such buses are well known and need not be described in any great detail. The aspects of the present invention are shown in the dotted area defined by numeral 30. These aspects will now be described in conjunction with FIGS. 3-8.

FIG. 3 is the expansion of the defined area 30 in FIG. 2. The X counter 71 holds the number of dots per scan line. The Y counter 72 holds the number of scan lines. Both counters 71, 72 are 16-bit software programmable up counters. When the X counter 71 value reaches to the value set by the software, a one-shot pulse (CO) is sent to Y counter 72, incrementing its value. When the Y counter 72 value reaches to the value set by the software, the one-shot pulse is sent to linear counter 73, reloading the original starting address.

Those X, Y counters 71, 72 are implemented by using Intel 82C54. An example of software flow chart to program counters 71, 72, 73 is listed in FIG. 8.

Linear counter 73 translates X and Y counters 71, 72 to the linear counter of the frame buffer address during DMA operation. Linear counter 73 is described as Latch and Mux 129 and DMA Address Linear Counter 130 in FIG. 4.

In FIG. 3, the variable size interface circuit 74 interfaces wider frame buffer data width (in one implementation 64 bits) to 16 bits CPU data bus, which is described as buffer 122, and gate 123 in FIG. 4. The DMA control circuit 77 transfers the wider data (64 bits) to the variable shift register 76, where the shift register 76 serially shifts the data out to the laser printer engine 20 via bus 18. DMA circuit 77 is described as Dot Counter 121, latches 125-127, dynamic random access memory timing generator 128 and CAS generator 145 in FIG. 4. Register 76 is described as shift register with input latch 124 in FIG. 4.

FIG. 4 shows the DMA controller block of FIG. 3. The dot counter 121 controlled by the Laser Printer Video signals generates DMA request whenever shift register 124 shifts out all data. The variable size interface circuit 74 in FIG. 3 consists of two parts. One is 64 bit buffer 122 which provides the interface for the CPU data bus of 16 bits to a wider frame buffer memory of 64 bits. The other part is the gate 123, which sets all 64 bits to zero input when the DMA cycle starts.

When the memory clear is enabled, the lowering of the WR-signal causes all the 64 bits input data to be zero. Therefore, the memory location is cleared during the same DMA cycle. This memory clearing function can be disabled so that the WR- signal stays in the high level during the DMA cycle and the memory data will not be changed.

The CAS generator 145 of FIG. 4 generates four CASD0-3 signals which control four memory banks (as seen in FIG. 6) of 16 bits width. When the CPU reads or writes the frame buffer, only one CASD signal is selected, so that only 16 out of 64 bit bus are used. At the DMA cycle, all four CASD cycles are functional, resulting in an effective M0-63 bus. A more detailed mechanism is shown in FIG. 6.

In FIG. 4, Flip/Flops 125, 126 and 127 form a DMA synchronization circuit. They generate the DMAST- signal. The signal goes into the Dynamic Random Access Memory Timing Generator 128 to produce the RAS-, CASR- and WR-signals to control Dynamic RAM, and the RASEN-, CASEN- and INC signals to control DMA address linear counter 130. The DMA address linear counter 130 counts up by the INC signal and reloads by the RELOAD signal which comes from Y counter 72 in FIG. 3. The DMA address linear counter 130 provides the DRAM address during the DMA cycles. Timing generator 128 is described as data delay line 131, gate PAL 132, and buffers 133-136 in FIG. 5. Latch and mux 129 is described as Latch 140, Latch 141, and Mux 142 in FIG. 5. DMA address linear counter 130 is described as Counter 137, Counter 138 and Counter 139 in FIG. 5.

In FIG. 5, DMA Timing and Address Generator Circuit is the expansion of DMA timing generator 128, Latch and Mux 129, and DMA address linear counter 130 of FIG. 4. The DMAST- signal goes into the data delay line 131 and gets a different timing interval It then goes through a gating Program Array Logic (PAL) 132 to generate the necessary timing and control for the DMA control. The PAL 132 generates the RAS-, CASR-, WR- and LAL- signals which go through tri-state buffers 133-136 and provide the DRAM control signals during DMA.

The counters #0 through #2 (137, 138, 139) are three ripple counters. They count up with INC signal which comes from PAL 132. The counters 137, 138, 139 reload the programmed start values when Y counter 72 reaches to its maximum value. The counters 138, 139 contain higher memory address which comes out during RAS time. The counter 138 address goes through latch 141 to provide DRAM row address MA0-7 at RAS time. The counter 139 address is stored in latch 140. The latched address provides two DMA address bits (MA8-9) at both RAS and CAS time through Mux 142. The counter 137 is a low address counter. It provides the 8 bits DMA memory address at CAS time.

Gate 123 of FIG. 4 consists of 16 AND GATES 150-165. At normal CPU cycle, the HOLD- signal stays high. The CPU data (D0-15) passing through these gates become input data MDI0-15 to the frame buffer with the same logical state. At the DMA cycle, the HOLD- signal becomes low, which forces all MDI0-15 data to low level. When the clear memory function is enabled, the write operation follows the read operation. All the 64 bits input to the frame buffer of four memory banks 172-175 will be cleared through 16 bits of MDI0-15 input.

The frame buffer 75 of FIG. 3 is made up of four memory banks 172-175, as shown in FIG. 6. Input of each bank has 16 bits data path (MDI0-15) which is the same width as the CPU data bus (D0-15). The number of banks can be varied from 1, 2, 4, 8, and so on, to match the speed of laser printer engine 20.

Four banks were selected for one preferred implementation, resulting in 64-bit output data path (M0-63). Each memory bank 172-175 of FIG. 6 has the same RAS- WR- signal lines and 16-bit input data lines of MDI0-15, but has different output data lines (16 of M0-63) and CAS signal line (one of CASD0-3). The timing of the DMA operation is shown in FIG. 7.

Since the CAS signal is an important signal for read or write operation of memory bank, the CAS signal can be controlled in order to control the variable frame buffer operation.

The CAS generator 145 of FIG. 4 consists of an OR GATE 166, a decoder 167 and four AND GATEs 168-171, as shown in FIG. 6. Signal DRAM- comes from CPU address decoder circuit. CAS-, A0 and A1 are from CPU. These signals go into the CAS generator 145. Gate 166 and decoder 167 select one out of four CASD0-3 signals at the normal CPU operation cycle. When the DMA operation CASR- signal from timing generator 128 of FIG. 4 goes active (low), all four CASD0-3 become active at the same time, allowing operation on all the four memory banks 172-175 at the same time.

The buffer 122 of FIG. 4 consists of four OR GATEs 176-179 and buffers 180-183, which selects one set of the memory bank output data (M0-63) to the CPU data bus (D0-15) at the normal CPU operation cycle. During DMA cycle, the DDOUT signal which comes from CPU stays high and all of the buffers 180-183 are in the tri-state stage blocking the data to CPU bus.

The shift register with input latch 124 of FIG. 4 consists of four blocks of shift registers 184-187, as also seen in FIG. 6. Those shift registers 184-187 latch 64 bits memory bank data (M0-63) during the DMA cycle and serially shift out to the laser printer 20.

FIG. 7 shows the design timing chart for the DMA circuit, including the SYSCLK, HOLD-, HLDA-, DMAST-, RASEN-, RAS-, CASEN-, CAS-, and WR- timing signals.

FIG. 8 shows the software flow chart example to set the starting address, X counter and Y counter. Referring now to FIG. 8, a software flow chart for initialization of the X, Y and linear counters 72, 71 and 73 of FIG. 3 is shown. In FIG. 8, after start step 220, the flow chart starts with step 222 of loading the frame buffer start address to the register of CPU 22 of FIG. 2.

The next step 224 is to shift the register four bits for word address.

The next step 226 writes one byte of the register to the counter 137 of FIG. 5.

At step 230, the flow chart of FIG. 8 shifts the register 8 bits to get the higher address bits.

The next step 232 writes one word of the register to counters 138, 139 of FIG. 5.

The next step 234 in FIG. 8 loads the number of dots per line to the register of CPU 22 of FIG. 2.

The next step 236 in FIG. 8 writes two bytes of the register to the X counter 71 of FIG. 3.

The next step 240 loads the number of line per band to the register of CPU 22 of FIG. 2.

The next step 242 of FIG. 8 writes two bytes of the register to the Y counter 72 of FIG. 3 with a bandhigh value.

The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and many modifications and variations are possible in light of the above teaching The preferred embodiment was chosen and described in order to best explain the principles of the invention and its practical applications to thereby enable others skilled in the art to best utilize the invention and its various embodiments and with various modifications as are suited to the particular use contemplated It is intended that the scope of the invention be defined only by the claims appended hereto.