Switched Capacitor Network

The invention relates to a switched capacitor network, comprising an input terminal and an output terminal, a series arrangement of at least a first and a second successive switching transistor arranged between the input terminal and the output terminal, each switching transistor having a control electrode for receiving a switching signal, and a capacitance between the junction point of the first and the second switching transistor in the series arrangement and a point of constant potential, the control electrodes of the first and the second switching transistor being adapted to receive a first and a second switching signal, respectively, each of the two switching signals being in the form of a number of one or more successive pulses, which number is equal for both switching signals, the pulse(s) of the first switching signal not overlapping those of the second switching signal with respect to time and the frequencies of occurrence of the pulses in the two switching signals being substantially equal if said number of pulses is two or more.

A capacitor network of this type is known, for example, from Philips Technisch Tijdschrift 41, 1983, no. 4, pages 109-129. The Article in this Journal relates to the use of a switched capacitor network in a switched capacitor integrator. Another switched capacitor network is shown in EP 0 024 011.

The time constant of the switched capacitor integrator in the Philips Journal is too small for some applications and it would be desirable to obtain a larger time constant for such applications.

It is an object of the invention to provide a switched capacitor network which, when applied in a switched capacitor integrator, provides the possibility of realizing larger time constants. To this end, the switched capacitor network is characterized in that the two successive first and second switching transistors in the series arrangement have a zone in common and in that the capacitance is exclusively constituted by the parasitic capacitance of the common zone.

The time constant of the switched capacitor integrator is proportional to C.sub.f /C.sub.s in which C.sub.s is the afore-mentioned capacitance arranged between the junction point of the two switching transistors and the point of constant potential (ground) and C.sub.f is the value of the negative feedback capacitor arranged between the output and the inverting input of the operational amplifier arranged behind the capacitor network.

The maximum value of C.sub.f /C.sub.s depends on the minimum value of C.sub.s and on the maximum value which, within certain economic and technological limits, can be given to C.sub.f. Due to limitations at the level of the integration of C.sub.f in an integrated circuit, C.sub.f cannot be chosen to be too large. The minimum value of C.sub.s is limited by the parasitic capacitances of the switching transistors.

According to the invention this knowledge is utilized by effectively determining the capacitance C.sub.s by means of the parasitic capacitances of the two switching transistors. This means that no capacitor is required between the junction point of the two switching transistor and the point of constant potential.

However, provided that it is ensured that two successive switching transistors in the series arrangement have a (semiconductor) zone in common, the afore-mentioned capacitance, which is equal to the parasitic capacitance of this common zone, will have a sufficiently low capacitance to realize a desired, sufficiently large time constant in the switched capacitor integrator.

Dependent on the technology and the type of switching transistor a capacitance of approximately 5 to 25 fF (1fF=10.sup.-15 F) can be realized.

Moreover, the realization of a (semiconductor) zone which is common for two successive switching transistors results in an economy of space on the substrate, which leads to smaller circuits. The negative feedback capacitor may also be much smaller, which leads to a considerably larger economy of space on the substrate.

The switched capacitor network comprising a series arrangement of a first and a second switching transistor may be further characterized in that the network also comprises a second series arrangement of a third and a fourth switching transistor each having a control electrode for receiving a switching signal, in that the third and the fourth switching transistor have a zone in common and in that the second series arrangement is arranged in parallel with the series arrangement of the first and the second switching transistor.

This provides the possibility of compensating for the offset voltage which is present due to asymmetry in the switching transistors. Different specific layout configurations can now be proposed to reduce the offset voltage.

The invention will now be described in greater detail, by way of example, with reference to the accompanying drawing in which:

FIG. 1 shows a circuit diagram of a first embodiment,

FIG. 1a shows the two switching signals for the switching transistors in the first embodiment,

FIG. 2 shows the parasitic capacitances of a switching transistor,

FIG. 3 shows the structure of the network of FIG. 1 in a vertical cross-section through the substrate of the circuit,

FIG. 4 shows the network of FIG. 1 in a more diagrammatical form,

FIGS. 5 and 5b show two different layout configurations of a second embodiment,

FIGS. 6a and 6b show two different layout configurations of a third embodiment in FIGS. 6a and 6b,

FIG. 7 shows the electrical circuit diagram of the embodiments of FIGS. 5 and 6,

FIG. 8 shows a series arrangement of nine switching transistors and the layout configuration the circuit of, and

FIG. 9 shows a layout configuration of a series arrangement of eight switching transistors.

FIG. 1 shows an embodiment of a switched capacitor network 10 comprising a series arrangement of a first and a second switching transistor T.sub.1 and T.sub.2, respectively, between an input terminal 1 and an output terminal 2. FIG. 1 shows the use of the capacitor network in a switched capacitor integrator. To this end the output terminal 2 is coupled to the inverting input (-) of an operational amplifier 3. Its output 4 is coupled to the inverting input via a negative feedback capacitor C.sub.f. The non-inverting input (+) of the amplifier 3 is coupled to a point of constant potential (ground).

The two switching transistors T.sub.1 and T.sub.2 have a zone in common. For the (MOS) transistor T.sub.1 this is the zone on which normally the drain electrode is arranged and for the (MOS) transistor T.sub.2 this is the zone on which normally the source electrode is arranged. This will be explained in greater detail with reference to FIG. 3. The two switching transistors T.sub.1 and T.sub.2 each have a control electrode (the gate electrode) which is electrically coupled to terminals 6 and 7, respectively. A first and a second switching signal S.sub.1 and S.sub.2 can be applied to the terminals 6 and 7, respectively. See FIG. 1a which shows the two switching signals as a function of time. In the absence of a switching signal, i.e. the switching signal is low, the switching transistors are turned off. This means that they represent an open switch. Under the influence of the switching signal, or in other words, when the switching signal is "high", the switching transistors are turned on, that is to say, they constitute a switch in the closed position. It is evident that the switching transistors are N-MOS transistors in this case. If the switching transistors are P-MOS transistors, the switching signals should of course be applied in an inverted form to the terminals 6 and 7.

The capacitance between the junction point 5 of the two switching transistors T.sub.1 and T.sub.2 and the point of constant potential (ground) is determined and solely formed by the parasitic capacitances of the two switching transistors. Thus no separate capacitor is arranged between the point 5 and "ground".

FIG. 2 shows the parasitic capacitances of a MOS switching transistor T.sub.1, in which i in accordance with FIG. 1 may be equal to 1 or 2. A parasitic capacitance C.sub.1i is present between the source electrode s and the gate electrode g, a parasitic capacitance C.sub.2i is present between the gate electrode g and the drain electrode d, and parasitic capacitances C.sub.3i and C.sub.4i are present between the source electrode and the bulk terminal b and between the drain electrode and the bulk terminal b, respectively.

FIG. 3 is a cross-section of the switched capacitor network of FIG. 1 as arranged in an integrated form in the substrate. In this case an N-MOS design is used. FIG. 3 shows a p-doped substrate 15 in which n-doped zones 16, 17 and 18 are provided. Insulating oxide layers 19, 20, 21 and 22 are provided on the substrate. These layers in turn carry conducting layers in the form of conducting silicon layers 23, 24, 25 and 26.

The conducting layer 23 constitutes the source electrode of switching transistor T.sub.1 and is electrically coupled to the input terminal 1. The conducting layer 24 constitutes the gate electrode of switching transistor T.sub.1 and is coupled to the control signal input 6. The conducting layer 25 constitutes the gate electrode of switching transistor T.sub.2 which is coupled to the control signal input 7. The conducting layer 26 constitutes the drain electrode of the switching transistor T.sub.2 which is electrically coupled to the output terminal 2. The switching transistor T.sub.1 and the switching transistor T.sub.2 have the zone 17 in common. Consequently, this common zone is the n-zone 17. Thus there is no drain electrode of the switching transistor T.sub.1 and no source electrode of the switching transistor T.sub.2 physically present on the substrate. At the area of the zone 17 there is no external capacitor which could serve as a capacitance between the junction point of the two switching transistors and the point of constant potential (ground). Only the parasitic capacitance of the common zone 17 is present. This parasitic capacitance C.sub.s (see FIG. 1) is actually constituted by the sum of the parasitic capacitances C.sub.21 and C.sub.41 of switching transistor T.sub.1 and the parasitic capacitances C.sub.12 and C.sub.32 of the switching transistor T.sub.2, see FIG. 2.

The operation of the switched capacitor integrator of FIG. 1 will hereinafter be described in greater detail with reference to the switching signals of FIG. 1a.

FIG. 1a shows the first switching signal S.sub.1 which is applied to the control electrode 6 of the first switching transistor T.sub.1 and the second switching signal S.sub.2 which is applied to the control electrode 7 of the second transistor T.sub.2. Both switching signals are in the form of pulse series. The pulses have a frequency f.sub.n of occurrence for which it holds that f.sub.n =1/T in which T is the period in a pulse series.

The pulses of the second switching signal S.sub.2 are shifted with respect to time over T.sub.2 with respect to the pulses in the first switching signal S.sub.1. The pulses in the first and the second switching signal do not overlap one another with respect to time.

Under the influence of the pulse at the instant t=t.sub.0 in the switching signal S.sub.1, the switching transistor T.sub.1 is turned on for a short period from the instant t.sub.0. The parasitic capacitance C.sub.s is now charged to the voltage Vref which is present at the input 1 of the integrator. It is assumed that the capacitor C.sub.f is discharged in advance by a reset signal which is applied to a switch (not shown) arranged parallel to the capacitor C.sub.f, which switch closes for a short period for this purpose. Under the influence of signal S.sub.2 the switching transistor T.sub.2 will subsequently be turned on for a short period from the instant t.sub.0 +T/2. As a result, the capacitance C.sub.s is discharged and the capacitor C.sub.f is charged. A voltage which is equal to

is then produced at the output 4. Subsequently a pulse is applied to the switching transistor T.sub.1 at the instant t=t.sub.0 +T and a pulse is applied to the switching transistor T.sub.2 at the instant t=t.sub.0 +3T/2. A voltage which is equal to

is then produced at the output 4. After each subsequent combination of a pulse in the switching signal S.sub.1 and a pulse in the switching signal S.sub.2 the output voltage will have increased each time by .alpha..Vref.

The time constant .tau. of the integrator of FIG. 1 is given by

The parasitic capacitance C.sub.s, together with the pulse frequency f.sub.n, defines an effective resistance R. This effective resistance, together with C.sub.f, defines the time constant .tau. and is equal to R=1/C.sub.s,f.sub.n.

A large time constant is produced by choosing f.sub.n to be low and C.sub.f /C.sub.s to be large.

In practice the lower limit for f.sub.n is determined by the bandwidth of the input signal and the sampling theorem and by the technological limitations resulting in leakage currents.

The maximum value of C.sub.f /C.sub.s depends on the minimum value of C.sub.s and the value which can be given to C.sub.f within certain economic and technological limits. In practice C.sub.f will be chosen to be not larger than 50-100 pF. The minimum value of C.sub.s is limited by the parasitic capacitances of the two switching transistors. By having the capacitance C.sub.s determined solely by the parasitic capacitances of the switching transistors, a very low capacitance can be realized. Dependent on the technology and the type of switching transistor the switched capacitance C.sub.s will have a value of approximately 5-25 fF. With C.sub.f of 50 pF and C.sub.s of 5 fF, a time constant of 0.1 s. can be realized at a clock frequency f.sub.n of 100 kHz.

Practical tests on the circuit of FIG. 1 have proved that it is realizable and usable. It has also been found that the offset voltage, which results from the asymmetry in the switching transistor, plays an important role. Particularly the gate-source and gate-drain overlap capacitances C.sub.11 and C.sub.22 are concerned.

For this reason specific layout configurations are proposed for the relevant input circuit 10 with the switched parasitic capacitance C.sub.s to reduce the offset voltage.

The indication of a switched capacitor network such as the network 10 in FIG. 1 will hereinafter be given in the form as shown in FIG. 4.

FIG. 5 shows the switched capacitor network 10 in FIG. 5a with which a second switched capacitor network 10' comprising a series arrangement of a third and a fourth switching transistor T.sub.3 and T.sub.4 is arranged in parallel. The control electrodes of the switching transistors T.sub.1 and T.sub.3 are coupled together. Similarly, the control electrodes of the switching transistors T.sub.2 and T.sub.4 are coupled together. This compensates for the geometrical asymmetry of the switching transistors, which is the result of limitations in the manufacturing process, so that a reduced offset voltage is obtained.

FIG. 5b shows an alternative layout; the switching transistors are slightly further apart and are aligned. It is true that the compensation will usually be reduced thereby, but the circuit has the advantage that the various connection leads do not cross one another so that parasitic coupling capacitances are not produced.

FIGS. 6a and 6b show two alternatives, in which the associated circuit diagram is now slightly modified: the two parallel capacitor networks are now switched out of phase (see FIG. 7). This has the additional advantage that clock asymmetry is also compensated for. In addition it provides the possibility of realizing the layout of FIG. 6a in which the gate structures of the compensating switches are uninterrupted. This may further reduce the sensitivity to geometrical errors (notably mask errors).

FIG. 7 shows the electrical circuit diagram of the two parallel-arranged capacitor networks 10 and 10'. The switching transistors T.sub.1 to T.sub.4 are shown as switches. C.sub.s ' is the parasitic capacitance of the zone which is common to the switching transistors T.sub.3 and T.sub.4.

In the networks according to FIGS. 5a and 5b the switches T.sub.1 and T.sub.3 are first closed simultaneously. This means that the two parasitic capacitances C.sub.s and C.sub.s ' are charged to the voltage Vref.sub.1 which is present at the input terminal 1. After the switches T.sub.1 and T.sub.3 have been opened, the switches T.sub.2 and T.sub.4 close simultaneously and the two capacitances are discharged via the output terminal 2.

In the networks according to FIGS. 6a and 6b the switches T.sub.1 and T.sub.4 are closed simultaneously. This means that the capacitance C.sub.s is charged to the voltage Vref and the capacitance C.sub.s ' is discharged via the output terminal 2. Subsequently, the switches T.sub.1 and T.sub.4 are opened and then the switches T.sub.2 and T.sub.3 close simultaneously. This means that the capacitance C.sub.s is discharged via the output terminal 2, whilst the capacitance C.sub.s ' is charged to the voltage Vref.

A further reduction of the (effectively) switched capacitance may be obtained by arranging a larger number of switches in series, as in FIG. 8a. The network comprises nine series-arranged switching transistors T.sub.1 to T.sub.9 in which each time two successive switching transistors T.sub.i and T.sub.i+1 have a zone in common. The common zone then has a parasitic capacitance C.sub.si.

A compensation is also possible for such a network, see FIG. 8b. The nine switching transistors are to this end arranged along a U-shaped line on the substrate.

FIG. 9 shows an embodiment in which eight series-arranged switching transistors T.sub.1 to T.sub.8 are arranged along a U-shaped line on the substrate.

It is to be noted that the invention is not limited to the embodiments shown. The invention may also be used for those embodiments which differ from the embodiments shown in aspects not relating to the invention. For example, the networks are not limited to their use in a switched capacitor network, but they can generally be used where (parasitic) capacitances are switched.