Clock Recovery Circuit for Digital Demodulator

This invention relates to a clock recovery circuit for a digital demodulator of the type comprising means for multiplying an input signal with first and second orthogonal demodulation reference signals to generate respective product signals, means for integrating the product signals to generate first and second integrated values indicative of digital data encoded in the input signal, and means for digitizing the integrated values to generate first and second digital values

Digital demodulators of the general type described above are well known to those skilled in the art, as for example in Quadrature Amplitude Modulation (QAM) systems. Typically, a plurality of separate component signals are combined to form a composite signal which is transmitted on a single signal channel, and each signal is orthogonal to the others and is amplitude modulated. When the received composite signal is multiplied by an appropriate local oscillator signal and the resulting product is integrated over an integral number of symbol periods, the resulting integration is indicative of the amplitude of a respective one of the component signals of the composite signal.

"Offset Quadrature Communications with Decision-Feedback Carrier Synchronization" (Marvin K. Simon and Joel G. Smith, IEEE Transations on Communications Volume Com-22 No. 10, Oct. 1974, Pages 1576-1584) discloses a related offset quadrature phase shift keyed system which utilizes a voltage controlled oscillator to generate the local oscillator signals. The frequency and phase of this oscillator are controlled in a feedback loop. The oscillator generates demodulation reference signals which are multiplied with the incoming signal in multipliers. The resulting products are integrated and then quantized to produce two digitized values. As shown in FIG. 3 of the Simon ,e/uns/et al./ article, the feedback loop for the voltage controlled oscillator includes two feedback signals which are summed to create a control signal e(t). Each of these feedback signals is generated as the product of the digitized value of one channel with the delayed product value of the other channel.

This approach places considerable demands on the multipliers. Since the analog input channel of each multiplier receives the product value from a respective channel, each multiplier must remain linear over a considerable range of product values. Such multipliers, though possible to create, can be undesirably expensive in many applications.

It is a primary object of the present invention to provide an improved clock recovery system which reduces the range of analog inputs to such multipliers in clock recovery feedback loops, and thereby reduces the complexity and the cost of the hardware required to implement the system.

According to this invention, a digital demodulator of the type described initially above is provided with means for generating an error signal indicative of the difference between a first integrated value and a first digitized value. Means are also provided for combining the error signal with a second digital value to generate a feedback signal, and means are provided for utilizing the feedback signal to generate a control signal indicative of a phase difference between the input signal and the demodulation reference signals.

A primary advantage of this invention flows from the fact that the combining means combines the error signal with the second integrated value. The error signal itself is indicative of the difference between the integrated and digitized values, and will typically be much smaller in range than the first integrated value itself. For this reason, when the combining means is implemented with a multiplier, the multiplier only must operate with a relatively narrow range of analog input values. In this way the cost and complexity of the multiplier are reduced.

FIG. 1 is a block diagram of a receiver which incorporates a presently preferred embodiment of this invention.

FIG. 2 is a block diagram of a transmitter suitable for use with the receiver of FIG. 1.

FIGS. 3A and 3B are waveform diagrams of the local oscillator signals LOa and LOb of FIG. 1.

FIGS. 4a(consisting of FIGS. 4A-4E)-4b are schematic diagrams of preferred forms of selected components of FIG. 1.

FIG. 1 shows a receiver 10 that incorporates a presently preferred embodiment of this invention. This receiver 10 is responsive to a composite input signal on line 12. It acts to demodulate the signal to generate digital output signals a and b on lines 30, 32. The nature of the preferred input signal on line 12 will be described below in conjunction with FIG. 2. The receiver 10 includes two multipliers 14, 16. Each multiplies the input signal on line 12 with a respective demodulation reference signal or local oscillator signal LOa, LOb. The two local oscillator signals LOa, LOb are generated by a divider chain 18, and are mutually orthogonal. For example, the two local oscillator signals LOa, LOb can be sine and cosine functions at the same frequency FIGS. 3a and 3b show the preferred signals for LOa and LOb of this embodiment. The divider chain 18 itself does not form part of this invention. A preferred arrangement for the divider chain 18 is disclosed in copending U.S. Pat. application Ser. No. 07/427,281 filed concurrently, entitled "Local Oscillator Signal Generating System for Digital Demodulator", the disclosure of which is hereby incorporated by reference.

Each of the multipliers 14, 16 generates a respective product signal which is integrated for a time equal to a symbol period (800 nanoseconds in this embodiment) in an integrator 22, 24. The resulting integrated values a, b are applied to digitizers 26, 28 to generate digitized values a and b.

Because the local oscillator signals LOa, LOb are mutually orthogonal and selected to provide product signals that integrate to a non-zero value over a symbol period, the integrated values a, b generated by the integrators 22, 24 should be at one of the four digital amplitudes +3, +1, -1, -3 encoded in the input signal 12. To the extent that the integrated values a, b deviate from these expected values, such deviations are indicative of either amplitude or phase errors. The system disclosed in FIG. 1 operates to eliminate phase errors.

In order to reduce phase errors to zero between the local oscillator signals LOa, LOb and the input signal, the embodiment of FIG. 1 includes summers 34, 36. Each generates a respective error signal as a function of the difference between one of the integrated values a, b and the respective digitized value a, b. Thus, the error signal generated by the summer 34 is equal to a-a, and the error signal generated by the summer 36 is equal to b-b.

In multipliers 38, 40 the error signals a-a, b-b are multiplied by the digitized values b, a, respectively, to generate feedback signals which are summed with opposite signs in a summer 42. The resulting control signal is equal to ab-ba and is applied as an input to a low pass filter 44. The filtered control signal is then used to control a voltage controlled oscillator 46. As explained in the above-identified specification, the divider chain 18 is responsive to the voltage controlled oscillator 46, and by varying the phase of the voltage controlled oscillator 46 the system of FIG. 1 ensures that the local oscillators LOa, LOb are synchronized with the input signal 12.

In order better to define the environment of this invention, FIG. 2 shows a block diagram of a transmitter 50 that can be used to generate the input signal on line 12. This transmitter 50 includes four data signals D1-D4, and each of these data signals can be in any of four digital states (+3, +1, -1, -3). The four data signals D1-D4 are modulated with orthogonal modulating signals sin (1.5x), cos (1.5x), sin (3.5x), cos (3.5x) in respective multipliers 52, 54, 56, 58. In FIG. 2, x is equal to 2.pi. t/t.sub.s, where T.sub.s is equal to 800 nanoseconds. The modulated data signals D1, D2 are summed in a summer 60, and the resulting signal is multiplied by an envelope signal sin (x/.sub.2) in a multiplier 64. Similarly, the modulated data signals D3, D4 are summed in a summer 62 and multiplied by the envelope signal sin (x/2) in a multiplier 62. The resulting signals are combined in a summer 68 and then applied to a twisted pair line 12 via a line interface 70.

In each case, the data signals Dl-D4 retain their value throughout any given transmitted symbol period T.sub.s. Because each of the four components encodes one of four levels, the resulting composite signal on line 12 can be characterized as a 16 quadrature amplitude modulated (16 QAM) signal. The modulating signals at 1.5x and 3.5x are suppressed carriers, and the envelope at x/2 creates two side bands for each suppressed carrier. Thus, the composite signal is characterized by a frequency spectrum emphasizing the frequencies 1x, 2x, 3x and 4x. Further details of the transmitter 50 shown in FIG. 2 can be found in the above-identified specification.

It will be noted that the transmitter 50 generates a composite signal on line 12 having four orthogonal channels, while the receiver 10 of FIG. 1 processes only two orthogonal channels. Typically, the receiver 10 will include another circuit (not shown) similar to that shown for the remaining two orthogonal signals.

FIGS. 4a-4b provide detailed schematic diagrams of the presently preferred embodiments of the multiplier 14, integrator 22, digitizer 26, and additional components 34, 36, 42-46 of FIG. 1. As pointed out above, the divider chain 18 is fully disclosed in the above-identified specification which is hereby incorporated by reference for its teaching of the structure and operation of the divider chain 18.

In FIGS. 4a-4b, the block labeled 34, 38 receives an input OSIGN, which is the sign bit of b and therefore a one bit approximation of b. This circuit generates PHSERR, which corresponds to (a-a)b, in FIG. 1. Elements 16, 24, 28, 36, 40 correspond in structure to the elements 14, 22, 26, 34, 38 of FIGS. 4a-4b. The input signal PHSERRLO to the loop filter 44 is a current mode signal which is a wired sum from the two outputs PHSERR from the multipliers 38, 40.

An important advantage of the embodiment of FIG. 1 is that the multipliers 38, 40 are not required to operate with a wide range of analog inputs. The analog input to the multiplier 38 is equal to a-a, which is typically much small than either a or a. Similarly, the multiplier 40 is provided with an analog input equal to b-b which is much smaller than either b or b when the circuit is close to equilibrium. Because the analog input range for the multipliers 38, 40 is much reduced as compared to the prior art systems described above, the multipliers 38, 40 can be simplified in structure. This reduces the cost of the multipliers 38, 40, and therefore the cost of the overall receiver 10.

Of course, the detailed schematic diagrams referenced above have been provided only to illustrate the best mode of this invention, and those skilled in the art will recognize that the functions defined in FIG. 1 can be implemented with a wide variety of hardware.