Diffused Bit Line Trench Capacitor Dram Cell

This invention relates in general to trench-capacitor memory cells, and more particularly to a minimum-dimension memory cell with a trench capacitor and a diffused bit line.

Trench-capacitor dynamic random access memory (DRAM) cells have recently been developed in a continuing effort to fit the maximum charge storage capacity into the smallest space. Most conventional DRAM cells of this type comprise a capacitor trench having a storage oxide grown on its sidewalls. A grounded capacitor electrode fills this trench, and an (n+) doped region surrounds the trench in the semiconductor layer and extends to form a source region for the corresponding field effect pass gate transistor. A (p) pass gate channel region connects this source region to an (n+) diffused drain region of the pass gate transistor.

An undesirably large space is required to be laid out between the side of the trench capacitor opposite the pass gate transistor and the next cell. This is because a parasitic transistor will otherwise form between the (n+) implantation surrounding the capacitor trench and the (n+) drain region of the next pass gate transistor. Prior art attempts to minimize these parasitic transistors include providing local oxide isolating structures that still take up an undesirably large amount of cell area.

More recently, Lu et al. have proposed a trench-capacitor memory cell that stores the charge on the trench electrode rather than in a surrounding diffused region (N. C. Lu, "A Substrate-Plate Trench-Capacitor (SPT) Memory Cell for Dynamic RAM's", IEEE Journal of Solid State Circuits, Vol. SC-21, No. 5, pages 627-633 (October, 1986)). In this cell, a conductive plate connects an upper surface of the capacitor electrode to an adjacent source region of the pass gate transistor, spanning the capacitor storage oxide on the surface of the epitaxial layer. A metallic bit line is coupled to a drain region of the pass gate transistor.

This proposed cell has the disadvantage of requiring at least two layers of metal or other conductor thus complicating the cell's fabrication. A need therefore exists for a minimum-dimension trench-capacitor DRAM cell that requires only one level of metal interconnect while at the same time avoiding the large spacing requirements of conventional cells between the trench capacitor and the pass gate transistor of the next adjacent cell.

One aspect of the invention comprises a memory cell formed in a semiconductor layer of a first conductivity type. A trench is formed into a face of the semiconductor layer and sidewalls of the trench have a storage insulator formed thereon to define a trench hole. A conductive capacitor electrode is formed in the trench hole. A portion of the storage insulator is removed from a selected side of the sidewalls to create a gap that extends downwardly from the upper surface of the capacitor electrode by a predetermined depth. A conductive plug is formed in this gap to electrically connect the electrode to an adjacent region of the semiconductor layer. This adjacent region is doped to be of a second conductivity type and forms a diffused region of a respective pass gate transistor.

In another aspect of the invention, an array of trench-capacitor memory cells is formed in the semiconductor layer. A plurality of spaced-apart elongate bit lines of the second conductivity type are formed in the layer, and a plurality of spaced-apart elongate parallel conductive word lines are formed so as to be insulatively disposed over the face of the semiconductor layer, and at an angle to the bit lines. A plurality of memory cells are formed in between the bit lines and each has a trench capacitor and a pass gate transistor. A diffused region of the transistor is formed to be of the second conductivity type, and to be electrically coupled to an electrode of the capacitor. A transistor channel region of the first conductivity type is disposed on the face between the diffused region and one of the bit lines. A thin pass gate insulator is formed on the face over the channel region, and one of the word lines is formed over the pass gate insulator for actuation of the transistor.

Yet another aspect of the invention comprises a method for fabricating a memory cell in a semiconductor layer. First, a trench is formed into the layer, followed by the formation of a sidewall insulator on the sidewalls of the trench. A highly doped polycrystalline or amorphous material comprising silicon is deposited in the trench to form a capacitor electrode. A selected portion of the sidewall insulator is removed to create a gap between the electrode and the semiconductor layer, the gap extending from the outer face of the electrode inwardly along the sidewall for a predetermined depth. A substantially undoped polycrystalline or amorphous semiconductor material comprising silicon is deposited in the gap, and this material is doped to form a conductive plug. The plug electrically couples the electrode to an adjacent region of the semiconductor layer. Preferably, this region of the semiconductor layer is doped by diffusing dopant from the capacitor electrode through the plug into the adjacent semiconductor layer to form a diffused region of the respective pass gate transistor.

A principal advantage of the present invention is its avoidance of a large spacing requirement between the capacitor electrode and the pass gate transistor of an adjacent cell. This is because the charge is stored in the capacitor electrode rather than around the trench periphery, and no (n+) region is formed in the semiconductor layer around the trench. Therefore, no parasitic transistor is formed between this region and a drain region of the next pass gate transistor. Thus, the spacing between the capacitor electrode and the next pass gate transistor or bit line can be reduced to that required for misalignment tolerance.

Another advantage of the invention inheres in its avoidance of an extra layer of conductive interconnects. This advantage results from the use of a storage oxide gap plug to electrically couple the capacitor electrode to an adjacent source region of the pass gate transistor, together with the use of diffused bit lines rather than their metal or polysilicon counterparts. With 1.0 micron design rules, the cell size of the invention can be scaled to approximately 2.6.times.4.1 microns, suitable for 4 megabit DRAMs. Using 0.6 micron design rules, the cell is suitable for 16 megabit DRAMs.

Other aspects of the invention can be discerned from the following detailed description taken in conjunction with the drawings, in which:

FIGS. 1a-1f are greatly enlarged schematic sectional views of a semiconductor substrate and epitaxial layer, showing successive stages in the fabrication of a DRAM cell according to the invention;

FIG. 2 is a schematic plan view showing one layout of an array of DRAM cells according to the invention; and

FIGS. 3a-3c are greatly enlarged schematic sectional views of a semiconductor substrate showing successive stages in the fabrication of an alternative DRAM cell according to the invention.

FIG. 1 is a greatly enlarged sectional view showing the beginning stages of fabrication of a DRAM cell according to the invention. In this embodiment, a (p-) epitaxial layer 10 is formed on a (p-) semiconductor substrate 12. The concentration of dopant in the epitaxial layer 10 can be on the order of 10.sup.. ions/cm.sup.3, and that of the substrate 12 can be 10.sup.19 ions/cm.sup.3. The portion of substrate 12 and epitaxial layer 10 shown is in an active device region of the wafer that is surrounded by field oxide.

To illustrate the process according to the invention, a DRAM array area is shown generally at 14 and a peripheral area is indicated generally at 16. Active device areas 14 and 16 are isolated by field oxide isolating structures 18. Field oxide structures 18 are selectively grown from epitaxial layer 10 according to conventional methods.

An oxide/nitride/oxide hard mask is formed over an outer surface 20 of epitaxial layer 10. This trilayer mask includes a first, thin oxide layer 22 that is grown from epitaxial layer 10 until layer 22 is about 350 Angstroms in thickness. This is followed by a nitride layer 24 that is about 1500 Angstroms thick. The deposition of nitride layer 24 is followed by a second, thick oxide layer (not shown) whose thickness falls in the range of 5000 to 10,000 Angstroms. The oxide/nitride/oxide hard mask is patterned with a layer (not shown) of photoresist in order to define a trench area indicated generally at 26. The hard mask is then plasma-etched in a single step with CHF.sub.3 /C.sub.2 F.sub.6 chemistry.

The photoresist layer (not shown) is next stripped and a trench 28 is anisotropically etched with an etchant such as chlorine until it extends through epitaxial layer 10 into semiconductor substrate 12. It is preferred that trench 28 be about 6 to 10 microns deep. The deepest portion of trench 28 is not shown in FIGS. 1a-1f.

After trench 28 has been etched, a hydrogen fluoride solution is used to remove any trench residues on the sidewalls 30 of trench 28. The HF solution will somewhat undercut first oxide layer 22, and will remove the top oxide layer (not shown) of the oxide/nitride/oxide hard mask.

In the next step, a storage oxide layer 32 is grown on the sidewalls 30 (and on the bottom, not shown) of trench 28. Storage oxide layer 32 can be on the order of 100 to 150 Angstroms thick. A layer of heavily doped (p+) polycrystalline or amorphous silicon is then deposited as by low-pressure chemical vapor deposition (LPCVD) on the wafer to fill trench 28. This preferably polysilicon layer can have a dopant concentration of 10.sup.20 ions/cm.sup.3. The polysilicon layer is etched back as with an SF.sub.6 plasma or a wet etch to define a plurality of trench capacitor electrodes 34 inside respective trenches 28 (one each shown). Because of the etch non-uniformity, an upper surface 36 of capacitor electrode 34 may be somewhat recessed from the outer surface 20 of epitaxial layer 10. After the etchback of the polysilicon, nitride layer 24 is removed.

Turning now to FIG. 1b, a layer 38 of photoresist is deposited on oxide layer 22 and electrode surface 36 and patterned to define a bit line implantation area indicated generally at 40. An (n+) implant is performed with arsenic and phosphorus through the thin oxide layer 22. The arsenic can be implanted at a dose of about 3.times.10.sup.15 ions/cm.sup.2 and at an implantation energy of about 150 KeV. The phosphorus can be implanted at a dose of about 4.times.10.sup.14 ions/cm.sup.2 and an implantation energy of about 100 KeV. These implantations will form an (n+) diffused bit line 42. The photoresist layer 38 is then stripped.

Referring next to FIG. 1c, a layer 44 of oxide is deposited over oxide layer 22 and upper surface 36 of capacitor electrode 34 by chemical vapor deposition (CVD) until it is about 2000 to 4000 Angstroms thick. A layer 46 of photoresist is then deposited and patterned to define a transistor pass gate area indicated generally at 48. This photoresist pattern also defines a peripheral circuit area 50. Pass gate area 48 extends from a point over diffused bit line 42 over to expose a portion of upper surface 36 of capacitor electrode 34. The remaining portion of upper surface 36 remains masked so that oxide 44 is exposed over only one side of capacitor electrode 34.

The exposed areas 48 and 50 of oxide layers 44 and 22 are then etched away. This can either be performed with a CHF.sub.3 plasma etch or an HF wet etch. Oxide layers 44 and 22 are intentionally overetched such that a selected portion of storage oxide 32 is removed to form a gap 52 in between capacitor electrode 34 and sidewall 30. The amount of overetch will determine the depth of gap 52 as measured from upper surface 36 of capacitor electrode 34, which is preferred to be in the range of 3000 to 5000 Angstroms. An additional lithography (not shown) may be needed to protect the peripheral isolation oxide layer 18 from being etched. Gap 52 will only be about 150 Angstroms thick, as this was the thickness of storage oxide 32.

The overetch of oxide layers 44 and 22 inside areas 48 and 50 is followed by an LPCVD deposition of a layer 54 of undoped polycrystalline or amorphous silicon. Layer 54 has a thickness in the range of 500 to 2000 Angstroms. Because of the excellent step coverage of polysilicon, layer 54 will fill gap 52.

Turning now to FIG. 1e, poly layer 54 is etched isotropically, leaving only a polysilicon filament 58 within gap 52. An anisotropic etch may be used instead.

The final process steps are illustrated in FIG. 1f. The removal of polysilicon layer 54 (FIG. 1d) exposed several areas of epitaxial surface 20, particularly in peripheral circuit area 16 and between trench 28 and diffused bit line 42. The wafer is next subjected to a thermal cycle under an oxygen atmosphere to grow a thin (200 to 300 Angstroms) gate oxide layer 64. As this happens, dopant is diffused from heavily doped capacitor electrode 34, through the polysilicon material filling gap 52 and into epitaxial layer 10 to form an (n+) diffused region 66. Polysilicon filament 58 will be doped through the diffusion of dopant from dopant source 34. Filament 58 will be oxidized at a rate of about four times that of the gate oxide 64.

The oxidation of poly filament 58 defines a conductive polysilicon plug 68 that fills gap 52. As previously described, the undoped poly constituting plug 68 will be doped to be (n+) by diffusion of dopant from heavily doped capacitor electrode 34, and dopant will continue to diffuse through plug 68 to create an (n+) diffused region 66 that will act as the source of the pass gate transistor. A region 70 of (p) epitaxial layer 10 in between diffused regions 42 and 66 will act as a transistor channel. As can be seen, the degree of undercutting performed by the intentional overetch of layer 44 in FIG. 1d will determine the depth of diffused region 66.

After the poly oxidation and dopant diffusion step, a doped layer of polysilicon is deposited by LPCVD, patterned and etched to define a plurality of word line conductors 72 (one shown) and other poly conductors 74 (one shown). Succeeding metal interconnect and passivation steps (not shown) complete the DRAM array and peripheral circuitry.

Since capacitor electrode 34 is electrically coupled through plug 68 to source region 66, no surface conductor strap is required. The use of a diffused bit line 42 instead of a bit line conductor, together with the just-mentioned method of connecting the capacitor electrode 34 to the source region 66, eliminates the requirement for an entire conductor level, thus simplifying the fabrication of the device.

A plan view of the layout of the cell fabricated as illustrated in FIGS. 1a-1f is shown in FIG. 2, with like numbers identifying like structure as appropriate. As shown, the trench 28 for any particular cell can be placed to be extremely close to the next bit line 42. Using one micron design rules, only 0.2 micron need separate trench sidewall 30 from bit line 42 as a misalignment tolerance. Where 0.6 micron design rules are used, as for the fabrication of a 16 megabit DRAM, the separation between trench 28 and bit line 42 can be even less. The resultant savings in cell area allows a reduction in array size.

An alternative embodiment is illustrated in FIGS. 3a-3c, where numbers used in FIGS. 1a-1f identify like parts as appropriate. In this embodiment, a relatively thick layer 80 of oxide is deposited on an upper surface 82 of a semiconductor substrate 12. An epitaxial layer is not required in this embodiment, and is advantageously omitted due to its relative expense. Oxide layer 80 is on the order of 2000 to 4000 Angstroms thick. After the forming of oxide layer 80, a nitride layer 24 and a second mask oxide layer 84 are deposited as before to form an oxide/nitride/oxide hard mask.

The trilayer hard mask is patterned and etch to define a trench area 26 as before. A trench 28 is then anisotropically etched, but only to an initial depth of about one to two microns.

Referring next to FIG. 3b, an oxide layer 86 is formed either through a thermal cycle or by chemical vapor deposition (CVD). This oxide layer is then anisotropically etched back to form sidewall oxide layer 86 as shown. Top oxide layer 84 disappears in this etch step if the etch were anisotropic; otherwise, a thinner top oxide layer 88 remains.

Next, trench 28 is extended by an anisotropic etch until its total depth is in the range of six to ten microns. The sidewalls 30 of trench 28 are then doped along their exposed lower portions 89 with boron, either by oblique implantation or in a furnace with an appropriate boron source to produce a (p+) region 90 surrounding the lower portion of trench 28. Region 90 is formed in order to enhance the depletion capacitance of the storage capacitor, thereby increasing the resultant capacitance of the cell. The dopant concentration inside (p+) region 90 should preferably be on the order of 10.sup.19 to 10.sup.20 ions/cm.sup.3.

Turning now to FIG. 3c, sidewall oxide 86 is removed along with other trench sidewall residues through the use of a wet etch. A storage oxide layer 32 is then grown in its place along the entire length of sidewalls 30. A doped polysilicon material is then deposited through LPCVD as before and etched back to form capacitor electrode 34, and nitride layer 24 (FIG. 3b) is stripped. A layer 38 of photoresist is then deposited and patterned to define a bit line implantation area 40. Arsenic and phosphorus is implanted as before to create a diffused bit line 42. Subsequent fabrication steps are the same as those described in FIGS. 1b-1f. This alternative embodiment will yield a DRAM cell capacitor having enhanced capacitance without requiring an expensive epitaxial layer.

In summary, a DRAM cell structure using a diffused bit line and a storage oxide gap plug to connect the capacitor electrode to a source region of the pass gate transistor has been described. Since a first level of metal interconnect is avoided, and since the capacitor electrode is used to store charge, the trench capacitor may be positioned very close to the next bit line, thereby saving space.

While preferred embodiments of the invention and their advantages have been illustrated by the above detailed description, the invention is not limited thereto but only by the scope and spirit of the appended claims.