Color Masking Circuit and Color Video Printer Using the Same

The present invention relates to a color video printer for printing a color television picture and a color masking circuit for use in a color video printer or the like, and particularly relates to a color masking circuit which performs high-speed color masking processing to eliminate color impurities included in the color material and the like so as to obtain a printed picture with high color reproducibility.

A color video printer for fixing and recording a color television picture as a hard copy has become widely used in various fields as an alternative to photography or some other printing technique. There are various color video printers available which utilize different recording systems such as thermal transfer, ink-jets, light-spot scanning, etc. In any recording system, however, color reproduction is achieved by mixing the three colors of yellow (Y), magenta (M) and cyan (C) using a subtractive color process.

In thermal transfer printing of a sheet of printed matter, it is easy to obtain a superimposed color picture by switching color ink ribbons of the colors (Y), (M) and (C). Recently, therefore, a full-color video printer in which density gradation is given to respective picture elements (recording dots) has been developed and is expected to be used as an external output apparatus (a hard-copy device) to be connected to a video receiver, a picture processing device, a personal computer and so on. In controlling the density gradation, a constant voltage is applied to each of the heating resistors of a thermal head and current conduction time to the resistors is controlled to thereby cause the heating energy of the resistors to be different so as to give gradation to the transfer quantity of a color material (ink) to recording dots, that is, to give density gradation to picture elements.

In the conventional color video printer, however, the color reproducibility of printed pictures has not been superior. This is mainly because the colors (Y, M and C) of general color materials are not pure but include impurities. Therefore, if those primary colors are superimposed on a printed paper, the mixed color thereon shifts from the color of the original picture.

It is therefore an object of the present invention to solve the foregoing problems in the prior art.

It is another object of the present invention to provide a color masking circuit in which a high-speed color masking processing is performed so as to eliminate color impurities included in color materials and the like to thereby improve the color reproducibility.

The foregoing objects of the present invention are attained by a color masking circuit which performs color masking processing upon density data to indicate the density of color picture elements.

The color masking circuit comprises a matrix coefficient holding means for holding predetermined matrix coefficients for execution of a matrix operation, a matrix coefficient selecting means for selecting predetermined matrix coefficients from the matrix coefficient holding means according to desired output density data, multiplication circuits for multiplying the density data for respective colors by the selected matrix coefficients, and an addition circuit for adding the data obtained as resultant products from the multiplication circuits to each other to thereby produce the desired output density data.

In a color video printer according to the present invention, the picture element data forming a television picture is converted into density data, and the density data is subject to color masking processing by the above-mentioned color masking circuit to thereby obtain corrected density data. The thus obtained corrected density data is then converted into density gradation data for instructing density gradation of each picture element, and driving of the picture printing in accordance with the gradation data is performed to thereby form a printed picture corresponding to the television picture.

FIG. 1 is a block diagram illustrating the arrangement of a first embodiment of the color masking circuit according to the present invention;

FIG. 2 is a block diagram illustrating a specific example of the arrangement of the matrix coefficient holding circuit 112 and the matrix coefficient selecting circuit 114 in FIG. 1;

FIG. 3 is a block diagram illustrating a specific example of the arrangement of the multiplication circuit 106 for calculating a.sub.il D.sub.B in FIG. 1;

FIG. 4 is a block diagram illustrating a functional arrangement for explaining the operation of the multiplication circuit 106;

FIG. 5 is a block diagram illustrating the arrangement of a second embodiment of the color masking circuit according to the present invention;

FIG. 6 is a block diagram illustrating the main arrangement of a color video printer with a thermal transfer system which employs the color masking circuit according to the present invention; and

FIG. 7 is a diagram illustrating a current conduction time vs. density characteristic curve to be used in the density gradation system of the present invention.

Picture element data forming a color television picture is composed of picture elements P.sub.B, P.sub.G and P.sub.R for the respective colors of blue (B), green (G) and red (R). The density data D.sub.B, D.sub.G and D.sub.R corresponding to those picture elements P.sub.B, P.sub.G and P.sub.R are given by the following equations: ##EQU1##

In the case of ideal color materials having pure colors (Y, M and C), the following relationships are established: ##EQU2##

In the conventional video printer, adhering quantities of the respective color materials onto the surface of a print paper has been controlled on the basis of the density data D.sub.Y, D.sub.M and D.sub.C obtained by the above equations 1 and 2. However, since the actual colors of color materials include impure components, the color reproducibility becomes low in the printed picture if the printing is performed on the basis of the data D.sub.Y, D.sub.M and D.sub.C for the colors (Y), (M) and (C) obtained by the equations 2.

Therefore, according to the present invention, by way of example, the following linear color masking processing is performed upon the density data D.sub.B, D.sub.G and D.sub.R obtained by the equations 1: ##EQU3## Each matrix coefficient (correction coefficient) a.sub.ij is set to a value so that the impure component of each color is cancelled, theoretically or statistically, according to the characteristics of an ink sheet to be used, a print paper to be used, and so on. In the first embodiment of FIG. 1, each matrix coefficient is held by a matrix holding means.

For example, the datum D.sub.Y of the equation 4-1 is operated upon such that the matrix coefficients a.sub.11, a.sub.12 and a.sub.13 are selected from the matrix coefficient holding means by a coefficient selecting means, and the data D.sub.B, D.sub.G and D.sub.R are multiplied by the respective selected coefficients a.sub.11, a.sub.12 and a.sub.13 by a multiplication circuit. The resulting data values are added to each other by an addition circuit to thereby obtain the datum D.sub.Y in accordance with the equation 4-1. The data D.sub.M and D.sub.C of equations 4-2 and 4-3 are calculated through similar operations.

The embodiments of the present invention now will be described with reference to the accompanying drawings.

FIG. 1 shows the arrangement of the first embodiment of the color masking circuit according to the present invention.

In FIG. 1, six bits of density data D.sub.B (blue), D.sub.G (green) and D.sub.R (red) to be subjected to color masking processing are latched by latch circuits 100, 102 and 104, respectively, and respectively applied to multiplication circuits 106, 108 and 110 through the respective output terminals of the latch circuits 100, 102 and 104. However, the predetermined 3.times.3 matrix coefficients a.sub.11, a.sub.1 2, . . . a.sub.33 described above are loaded into a matrix coefficient holding circuit 112 which is constituted by registers. Each coefficient a.sub.ij in matrix coefficient holding circuit 112 is formed by seven bits including one sign bit.

In order to calculate the datum D.sub.Y of the equation 4-1, the matrix coefficients a.sub.11, a.sub.12 and a.sub.13 are selected by a matrix coefficient selecting circuit 114 and applied to the multiplication circuits 106, 108 and 110, respectively. The data D.sub.B, D.sub.G and D.sub.R are then multiplied by coefficients a.sub.11, a.sub.12 and a.sub.13 by the multiplication circuits 106, 108 and 110, respectively. The data of product a.sub.12 D.sub.G obtained by the multiplication circuit 108 and data of product a.sub.13 D.sub.R obtained by the multiplication circuit 110 then are added to each other by an addition circuit 116, and the resultant data of sum a.sub.12 D.sub.G +a.sub.13 D.sub.R and the data of product a.sub.11 D.sub.B obtained by the multiplication circuit 106 are added to each other by an addition circuit 118 so that the 8-bit data of D.sub.Y =a.sub.11 D.sub.B +a.sub.12 D.sub.G +a.sub.13 D.sub.R is produced.

Next, in order to obtain the datum D.sub.M of the equation 4-2, the matrix coefficients a.sub.21, a.sub.22 and a.sub.23 are selected by the matrix coefficient selecting circuit 114 and applied respectively to the multiplication circuits 106, 108 and 110 through which the data of product a.sub.12 D.sub.G, a.sub.13 D.sub.R and a.sub.11 D.sub.B were obtained as just described. Those data of product a.sub.22 D.sub.G, a.sub.23 D.sub.R and a.sub.21 D.sub.B are added to each other by the addition circuits 116 and 118 so that the 8-bit data D.sub.M =a.sub.21 D.sub.B +a.sub.22 D.sub.G +a.sub.23 D.sub.R is produced.

Next, in order to obtain the datum D.sub.C of the equation 4-3, the matrix coefficients a.sub.31, a.sub.32 and a.sub.33 are selected by the matrix coefficient selecting circuit 114 and subjected to an operation similar to that described above through the multiplication circuits 106, 108 and 110 and the addition circuits 116 and 118 so that the 8-bit data D.sub.C =a.sub.31 D.sub.B +a.sub.32 D.sub.G and a.sub.33 D.sub.R is produced.

As described above, when a set of density data D.sub.R, D.sub.G and D.sub.B of the RGB system is given, the 3.times.3 matrix operation according to the equations 4 is executed for those density data at a high speed using hardware so that the density data D.sub.Y, D.sub.M and D.sub.C of the YMC system are produced sequentially.

FIG. 2 shows a specific example of an arrangement of the matrix coefficient holding circuit 112 and the matrix coefficient selecting circuit 114. The matrix coefficient holding circuit 112 is arranged in the form of a 63 (7.times.9) bit serial-input-and-parallel-output shift register so that the preset matrix coefficients a.sub.ij successively given in the order of a.sub.33, a.sub.23, . . . a.sub.21 and a.sub.11 in serial bits are inputted (loaded) into predetermined positions of the shift register at the timing of a shift pulse SP outputted from the shift register in parallel bits.

The matrix coefficient selecting circuit 114 is constituted by tri-state buffers BF.sub.ij for respectively receiving the matrix coefficients a.sub.ij outputted in parallel from the matrix holding circuit 112, and a selector circuit SEL consisting of a decoder. Two-bit selection signals se.sub.0 and se.sub.1 for selecting the matrix coefficients are supplied to the selector circuit SEL. When the datum D.sub.Y is to be obtained as mentioned above, for example, the signals se.sub.0 and se.sub.1 (of "L", "L") are supplied to make only the output line L.sub.Y of the output lines L.sub.Y, L.sub.M and L.sub.C of the selector circuit SEL become "H", thereby turning on the tri-state buffers BF.sub.11, BF.sub.12 and BF.sub.13 with their control terminals connected to the output line L.sub.Y so that the corresponding matrix coefficients a.sub.11, a.sub.12 and a.sub.13 are transferred to the respective output sides of the buffers BF.sub.11, BF.sub.12 and BF.sub.13, and these coefficients are supplied to the multiplication circuits 106, 108 and 110, respectively. In the same manner, when the datum D.sub.M is to be obtained, the signals se.sub.0 and se.sub.1 take predetermined logic values to make only the output line L.sub.M of the selector circuit SEL become "H" so that the tri-state buffers BF.sub.21, BF.sub.22 and BF.sub.23 supply corresponding matrix coefficients a.sub.21, a.sub.22 and a.sub.23 to the multiplication circuits 106, 108 and 110, respectively. Further, when datum D.sub.C is to be obtained, only the output line L.sub.C of the selector circuit SEL is made "H" so that the tri-state buffers BF.sub.31, BF.sub.32 and BF.sub.33 supply the corresponding matrix coefficients a.sub.31, a.sub.32 and a.sub.33 to the multiplication circuits 106, 108 and 110, respectively.

FIG. 3 shows a specific example of the multiplication circuit 106 for calculating the product a.sub.il D.sub.B, and FIG. 4 shows the functional arrangement for explaining the operation of the multiplication circuit 106.

The 6-bit density data D.sub.B (d0, d1, d2, d3, d4 and d5) is loaded into a 6-bit parallel-input-and-parallel-output shift register 120 through the latch circuit 100 (FIG. 1). After being loaded with the density data D.sub.B, the shift register 120 makes each of its bits shift by one to the upper side (the overflow bit is cancelled). The contents (6 bits) in the respective stages of the shift register next are latched by latch circuits LT.sub.0 .about.LT.sub.5, respectively, and then applied to the respective input terminals of multiplexers MP.sub.0 .about.MP.sub.5. Six other bits of data with all the bits thereof made to be "0" (zero-level) are applied to other input terminals of the multiplexers MP.sub.n. The upper six bits A.sub.il, B.sub.il, . . . F.sub.il of the selected matrix coefficients a.sub.il (i=1,2,3) also are applied to the respective selector terminals SLT of the multiplexers MP.sub.n. Each multiplexer MP.sub.n passes the one input (the data applied from the corresponding latch circuit LT.sub.n) to the output terminal upon receiving a "1" bit at the selector terminal SLT, and passes the other input data ("0", "0", . . . "0") to the output terminal upon receiving a "0" bit at the selector terminal SLT.

The data respectively outputted from the multiplexers MP.sub.0 and MP.sub.1 next are added to each other by a half adder (H.A) 122 to thereby obtain 7-bit sum data. In the same manner, the data respectively outputted from the multiplexers MP.sub.2 and MP.sub.3 are added to each other by a half adder (H.A) 124, and the data respectively outputted from the multiplexers MP.sub.4 and MP.sub.5 are added to each other by a half adder (H.A) 126. Then, the sum data respectively obtained by the half adders 122 and 124 as the results of addition are added to each other by a half adder (H.A) 128, and the sum data obtained by the half adder 128 and the sum data obtained by the half adder 126 are added to each other by a half adder (H.A) 130. Then, a sign bit S of the matrix coefficient a.sub.il is added to the sum data obtained by the half adder 130. The 8-bit data thus obtained at the output of the half adder 130 is the data a.sub.il D.sub.B which is the resultant product obtained by multiplying the density datum D.sub.B by the matrix coefficient a.sub.il.

Though description has been made above as to the arrangement and operation of the multiplication circuit 106, it is a matter of course that the multiplication circuits 108 and 110 have the same arrangement and produce the products a.sub.i2 D.sub.G and a.sub.i3 D.sub.R, respectively, by an operation similar to the multiplication circuit 106.

FIG. 5 shows the arrangement of a second embodiment of the color masking circuit according to the present invention. In this embodiment, look-up tables 60, 62 and 64 constituted by ROMs are used, and the density data D.sub.B, D.sub.G and D.sub.R are applied in parallel, 18 bits in total, as a variable (address) to each of the look-up tables 60, 62 and 64. In the respective look-up tables 60, 62 and 64, the calculated values of the equations 4 corresponding to all of the possible values of input data (18 bits) are stored in the predetermined addresses of the ROMs. When the density data D.sub.B, D.sub.G and D.sub.R are inputted, the 6-bit density data D.sub.Y, D.sub.M and D.sub.C corresponding to those input data D.sub.B, D.sub.G and D.sub.R are read out.

FIG. 6 shows the main arrangement of a color video printer of a thermal transfer system which employs the foregoing color masking circuit according to the present invention.

A color television video signal of a standard system constituting a television picture, for example, a color television video signal S.sub.NTSC of an NTSC system is applied to an input terminal 10. The television video signal S.sub.NTSC is decoded into primary color video signals S.sub.R (red), S.sub.G (green) and S.sub.B (blue) by a RGB decoder 12. The primary color video signals S.sub.R, S.sub.G and S.sub.B then are converted into digital video signals, that is, picture elements P.sub.R, P.sub.G and P.sub.B are digitized by A/D converters 18, 20 and 22 at a predetermined sampling rate (for example, at a frequency four times as high as the frequency of a color sub-carrier) and with a predetermined quantizing bit number (for example, 6 bits). The picture elements P.sub.R, P.sub.G and P.sub.B are stored respectively in frame memories 24, 26 and 28 for every frame. At that time, the respective 6-bit picture elements P.sub.R, P.sub.G and P.sub.B are written-in in the order corresponding to the raster scanning of the television picture. The television video signal S.sub.NTSC is supplied also to a horizontal synchronization separating circuit 14, which synchronizes the horizontal synchronizing signal to the local horizontal synchronizing signal generated by phase locked loop 16.

For the purpose of a still picture monitor, one-frame picture elements P.sub.R, P.sub.G and P.sub.B stored in the frame memories 24, 26 and 28 are read out in the order corresponding to the raster scanning of the television picture, and they are restored into the analog primary color video signals S.sub.R, S.sub.G and S.sub.B by D/A converters 30, 32 and 34, respectively, and then restored into the television video signal S.sub.NTSC by an NTSC encoder 36, before being transferred to a monitor display 80. If the display 80 has an RGB terminal, the primary color video signals S.sub.R, S.sub.G and S.sub.B are directly transferred without passing through the encoder 36.

For making a hard copy of the television picture, the picture elements are read one line after another from the first line of the memory cells of the frame memories 24, 26 and 28, and are respectively latched in line memories 40, 42 and 44. The one-line color picture elements outputted from the respective line memories 40, 42 and 44 are input into an inverse gamma correction circuit 48 so as to be subjected to inverse gamma correction. Moreover, in the circuit 48, the above-mentioned equations 1 are executed by a digital logarithmic operator so that the density data D.sub.B, D.sub.G and D.sub.R are produced. Those density data D.sub.B, D.sub.G and D.sub.R then are supplied to a color masking circuit 50 according to the present invention as described above, in which the operation of the above-mentioned equations 4-1 to 4-3 are sequentially executed.

Corrected density data D.sub.Y, D.sub.M and D.sub.C produced from the color masking circuit 50 are supplied to a density-to-time converting circuit 52. In the density-to-time converting circuit 52, the density information of the respective density data D.sub.Y, D.sub.M and D.sub.C is converted into gradation data C.sub.Y, C.sub.M and C.sub.C for instructing the heat transfer time (the current conduction time to a heating resistor) for every picture element. That is, in the thermal transfer system shown, the period of time of current conduction to each heating resistor (printing element) of a thermal head (printing head) 54 is controlled by applying a constant voltage to each heating resistor so as to give proper gradation to the heating energy of the resistor to consequently give proper gradation to the quantity of ink transferred and hence to the density of the picture. The period of time of current conduction to the respective heating resistors corresponds to the density information of the respective density data.

FIG. 7 shows an applying time vs. density characteristic curve to be used in the density gradation system of the present invention. The density with a gradation level d.sub.1 is obtained when the voltage is applied to the heating resistor for the current conduction time t.sub.1 equivalent to a unit current conduction time .DELTA.t, and the density with a gradation level d.sub.2 is obtained when the voltage is applied for the current conduction time t.sub.2, which is two times as long as the unit current conduction time .DELTA.t. In this example, a maximum gradation level d.sub.64 in the vicinity of the saturation density is obtained when the voltage is applied for the current conduction time t.sub.64, which is sixty-four times as long as the unit current conduction time .DELTA.t.

The one line gradation data C.sub.Y, C.sub.M and C.sub.C, corresponding to the respective density data D.sub.Y, D.sub.M and D.sub.C, are supplied from the density-to-time converting circuit 52 to the thermal head 54 in a predetermined order, and the heating resistors aligned on one line generate heat for the time instructed by the corresponding gradation data C.sub.Y, C.sub.M and C.sub.C so that picture elements (recording dots) corresponding to those of the television picture are printed on one printing line.

The pictures of the respective colors (Y, M, C) are not printed at the same time, but are sequentially printed piece by piece in synchronism with the changing-over of ink sheets. Therefore, the gradation data C.sub.Y, C.sub.M and C.sub.C are sequentially supplied to the thermal head 54 for one piece after another. Since the color impurities in ink sheets and the like have been eliminated (corrected) by color masking in the manner described above, the printed picture is superior in color reproducibility.

A system controller 46 controls the operation of the whole printer, and in the case where the color masking circuit of the above-mentioned first embodiment is included in the printer, the system controller 46 gives data such as the preset masking coefficients a.sub.ij and the selector signals se.sub.0 and se.sub.1 to the color masking circuit 50. A mechanism control section 56 controls the operation of a printer mechanism section, and a mechanism sensor section 58 includes a head feed mechanism, a paper feed mechanism and various sensors. However, the application of the color masking circuit according to the present invention is not limited to the above-mentioned color video printer.

As described above, according to the present invention a matrix operation for color masking processing can be achieved at a high speed by means of hardware. In the first embodiment, for example, the circuit is constituted by multiplication and addition means. Moreover, if the color masking circuit according to the present invention is produced in the form of an LSI, the circuit can be constituted by few parts. Further, in a color video printer using the masking circuit according to the present invention, it is possible to obtain printed pictures in which impurities of color materials are cancelled so as to make the color reproducibility high.

Although only a few exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the preferred embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included in this invention as defined by the following claims.