Variable-Capacitance Diode Device

1. Field of the Invention:

This invention relates to a variable capacitance diode device suited to tuning with an electronic tuning circuit.

2. Description of the Prior Art:

Variable-capacitance diode devices have recently found extensive use as tuning elements for electronic tuning circuit. There have conventionally been demands for variable-capacitance diode devices with a wide voltage range. With a variable-capacitance diode device, as the potential difference across the junction thereof increases with a reverse bias voltage (referred to as applied voltage hereinafter), the width of depletion layer tends to expand with a distribution of impurity concentration in the semiconductor layer. To achieve a variable-capacitance diode device with a wide voltage range, it has been the usual practice that the impurity concentration in that region of the semiconductor layer where the depletion layer tends to expand, is controlled so as to be proximate to the Gaussian distribution, i.e., so as to decrease smoothly so that the expansion of the depletion layer increases gradually with the applied voltage. Recently, however, there have been demands for a variable-capacitance diode device which is designed such that a wide range of variation in the depletion layer width occurs with respect to the narrow range of variation in the applied voltage and sufficient tuning capacitance is available.

The conventional variable-capacitance diode device will now be described with reference to FIG. 1 wherein the abscissa represents the depth X.sub.i from the surface of the semiconductor substrate, and the ordinate indicate the impurity concentration C on a semi-logarithmic scale. In FIG. 1, the dotted curve (10) represents a semiconductor layer of the N.sup.+ conductivity type formed through a thermal diffusion of the impurity; and the solid curve (11) indicates a semiconductor layer of the P.sup.+ conductivity type. A PN junction J is defined between the N.sup.+ and P.sup.+ type semiconductor layers. Thus, the impurity concentration in the semiconductor layer of the N.sup.+ conductivity type as indicated by the curve (12) decreases smoothly except for the PN junction J, and it is usual that the concentration curve (12) represents a concentration profile in the form of Gaussian distribution which is proximate to the curve (10). Alternatively, the arrangement is made such that the impurity concentration decreases in steps along a curve corresponding to the Gaussian distribution and the width of the depletion layer expands with an increase in the voltage applied across the PN junction. In FIG. 1, the region indicated at (13) corresponds to an epitaxial layer, and the region shown at (14) corresponds to substrate.

However, it will be seen that the profile of impurity concentration in the N.sup.+ conductivity type semiconductor layer (indicated by the curve (12)), except in the proximity to the PN junction J, is such that the following relationship holds:

on the assumption that the impurity concentration at the highest point of the curve is A.sub.1, and those at sequential points are A.sub.2, A.sub.3, . . . , A.sub.i, A.sub.i+1, . . . respectively. The profile of impurity concentration in the region A.sub.1, A.sub.2, A.sub.3 appears approximate to the Gaussian distribution, and tends to swell out. Such swelling will be described with reference to FIG. 2 which illustrates the relationship between the applied voltage and the capacitance on semi-logarithmic scale.

As shown at (I) in FIG. 2, the relationship between the applied voltage and the capacitance varies along a curve resembling inverted S-shape corresponding to the profile of impurity concentration, instead of changing linearly from the maximum impurity concentration C.sub.max to the minimum impurity concentration C.sub.min. Thus, when the voltage range over which the capacitance is usable as tuning capacitance is wide, sufficient tuning capacitance is available, and critical problems are relatively less likely to arise. In contrast thereto, when it is desired that a variable-capacitance diode device having a similar construction to that of the prior art be operated with an applied voltage as low as 1 or 2 V, i.e., when it is attempted to make use of tuning capacitance occurring over a narrow voltage range as shown at (II) in FIG. 2, such a disadvantage that sufficient capacitance variation is not available, and thus the conventional device needs to be improved in this respect.

The present invention has been made with a view to eliminating the problems such as mentioned above.

It is a primary object of this invention to provide a variable-capacitance diode device which is so designed that sufficient tuning capacitance is available even with a low voltage.

Another object of this invention is to provide a variable-capacitance diode device which is designed so that the capacitance is varied substantially linearly with applied voltage on a semi-logarithmic scale.

Still another object of this invention is to provide a variable-capacitance diode device having such a construction that the impurity concentration at a predetermined depth can be reduced.

The present invention relates to a variable-capacitance diode device which is usable as a tuning element with an electronic tuning circuit. More particularly, the present invention provides a variable-capacitance diode device including a semiconductor layer of a first conductivity type wherein a high impurity concentration decreases gradually as the depth from the PN junction increases, and wherein the profile of impurity concentration in the semiconductor layer of the first conductivity type is such that at least one point where the following relation holds, occurs in the semiconductor layer of the first conductivity type:

on the assumption that the impurity concentration in terms of the distance X.sub.i depth-wise of the PN junction except in the vicinity of the PN junction is A.sub.i, thereby making it possible to achieve high capacitance with a variation in the applied voltage.

Other objects, features and advantages of the present invention will become apparent from the ensuring description taken in conjunction with the accompanying drawings.

FIG. 1 illustrates the impurity concentration profile of a conventional variable-capacitance diode device;

FIG. 2 is a view useful for explaining the relationship between applied voltage and capacitance;

FIG. 3 illustrates the impurity concentration profile of the variable-capacitance diode device according to an embodiment of this invention;

FIG. 4 is a view useful for explaining the relationship between applied voltage and capacitance in the device shown in FIG. 3;

FIGS. 5 and 6 illustrate impurity concentration profiles of the variable-capacitance diode devices according to other embodiments of the present invention.

Referring to FIG. 3, there is illustrated the profile of impurity concentration of the variable-capacitance diode device according to an embodiment of the present invention, wherein the abscissa indicates the depth X.sub.i from the surface of the semiconductor substrate, and the ordinate shows the impurity concentration C on a logarithmic scale.

As illustrated in FIG. 3, the variable-capacitance diode device according to this invention includes a PN junction J which is defined at a depth X.sub.1 from the surface of the semiconductor substrate by a P.sup.+ conductivity type semiconductor layer in which the impurity concentration is distributed as shown by the curve (3), and an N.sup.+ conductivity type semiconductor layer in which the impurity concentration is distributed as shown by the curves (4) and (5); and a point at a depth X.sub.2 from the surface of the semiconductor substrate where a low donor concentration of the N.sup.+ conductivity type semiconductor layer occurs, i.e., so-called inflection point T.

The capacitance C of the PN junction is related to the depletion layer width W and the area S of the PN junction as follows:

where .epsilon. is the product of the relative dielectric constant of silicon and the dielectric constant of a vacuum, i.e., it is equal to 1.062.times.10.sup.-8.

To decrease the capacitance C, on the other hand, it will be seen from Equation (1) that it is only necessary to increase the depletion layer width on the assumption that the area S of the PN junction is constant. Furthermore, the following equation holds true with respect to the depletion layer width: ##EQU1## where K=Factor of proportionality

N.sub.A =Acceptor concentration

N.sub.D =Donor concentration

V=Applied voltage

.PHI.=Diffusion potential

e=Electron charge (1.60.times.10.sup.-19 C)

Since the acceptor concentration N.sub.A is much higher than the donor concentration N.sub.D, i.e., N.sub.A >>N.sub.D, the following equation holds: ##EQU2##

Thus, to increase the depletion layer width W, it will be seen from Equation (2) that it is only necessary to decrease the donor concentration N.sub.D on the assumption that the applied voltage remains unchanged. In other words, it is only required that a region with a lower donor concentration be established in the N.sup.+ conductivity type semiconductor layer at the depth X.sub.i as measured from the surface of the semiconductor substrate.

The variable-capacitance diode device of this invention is constructed on the basis of the above-mentioned concept, wherein the PN junction J is defined, at the depth X.sub.1 from the surface of the semiconductor substrate, between the P.sup.+ conductivity type semiconductor layer with such an impurity concentration profile as shown by the dotted curve (3) and the N+ conductivity type semiconductor layer with such impurity concentration profiles as shown by the curves (4) and (5). The N+ conductivity type semiconductor layer represented by the curves (1) and (2) is arranged such that the inflection point T of the impurity concentration profile occurs at the depth of X.sub.2 as measured from the surface of the semiconductor substrate. More specifically, according to the present invention, the donor concentration is decreased by providing the inflection point T in the region A.sub.1, A.sub.2, A.sub.3 where swelling of the impurity concentration profile occurs.

Description will now be made of the formation of the N.sup.+ conductivity type semiconductor layers having such impurity concentration profiles as shown by the curves (1) and (2) in FIG. 3 respectively.

First, an N.sup.+ conductivity type semiconductor layer having such an impurity concentration profile as shown by a chain line (a) is formed through thermal diffusion or the like; and a P.sup.+ conductivity type semiconductor layer having such an impurity concentration profile as shown by a dotted line (b) is formed through thermal diffusion or the like. These two semiconductor layers are arranged such that the impurity concentrations along the curves (a) and (b) become equal or close to each other at a depth of X.sub.2 from the surface of the semiconductor substrate and the P.sup.+ conductivity type impurity concentration along the curve (b) never becomes higher than the N.sup.+ impurity concentration along the curve (a) at any point that is X.sub.i deep from the surface of the semiconductor substrate. Charges in the semiconductor layers represented by the curves (a) and (b) are provided by impurity elements which are opposite in charge polarity to each other; thus, a quantity of charges of the N.sup.+ conductivity type impurity element as represented by the curve (a) tend to be cancelled out with the same quantity of charges of the P.sup.+ conductivity type impurity element as represented by the curve (b). In this case, however, since the N.sup.+ conductivity type impurity concentration along the curve (a) is higher than the P.sup.+ conductivity type impurity concentration along the curve (b), charges in the semiconductor layers represented by the curves (a) and (b) turn out to be of the N.sup.+ conductivity type. In the region (or at any point) that is X.sub.2 deep from the surface of the semiconductor substrate, the impurity concentrations along the curves (a) and (b) are set up to be equal to each other so that the N.sup.+ and P.sup.+ conductivity type impurity charges are cancelled out each other and thus the quantity of charges in that region turns out to be substantially equal to the quantity of charges which exist inherently in the semiconductor substrate. Alternatively, the N.sup.+ conductivity type semiconductor layer may dominate to some extent, without being cancelled out as mentioned just above. At any point at the depth of X.sub.i as measured from the surface of the semiconductor substrate, however, the P.sup.+ conductivity type impurity concentration never exceeds the N.sup.+ conductivity type impurity concentration. It is not necessarily required that the impurity concentrations at the depth of X.sub.2 be equal to each other; rather, it is simply required that the P.sup.+ conductivity type diffusion layer be formed in such a manner that the impurity concentration thereof turns out to be close to that of the N.sup.+ conductivity type one at the depth of X.sub.2, as measured from the surface of the semiconductor substrate.

Referring again to FIG. 3, the curve (c) represents the profile of impurity concentration intrinsic in the epitaxial layer formed in the semiconductor substrate, and the curve (d) indicates the profile of impurity concentration of the semiconductor substrate. Although the epitaxial layer and substrate layer formed in the bottom portion of the semiconductor substrate include an inflection point of the N.sup.+ conductivity type impurity concentration, such an inflection point may be disregarded since the depletion layer simply extends short of those layers.

The variable-capacitance diode device according to this invention is arranged such that the impurity concentration profiles as represented by the curves (4) and (5) include a region in which the following relationship holds:

on the assumption that the N.sup.+ conductivity type impurity concentration in the vicinity of the PN junction J is A.sub.O ; the maximum peak of the impurity concentration profile represented by the curve (4) is A.sub.1 ; and the impurity concentrations at points scattered in the direction of depth X.sub.i are A.sub.2, A.sub.3, . . . , A.sub.i respectively. In other words, the variable-capacitance diode device according to this invention is arranged such that there occurs at least one point where the above-mentioned expression (3) holds true, except for the inflection points in the vicinity of the PN junction and in the portion of the epitaxial layer and substrate area. The region A.sub.3, A.sub.4, A.sub.5 in FIG. 3 is the region where the foregoing expression (3) holds true.

Referring to FIG. 5, there is illustrated another embodiment of the present invention which includes an N.sup.+ conductivity type semiconductor layer having such impurity concentration profiles as represented by curves (2), (3), (4) wherein more than one inflection point T occur at points each having a predetermined depth as measured from the surface of the semiconductor substrate.

Referring to FIG. 6, there is illustrated still another embodiment of the present invention which includes a gentle inflection point T, as opposed to the embodiment described above in connection with FIG. 3 wherein the impurity concentration profile of the N.sup.+ conductivity type semiconductor layer changes very sharply as indicated at A.sub.1, A.sub.2, A.sub.3, . . . , A.sub.i. It goes without saying that this embodiment is also arranged such that the profile of impurity concentration varies so as to satisfy the requirement as defined by the above-mentioned expression (3).

With the construction of the variable-capacitance diode device according to this invention which has such profiles of impurity concentration as shown in FIG. 3, the relationship between applied voltage and capacitance turns out to be substantially linear as shown at (II) in FIG. 4 so that sufficient tuning capacitance can be achieved even with application of as low a voltage as about 1 to 2 V, as opposed to the prior art wherein the curve representing the relationship between applied voltage and capacitance swells out in the form of inverted S-shape as shown at (I) in FIG. 4.

As will be appreciated from the foregoing discussion, according to the present invention, there is provided a variable-capacitance diode device wherein a region or point where the donor concentration is decreased, is provided in that portion of the N.sup.+ conductivity type semiconductor layer in the vicinity of the PN junction. Such a variable-capacitance diode device is advantageous in that a wide range of capacitance can be achieved even with application of a voltage as low as 1 to 2 V for example; the capacitance is varied with the applied voltage substantially linearly on logarithmic scale, which facilitates handling of the device; and sufficient tuning capacitance is achieved.

A further advantage is that the variable-capacitance diode device of this invention has such a construction as to make it easy to form a low impurity concentration region at a predetermined depth.

While the present invention has been illustrated and described with respect some specific embodiment thereof, it is to be understood that the present invention is by no means limited thereto but encompasses all changes and modifications which will become possible within the scope of the appended claims.