Circuit for Limiting Current Peaks at Turn-on of a Switching Transistor

This invention relates to a circuit arrangement for limiting the switching-on current peaks in a switching transistor having a control input to which rectangular switching pulses of the same height are applied.

Such an arrangement is known, for example, from German Patent Application DE-35 18 913. The switching transistor--a field effect transistor--in the known arrangement is included in the primary circuit of a clocked direct voltage converter. A pulse width modulator controls the switching time of the field effect transistor in that it applies between the gate and source connections of the transistor rectangular switching pulses which vary in length. A saturable choke by which the switching-on current peaks are limited is arranged in series with the main current path of the switching transistor, i.e. in the drain supply lead.

When the transistor is switched to the conducting state, without the use of the saturable choke the overall input voltage drops across its drain-source path. Therefore, high current peaks (8 A and higher) occur and thus high power dissipations in the transistor are the result, which can lead to its destruction. The choke limits the current peaks and then reaches the saturated state so that the further behaviour of the converter during a switching pulse is not influenced thereby.

Since, however, the choke is arranged in the operating circuit of the transistor, at the switching-on instants of the transistor a voltage difference of the order of the input voltage of the direct voltage converter appears across this choke. The choke must therefore be dimensioned so that it is capable of withstanding, without damage, accidental voltage differences of the indicated order. Dependent upon the type of application, the input voltage of a direct voltage converter can lie at a few volts or at a few hundred volts. Therefore, the known protection circuit must be dimensioned anew for each type of application if it is not to be unnecessarily overdimensioned.

An object of the invention is to provide a circuit arrangement of the kind mentioned in the opening paragraph, which need not be dimensioned in accordance with the voltage conditions in the operating circuit of the switching transistor.

This object is achieved in that a coil is included in a connection lead of the switching transistor, which coil is traversed by the operating current of the switching transistor, in that the voltage produced by self-induction of this coil counteracts the control voltage of the switching transistor and in that the self-inductance of the coil is proportioned so that only the occurrence of switching-on current peaks leads to an effective reduction of the control voltage of the switching transistor.

When the coil is arranged in accordance with the invention, it need not have a magnetically saturable core. The maximum voltage differences that may occur between its connections are equally as large as the height of the switching pulses for the switching transistor so that its magnetic cross-section and its number of turns need only be dimensioned in accordance with this load. The number of turns can be chosen in all types of application to be so small that the winding capacitance of the coil is pratically zero.

Advantageous embodiments and a further improvement of the invention can be derived from the following description. In a further improvement of the invention, a circuit arrangement is provided by means of which the operating current through the switching transistor of a clocked direct voltage converter is monitored. In direct voltage converters having a high power transmission, the further improvement has the advantage that smaller losses occur than in monitoring circuits in which the operating current flows through an ohmic measuring resistor.

In order that the invention may be readily carried out, it will now be described more fully, by way of example, with reference to the sole FIGURE of the accompanying drawing which shows a preferred embodiment of the invention.

The FIGURE shows the principle circuit diagram of a clocked direct voltage converter which employs the invention along with its further improvement.

The primary circuit of the direct voltage converter, to whose input E.sup.+, E.sup.-, an input voltage UB is applied, includes the parallel-combination of a capacitance CL and the primary coil of a transformer U as well as the main current path of a field effect transistor T, whose drain connection D is connected to the parallel-combination and whose source connection S is connected through a further coil PW to the negative terminal E.sup.- of the input voltage source. A demagnetization diode DE1 is connected in reverse direction parallel to the coil PW. A pulse width modulator PWM supplies the gate of the field effect transistor T with control pulses UST. The control voltage UST is applied between the gate connection G of the transistor and the negative terminal E.sup.- of the primary voltage source. When the transistor T is opened, the control voltage UST is 15 V, while, when it is closed, this voltage is zero V. The capacitance CL is the winding capacitance of the transformer U transformed to the primary side. The secondary circuit of the transformer U, which at the same time is the output circuit of the direct voltage converter, includes a first rectifier diode GR1 and an output capacitor CA, at which an output voltage UA is developed. A voltage divider R1, R2, whose centre tapping is connected to an input of the pulse width modulator PWM, is arranged parallel to the capacitor CA.

When the transistor T is cut off, the overall input voltage UB appears between its drain and source connections. When the transistor is opened, the capacitance CL acts, at the switching-on instant, as a shortcircuit so that the voltage UB now is applied between the drain connection D and the negative terminal E.sup.- of the input voltage source, i.e. appears across the series-combination of the low-ohmic drain-source path of the transistor T and of the coil PW.

A rapid increase of the current I is now also avoided by means of the coil PW, which need not have a saturable core, in that it reduces the gate-source voltage of the transistor T to substantially zero volt. Thus, the flow of the current through the transistor T is controlled so that at the ends of the coil PW a voltage difference larger than 15 V can never occur. Its inductance is solely to be proportioned so that the transistor T remains conducting in the operating range of the current I. The energy contained in the switching-on current peak of the current I is stored in the coil PW as magnetic energy and is converted into heat through the demagnetization diode DE1 when the current I decays.

It has not been taken into account in the explanation given thus far that the coil PW is the primary coil of a current converter STW. This fact is of no importance for the switching-on processes because the secondary coil of the current converter STW--as will be explained more fully below--has such a high ohmic value that the reaction of the secondary circuit on the primary circuit of the current converter STW is practically negligible.

The object of the secondary circuit of the current converter STW is to shorten, via the pulse width modulator PWM, the switching-on time of the transistor T when the current i, increasing at a substantially constant varying rate, exceeds a critical value. The pulse width modulator must remain uninfluenced by the processes described above at the switching-on instant.

For this reason, the series arrangement of a second rectifier diode GR2 and of a first load resistor RB1 (load) is connected between the connections of the secondary coil SW of the current transformer STW. The series arrangement of a choke DR and of a second load resistor RB2 is connected parallel to the first load resistor RB1. The choke DR is shunted by a second demagnetization diode DE2. The output connections of the secondary circuit correspond to the connections of the second load resistor RB2. The voltage present between these connections is applied to the current monitoring connections of the pulse width modulator PWM, which in the present example is the integrated element UC1846. The choke DR is saturable, that is to say that its core is made of a material which in operating conditions goes into magnetic saturation.

Now when the transistor T is switched into the conducting state, a voltage is developed across the connections of the secondary winding SW or across the load resistor RB1, which voltage initially has a peak starting at zero and then increases uniformly to a limit value. The resistance value of the load resistor RB1 is chosen so that the ratio of the variation in time of the voltage drop across it to the variation in time of the current i in the primary circuit of the direct voltage converter is analogous to a great extent. This analogy is utilized to immediately shorten the switching-on times of the transistor T when the voltage across the load resistor RB1, apart from the peak, exceeds a critical value. Use is made for this purpose of the voltage divider comprising the saturable choke DR and the second load resistor RB2, whose resistance value amounts approximately to one hundredth of the resistance value of the first load resistor RB1. The current flowing through this voltage divider increases with the voltage across the load resistor RB1, apart from a current peak suppressed by the choke DR. When the current through the choke DR has exceeded a threshold depending upon the dimensioning of the choke DR, it goes into magnetic saturation. This process leads to a more rapid current increase through the choke DR and hence to a more rapid voltage increase across the resistor RB2. The choke DR therefore acts as a current-dependent resistor; when it is not saturated, the overall load connected to the secondary coil SW is small, while, when it is saturated, the load is increased. The increased overall load results in that on the primary side of the current converter STW only its parasitic inductance is still active. This is particularly advantageous for the dimension of the inductance of the primary coil PW when high operating currents can flow. When the current I further increases, this is also the case for the current through the load resistor RB2 and hence for the voltage drop across it. When, finally, this voltage is applied at a threshold adjustable at the pulse width modulator PWM, the transistor T is cut off immediately until the next switching pulse occurs.

As already indicated, it should be ensured with the proportioning of the resistors RB1 and RB2 that the resistance value of the resistor RB1 is considerably larger (about a factor 100 larger) than that of the resistor RB2. Moreover, the resistance value of the resistor RB1 must also be large with respect to the ohmic resistance of the windings PW and SW in order that the above explanations of the operation of the coil PW hold good. At 15 V for the voltage UST, the current converter STW can be constructed so that the resistor RB1 has a value of a few hundred ohms and the resistor RB2 has a value of a few ohms.