Differential Transconductance Circuit

The invention relates to a transconductance circuit comprising

a first and a second transistor of a first conductivity type having their bases coupled to input terminals for receiving an input signal and having their emitters connected to a common point by means of a first resistor, which common point is coupled to a first power-supply terminal by means of a current source, and

a third transistor of the first conductivity type whose collector-emitter path is arranged between a second power-supply terminal and the common point and having its base coupled to a tap of a voltage divider comprising two substantially identical second resistors arranged between the bases of the first and the second transistor.

Such a circuit arrangement is generally suitable for use in integrated circuits and is particularly suitable for those uses where a comparatively large input voltage range is required.

Such an arrangement is known from European Patent Application 0,157,447 and corresponding U.S. Pat. No. 4,612,513. In the absence of an input voltage most of the current from the current source flows through the third transistor, so that only a small current will flow through the first resistors and the first and the second transistor. When the input voltage increases the current through the third transistor decreases and the current through either the first or second transistor increases until the entire current from the current source flows through this transistor. As a result of the small quiescent current through the first resistors and the first and the second transistor this circuit has a very low input offset voltage. Moreover, since the current through the first and the second transistor increases as the input voltage increases the circuit has a substantial slew rate.

However, a drawback of this circuit is that it exhibits a comparatively large non-linearity, which is caused by the fact that for low input voltages the transconductance of the circuit is substantially twice as high as that for high input voltages. Indeed, for low input voltages both the first and the second transistor contribute to the signal output current, whereas for high input voltages only one of the transistors contributes to this current.

Therefore, it is an object of the invention to improve the linearity of the known transconductance circuit. According to the invention a transconductance circuit of the type defined in the opening paragraph is characterized in that the circiut further comprises

a fourth and a fifth transistor of the first conductivity type, having their collector-emitter paths arranged in series with the collector-emitter paths of the first and the second transistor, having their bases coupled to a reference-voltage terminal, and having their collectors coupled to the output terminals for supplying an output signal, and

a third resistor arranged between the emitters of the fourth and the fifth transistor.

For low input voltages the currents through the first and the second transistor and hence those through the fourth and the fifth transistor are comparatively small. The base-emitter resistances of the fourth and the fifth transistor are then comparatively high. A part of the signal current through the first and the second transistor consequently flows through the third resistor, causing the output signal current and hence the transconductance of the circuit to be reduced. For high input voltages and consequently comparatively large collector currents the base-emitter resistances are comparatively low, so that almost the entire signal current flows into the collectors of the forth and the fifth transistor. As a result of this, comparatively high input voltages have hardly any influence on the transconductance of the circuit. The steps in accordance with the invention thus ensure that for low input voltages the transconductance is better in conformity with that for high input voltages, which improves the linearity of the circuit.

An embodiment of the circuit in accordance with the invention is characterized in that the circuit further comprises a sixth and a seventh transistor of a second conductivity type, having their collector-emitter paths arranged between the emitters of the first and the second transistor and the first power-supply terminal and having their bases coupled to the bases of the first and the second transistor. In the known circuit the input voltage range depends inter alia on the value of the current source, which dictates the maximum output current of the circuit. The current of this current source cannot be selected arbitrarily large because the quiescent current through the first resistors and the first and the second transistor and hence the input voltage offset will then increase. In the embodiment of the circuit in accordance with the invention the input voltage range is extended in that the sixth and the seventh transistor are turned on at high input voltages to supplement the current from the current source. In addition, the sixth and the seventh transistor protect the first and the second transistor against base-emitter breakdown owing to high negative base-emitter voltages.

The invention will now be described in more detail, by way of example, with reference to the accompanying drawing, in which

FIG. 1 shows the basic diagram of a transconductance circuit in accordance with the invention, and

FIG. 2 shows an embodiment of a transconductance circuit in accordance with the invention.

FIG. 1 shows the basic diagram of a transconductance circuit in accordance with the invention. The circuit comprises two NPN transistors T.sub.1 and T.sub.2 whose emitters are connected to a common point 2 via two substantially identical resistors R.sub.1, which common point is connected to the negative power-supply terminal 3, in the present case ground, by means of a current source 1. The bases of the transistors T.sub.1 and T.sub.2 are connected to input terminals 4 and 5 for receiving an input voltage V.sub.i. Moreover, a voltage divider comprising two substantially identical resistors R.sub.2 is arranged between the bases of the transistors T.sub.1 and T.sub.2, the junction point between said resistors being connected to the base of an NPN transistor T.sub.3. The collector-emitter path of this transistor is arranged between the positive power-supply terminal 6 and the common point 2.

The collector-emitter paths of two NPN transistors T.sub.4 and T.sub.5 are arranged in series with the collector emitter paths of the transistors T.sub.1 and T.sub.2. The bases of said transistors T.sub.4 and T.sub.5 are connected to a terminal 7 for a reference potential. A resistor R.sub.3 is arranged between the emitters of the transistors T.sub.4 and T.sub.5. The collectors of these transistors are connected to output terminals 8 and 9 from which the output currents of the circuit can be taken. The terminals 8 and 9 may be interconnected, for example by means of a differential-to-single-ended converter, such as a current mirror. However, alternatively the terminals 8 and 9 may be connected to any other active or passive load.

When the transistors T.sub.4 and T.sub.5 and the resistor R.sub.3 are ignored, the circuit operates as follows. In the quiescent state the bias current through the transistors T.sub.1 and T.sub.2 is much smaller than that through the transistor T.sub.3 as a result of the feedback resistors R.sup.1 so that most of the current I.sub.0 from the current source 1 flows through the last-mentioned transistor. As a result of the small bias currents the circuit has a very low input offset voltage. As the input voltage increase the current through the transistor T.sub.3 decreases gradually to zero, and the current through, for example, the transistor T.sub.1 increases gradually until the entire current I.sub.0 flows through this transistor.

The maximum signal current which can be delivered by the circuit is equal to the difference between the collector currents of the transistors T.sub.1 and T.sub.2. For high input voltages one of the transistors T.sub.1 and T.sub.2 is wholly or substantially cut off, so that only one of these transistors contributes to the output signal current. This current is inversely proportional to the sum of the resistance values of the resistors R.sub.1. For low input voltages both transistors carry equal signal currents of opposite phase and of a magnitude which is also inversely proportional to the sum of the resistance values of the resistors R.sub.1 if the base-emitter resistances of the transistors T.sub.1 and T.sub.2 are ignored. Consequently, the maximum output current is substantially inversely proportional to the resistance value of the resistor R.sub.1. The transconductance of the circuit for low input voltages is therefore substantially twice as high as that for high input voltages. This input voltage which increases as the transconductance decreases leads to non-linearities of the output signal.

By means of the transistors T.sub.4 and T.sub.5 and the resistor R.sub.3 the transconductance of the circuit for low input voltages is reduced, so that it more closely approximates to the transconductance for high input voltages. For low input voltages the base-emitter resistance of the transistors T.sub.1 and T.sub.2 will then be comparatively high because the bias currents are then small. Since the bias currents through the transistors T.sub.4 and T.sub.5 are equal these transistors also have comparatively high base-emitter resistances. If the value of the resistor R.sub.3 is small relative to the value of said resistances a part of the signal current flowing in the collectors of the transistors T.sub.1 and T.sub.2 will flow through the resistor R.sub.3. The signal currents in the collectors of the transistors T.sub.4 and T.sub.5 are consequently smaller than those in the collectors of the transistors T.sub.1 and T.sub.2. As a result of this the circuit will have a lower transconductance for small input voltages than the known circuit. For high input voltages the circuit is hardly influenced by the transistors T.sub.4 and T.sub.5 and the resistor R.sub.3. For high input voltages the base-emitter resistances of the transistors T.sub.4 and T.sub.5 are low relative to the resistance value of the resistor R.sub.3 because the bias currents flowing through these transistors are then larger. As a consequence, the signal current flowing in the collectors of the transistors T.sub.4 and T.sub.5 will be substantially equal to that in the collectors of the transistors T.sub.1 and T.sub.2.

For a specific current I.sub.0 of the current source 1 the resistance value of the resistor R.sub.3 for an optimum linearity of the circuit can be computed as follows. For high positive input voltages V.sub.in the collector signal current of the transistor T.sub.4 complies with:

The transistor T.sub.2 is then substantially cut off, so that:

Obviously, the situation is reversed for high negative input voltages. Consequently, the difference between the two collector currents complies with:

For low input voltages both transistors T.sub.1 and T.sub.2 carry a signal current. The signal current in the collector of the transistor T.sub.1 complies with: ##EQU1## and that of the transistor T.sub.2 complies with: ##EQU2## where s is the transconductance and Vbe is the base-emitter voltage of the relevant transistor. If for low input voltages the transconductance of the circuit must be equal to that for large input voltages this means that

Since the collector current of the transistor T.sub.1 is equal to the sum of the collector current of the transistor T.sub.4 and the current through the resistor R.sub.3 this means that: ##EQU3## It follows that for an optimum value of the resistor R.sub.3 the following requirement must be met: ##EQU4##

The transconductance s=qI1/kT, where I.sub.1 is the quiescent current through the transistors T.sub.1 and T.sub.2, k is Boltzmann's constant, q is the elementary charge and T is the absolute temperature. The magnitude of the current I.sub.1 can be derived simply from the voltage equation for the loop comprising the base-emitter junctions of the transistors T.sub.1 and T.sub.3 and the resistors R.sub.1 and R.sub.2 and from the equation for the sum of the current through the transistors T.sub.1, T.sub.2 and T.sub.3, which is equal to the current I.sub.0 of the current source 1.

Since the transconductance s is inversely proportional to the absolute temperature the current I.sub.1 and hence the current I.sub.0 of the current source I should preferably increase as a direct proportional function of the absolute temperature in order to achieve an optimum value of the resistance over a wide temperature range. Such PTAT current sources (PTAT=Proportional To Absolute Temperature) are generally known and require no further explanation. Such a current source is shown, for example, on page 283, FIG. 425 in the book "Analysis and Design of Analog Integrated Circuits", 1984.

In FIG. 2, which shows an embodiment of the circuit in accordance with the invention, identical parts bear the same reference numerals as in FIG. 1. In this circuit the emitters of the transistors T.sub.1 and T.sub.2 are connected to the negative power-supply terminal 3 by means of the collector-emitter paths of the PNP transistors T.sub.6 and T.sub.7. The base of the transistor T.sub.6 is connected to the base of the transistor T.sub.1 and the base of the transistor T.sub.7 is connected to the base of the transistor T.sub.2. In the circuit shown in FIG. 1 the effective input-voltage range is dictated by the current I.sub.0 from the current source 1. This is because the current I.sub.0 is the maximum output current of the circuit. The current I.sub.0 cannot be selected too large because otherwise the input offset voltage will increase excessively. In the circuit shown in FIG. 2 the input-voltage range is extended in that for high input voltages the transistors T.sub.6 and T.sub.7 are turned on to increase the bias current of the circuit. In addition, the transistors T.sub.6 and T.sub.7 protect the transistors T.sub.1 and T.sub.2 against emitter base breakdown in the case of high voltages across the emitter base junctions of these transistors.

The invention is not limited to the embodiments shown herein. For example, the circuits shown may be equipped with transistors of opposite conductivity types. Moreover, the transistors may have either equal or unequal emitter areas.

In addition, it is possible to merely increase the input-voltage range of the circuit and to refrain from the linearity correction if the latter aspect is not important.