Method of Manufacturing a Semiconductor Device

1. Field Of the Invention

The present invention relates to a method of manufacturing a dielectric-isolated semiconductor device having a high isolation breakdown voltage.

2. Description of the Prior Art

It is well known in the art that a thin layer of silicon is preferably formed on a dielectric substrate in order to attain good electrical insulation between electric components provided on the substrate, as well as to cause no irregularity on the substrate surface. A method of forming a silicon layer on a substrate having an insulation layer has been studied since around 1964 to attain the aforementioned object, and a method called dielectric isolation has been developed as summarized in J. Electrochem. Soc. Vol. 124, No. 1, 1977, pp. 5c-12c.

FIG. 1A to FIG. 1F are cross sectional views showing a conventional method of manufacturing a semiconductor device of a high breakdown voltage by dielectric isolation.

As shown in FIG. 1A, a silicon oxide film is first provided on the surface of a silicon substrate 20, and portions to define grooves in the silicon substrate 20 are removed by photoengraving process and silicon oxide film etching process to form a silicon oxide film pattern 23. The silicon oxide film pattern 23 is utilized as a mask to etch exposed surface parts of the silicon substrate 20 by an etching solution mainly composed of KOH, to define grooves 27 enclosed by (111) surfaces of a slow etching speed, as shown in FIG. 1B.

Then, the silicon oxide film pattern 23 is removed and thereafter n.sup.+ type diffusion is performed over the entire surface, to form an n.sup.+ type diffusion layer 28, as shown in FIG. 1C. Thereafter a thick silicon oxide film 21 is formed as shown in FIG. 1D. Then a polysilicon layer 22 of about 500 .mu.m in thickness is formed on the silicon oxide film 21, as shown in FIG. 1E. Finally the silicon substrate 20 is mechanically polished from its underside, so that monocrystal silicon island can be obtained on an insulation film formed by the silicon oxide film 21, as shown in FIG. 1F.

A large number of processes for improving this method have been reported. The feature of such processes also resides in growing on a silicon substrate a thick polysilicon layer for serving as a support substrate and polishing or etching of the silicon substrate to appropriate thickness.

In the conventional method of manufacturing a semiconductor device having a high breakdown voltage as hereinbefore described, extremely thick polysilicon growth of 500 .mu.m must be performed in order to form the polysilicon layer 22. Thus, productivity in the growth step is inferior while the wafer is extremely warped. Further, since the monocrystal silicon islands are formed on the underside of the silicon oxide film 21 by mechanical polishing, they are essentially inferior in thickness accuracy, while damage is left on the surface of the silicon substrate 20.

According to the present invention, a method of manufacturing a semiconductor device comprises the steps of preparing a semiconductor substrate of a predetermined conductivity type, implanting at least either nitrogen ion or oxygen ion into a portion of predetermined depth in the semiconductor substrate to form a dielectric layer, a portion of the semiconductor substrate on the dielectric layer being defined as a residual semiconductor layer, annealing the semiconductor substrate provided with the dielectric layer, and forming an epitaxial semiconductor layer having a thickness over 2 .mu.m on the residual semiconductor layer by epitaxial growth.

Accordingly, it is an object of the present invention to provide a method of manufacturing a dielectric-isolated semiconductor device of a high breakdown voltage which is excellent in productivity with no warp of a wafer, while being also excellent in thickness accuracy of a semiconductor layer with no damage left on a surface.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1A to FIG. 1F are sectional views showing a conventional method of manufacturing a semiconductor device of a high breakdown voltage bY dielectric isolation;

FIG. 2A to FIG. 2K are sectional views showing an embodiment of a method of manufacturing a semiconductor device of a high breakdown voltage by dielectric isolation in accordance with the present invention;

FIG. 3 typically illustrates crystal states with respect to the amount of oxygen ion implantation and annealing temperature;

FIG. 4 is a graph showing a relationship between the amount of ion implantation, thickness of a buried SiO.sub.2 layer and thickness of a surface residual silicon layer: and

FIG. 5A to FIG. 5C are sectional views showing another embodiment of the method of manufacturing a semiconductor device of a high breakdown voltage by dielectric isolation in accordance with the present invention.

FIG. 2A to FIG. 2K are sectional views showing an embodiment of a method of manufacturing a semiconductor device of a high breakdown voltage in accordance with the present invention. In this embodiment, element isolation is performed by SIMOX (separation by implanted oxygen).

As shown in FIG. 2A, oxygen ions 5 are ion-implanted into a p type silicon substrate 1 having its (001) surface as a major surface under acceleration voltage of 150 keV by 2.3.times.10.sup.18 cm.sup.-2, to form a buried silicon oxide layer (hereinafter referred to as "buried SiO.sub.2 layer") 6 serving as a dielectric layer as shown in FIG. 2B.

Then, an SiO.sub.2 film 12 is formed on the surface of the p type substrate 1 to serve as a protective film for annealing, as shown in FIG. 2B. Thereafter annealing is performed at 1350.degree. C. for 30 minutes to leave a surface residual silicon layer 4 of 700 .ANG. in thickness while simultaneouslY forming the buried SiO.sub.2 layer 6 of 5000 .ANG. in thickness having complete interatomic connection.

The SiO.sub.2 film 12 is removed from the surface of the p type substrate 1, and thereafter antimony ions 17 of high concentration are ion-implanted as shown in FIG. 2C and diffused to form n.sup.+ type layer in the surface residual silicon layer 4.

The surface of the p type substrate 1 is cleaned and thereafter the wafer is heated up to 950.degree. C. in an atmosphere of dichlorosilane (H.sub.2 --SiH.sub.2 Cl.sub.2) gas, to epitaxially grow an n.sup.- type silicon layer 8 of 50 .mu.m in thickness on the surface residual silicon layer 4, as shown in FIG. 2D.

Then, an SiO.sub.2 layer 13 is formed on the n.sup.- type silicon layer 8 as shown in FIG. 2E, and is provided with windows in predetermined portions of the SiO.sub.2 layer 13 by photoengraving process and SiO.sub.2 etching process.

Portions of the n.sup.- type silicon layer 8 and the n.sup.+ type surface residual silicon layer 4 corresponding to the windows of the SiO.sub.2 layer 13 are selectively etched by an etching solution mainly composed of KOH as shown in FIG. 2F by using the SiO.sub.2 layer 13 as a mask, to dig grooves 14 to reach the buried SiO.sub.2 layer 6.

Then, n.sup.+ type diffusion is performed on sides of the grooves 14 to form n.sup.+ type silicon layers 9 as shown in FIG. 2G. Thereafter the SiO.sub.2 layer 13 is removed. The n.sup.+ type silicon layers 9 can be easily formed on the sides of the grooves 14 by ion implantation through the SiO.sub.2 layer 13 serving as a mask, for example, since opening portions of the grooves 14 are tapered toward the buried SiO.sub.2 layer 6. Thus, the bottom and side surfaces of the n.sup.- type silicon layer 8, which is element-isolated by the grooves 14, are provided with n.sup.+ type layers (the surface residual silicon layer 4 and the n.sup.+ type silicon layers 9).

Thereafter the SiO.sub.2 layer 13 is removed and an element isolation SiO.sub.2 layer 10 of 2 .mu.m in thickness is formed over the entire surface, as shown in FIG. 2H. Further, a polysilicon layer 11 is grown on the element isolation SiO.sub.2 layer 10 up to 80 .mu.m in thickness, as shown in FIG. 2I.

Then the surface of the polysilicon layer 11 is mechanically polished to be flattened. Such polishing is stopped when the element isolation SiO.sub.2 layer 10 is exposed. Then the element isolation SiO.sub.2 layer 10 and the polysilicon layer 11 are planarly removed by chemical treatment, to expose a surface with no damage of the n.sup.- type silicon layer 8, as shown in FIG. 2J.

Thus, the n.sup.+ type surface residual silicon layer 4, the n.sup.- type silicon layer and the n.sup.+ type silicon layers 9 are enclosed by the buried SiO.sub.2 layer 6 and the element isolation SiO.sub.2 layer 10, to be completely isolated from adjacent element regions. The n.sup.- type silicon layer 8 is subjected to various semiconductor processing steps, to obtain a semiconductor device having an element isolation structure of a high breakdown voltage, as shown in FIG. 2K.

Since the center of &he element region &thus obtained is n.sup.- type, i.e., low impurity concentration, a depletion layer can be easily extended from a p-n junction formed in the element region, to improve junction breakdown voltage. Further, since the .sup.+ type diffusion layers 9 of low resistance are provided on the sides of the element region, a current flowing in the bottom portion (surface residual silicon layer 4) of the element region can be extracted on the surface part of the element region through the n.sup.+ type diffusion layers 9.

This method of manufacturing a semiconductor device by carrying out element isolation as hereinbefore described and performing various processing steps on the isolated element region ha the following advantages:

First, the surface of the n.sup.- type silicon layer 8, which is provided with semiconductor elements, is excellent in crystallinity since the surface is not mechanically polished. and, therefore, has no damage. Secondly, the n.sup.- type silicon layer 8 is excellent in reproducibility and controllability of film thickness since the same is formed by epitaxial growth. For example, reproducibility in the case of forming an n.sup.- type silicon layer 8 of 50 .mu.m in thickness is within .+-.1 .mu.m. Thirdly, warp of the wafer is minimized since the polysilicon layer 11 is formed in thickness of 80 .mu.m. Further, the formation time of the polysilicon layer 11 can be extremely shortened to improve productivity as compared with the conventional case, in which a polysilicon layer of 500 .mu.m in thickness must be formed.

A similar effect can be attained by employing nitrogen ion in place of oxygen ion to form a dielectric layer.

The n.sup.- type silicon layer 8, formed by epitaxial growth, is 50 .mu.m in thickness for the following reason: Since oxygen ions are implanted into the p type substrate 1 in this manufacturing method, the surface residual silicon layer 4 contains oxygen of high concentration. Such oxygen is left after annealing processing to cause a lattice defect, such as dislocation, in the surface residual silicon layer 4. However, such dislocation can be completely prevented, by forming the n.sup.- type silicon layer 8 of about 50 .mu.m in thickness by epitaxial growth on the surface residual silicon layer 4, since oxygen concentration in an upper part of the n.sup.- type silicon layer 8 is decreased to reduce dislocation density, as the growth thickness of the layer 8 is increased. It has been confirmed through an experiment that dislocation can be completely prevented in a portion of the n.sup.- type silicon layer 8 exceeding 2 .mu.m in height, if epitaxial growth over 2 .mu.m is performed.

FIG. 3 typically shots crystal states in relation to the amount of oxygen implantation and annealing temperature in the case of forming a buried SiO.sub.2 layer by oxygen ion implantation into a silicon substrate. Oxygen ions implanted into a silicon substrate 15 inwardly advance in the silicon substrate 15 and is stopped at depth corresponding to an acceleration voltage. These oxygen ions have to be in constant distribution corresponding to the acceleration voltage. i.e., the so-called LSS (Lindhard-Scharf-Schiott) distribution. Symbol R.sub.O indicates the distance of the deepest implantation from the surface of the silicon substrate 15. In a surface residual silicon layer 4 having depth R.sub.D through which the oxygen ions 5 pass, damage such as a lattice defect is caused by the impact of implantation of the oxygen ions 5, and hence crystallinity in the surface residual silicon layer 4 becomes imperfective.

When the amount of oxygen ion implantation is increased to a critical amount .phi..sub.C, formation of a buried SiO.sub.2 layer 6 is started in the silicon substrate 15. When acceleration voltage is 200 keV and the ion implantation temperature T.sub.i is in excess of 500.degree. C., for example, the critical amount .phi..sub.C of implantation is about 1.4.times.10.sup.18 cm.sup.-2. When the oxygen ions 5 are further implanted in excess of the critical amount .phi..sub.C, the buried SiO.sub.2 layer 6 is increased in thickness while the silicon substrate 15, into which the oxygen ions are implanted, is also increased in thickness. However, since the oxygen ions 5 knock out silicon atoms of the surface of the silcion substrate 15 upon implantation, the surface of the silicon substrate 15 is changed as shown by the solid line with increase in amount of implantation of the oxygen ions 5, although the same is theoretically changed as shown by the broken line. Thus, the thickness of the surface residual silicon layer 4 is reduced.

Then, the silicon substrate 15, implanted with the oxygen ions 5, is heated to be annealed. Such annealing processing Is performed In order to remove a lattice defect, caused by impact upon ion implantation, from the surface residual silicon layer 4, to thereby recover its crystallinity. At the same time, the buried SiO.sub.2 layer 6 is increased in thickness and interatomic connection become perfect while an Si/SiO.sub.2 interface 16 is clarified. Increase in thickness of the buried SiO.sub.2 layer 6 is saturated by annealing processing at a temperature exceeding 1250.degree. C.

F1G. 4 shows a relationship between the amount& of oxygen ion implantation, thickness of a buried SiO.sub.2 layer and thickness of a surface residual silicon layer, while Table 1 lists up some of values read from FIG. 4 and breakdown voltages.

Referring to FIG. 4, straight lines L1 to L4 represent thickness values of a surface residual silicon layer 4 in the case of implanting oxygen ions 5 into a silicon substrate 15 at acceleration voltage of 150 keV through a screen oxide film of 0 .ANG., 500 .ANG., 750 .ANG.and 1000 .ANG. in thickness, respectively. and a broken line BL1 represents thickness of a buried SiO.sub.2 layer 6.

As is obvious from Table 1 , thickness of the buried SiO.sub.2 layer 6 must be increased in order to increase breakdown voltage. However, thickness of the surface residual silicon layer 4 is reduced as thickness of the buried SiO.sub.2 layer 6 is increased. For example, since a buried SiO.sub.2 layer formed by oxygen ion implantation generally has field strength of 8 to 10.times.10.sup.6 V/cm, a breakdown voltage of about 500 V is obtained by implanting oxygen ions 5 of 2.7.times.10.sup.18 cm.sup.-2 into a silicon substrate as shown in Table 1, while thickness of a surface residual silicon layer is 150 .ANG.. When the amount of implantation of the oxygen ions 5 is further increased, thickness of the surface residual silicon layer is reduced to less than 150 .ANG., whereby it becomes technically difficult to perform a step of epitaxially growing a new silicon layer on the surface residual silicon layer 4, subsequently to oxygen ion implantation and annealing. Namely, the limit of breakdown voltage is at the level of 500 V in a method of forming a buried SiO.sub.2 layer by oxygen ion implantation, i.e., the so-called SIMOX. Thus, it is difficult to produce a semiconductor device requiring higher breakdown voltage.

FIG. 5A to FIG. 5C are sectional views showing another embodiment of the method of manufacturing a semiconductor device in accordance with embodiment of the present invention, which solves the aforementioned problem concerning the limit of a breakdown voltage. First, nitrogen ions 2 are ion-implanted into a p type substrate I, which has a major surface of (001) surface, under acceleration voltage of 400 keV by 1.5.times.10.sup.18 cm.sup.-2, as shown in FIG. 5A, to form a nitrogen ion implanted layer 3 of .+-.2000 .ANG. in width around a position of about 6000 .ANG. in depth from the surface of the p type substrate 1.

Then, as shown in FIG. 5B, oxygen ions 5 are implanted under 150 keV by 2.3.times.10.sup.18 cm.sup.-2, to form an oxygen ion implanted layer 6 independently on &he nitrogen ion implanted layer 3.

As shown in FIG. 5C, a protective SiO.sub.2 layer 12 is formed on the surface of a surface residual silicon layer 4, thereafter annealing processing is performed in a nitrogen atmosphere at 1250.degree. C. for two hours. Thus, through the aforementioned steps shown in FIG. 5A to FIG. 5C, a buried dielectric layer, having two-layer structure of the buried SiO.sub.2 layer 6 and the buried Si.sub.3 N.sub.4 layer 3, is formed in the p type substrate 1.

Thereafter the SiO.sub.2 layer 12 on the surface residual silicon layer 4 is removed similarly to the manufacturing method shown in FIG. 2, and then antimony of high concentration is ion-implanted and diffused to n.sup.+ -typify the surface residual silicon layer 4 similarly to the step shown in FIG. 2C. Further, processing similar to that of the steps shown in FIG. 2D to FIG. 2K is performed to implement a semiconductor device having high breakdown voltage.

Now consider the breakdown voltage of the dielectric layer formed in the aforementioned manner to have two-layer structure of the buried SiO.sub.2 layer 6 and the buried Si.sub.3 N.sub.4 layer 3. Assuming that E.sub.SiO2 and E.sub.Si3N4 represent electric fields in these dielectric layers upon application of a voltage to these dielectric layers and t.sub.SiO2 and t.sub.Si3N4 represent thickness values thereof while V.sub.SiO2/Si3N4 represents the breakdown voltage of the dielectric layers, a relationship between these factors is as follows:

Further, assuming that .epsilon..sub.SiO2 and .epsilon..sub.Si3N4 represent relative permittivity values of these dielectric layers, the following relation is obtained from continuity of dielectric flux density:

The expression (2) is transformed and is substituted in the expression (1) to obtain the following expression: ##EQU1##

In this embodiment, the critical field of E.sub.SiO2 is 10 MV/ m, thickness values t.sub.Si3N4 and t.sub.SiO2 are 0.4 .mu.m and 0.5 .mu.m, respectively, and the relative permittivity values .epsilon..sub.SiO2 and .epsilon..sub.Si3N4 are 3.9 and 7.4, respectively. Therefore, the breakdown voltage V.sub.SiO2/Si3N4 of the dielectric layers becomes 710 V by substituting these values in the expression (3). Namely, a dielectric breakdown voltage is increased by about 50% by virtue of nitrogen ion implantation.

Although nitrogen ions and oxygen ions are implanted under implantation voltage levels of 400 keV and 150 keV, respectively, in the above embodiment, the point is that implantation voltage levels may be set so that the buried SiO.sub.2 layer 6 and the buried Si.sub.3 N.sub.4 layer 3 formed by these ions upon implantation are independent of each other, in other words, are not overlapped. However, since the buried SiO.sub.2 layer 6 is superior in insulability to the buried Si.sub.3 N.sub.4 layer 3 in the ion implantation method, the buried SiO.sub.2 layer 6 is preferably formed in a region shallower than the buried Si.sub.3 N.sub.4 layer 3, in order to maintain effective insulation from an element region formed on these layers 3 and 6.

Further, although nitrogen ions and oxygen ions are implanted by 1.5.times.10.sup.18 cm.sup.-2 and 2.3.times.10.sup.18 cm.sup.-2, respectively, in the above embodiment, the present invention is not restricted to these values but the amounts of implantation of nitrogen ions and oxygen ions are preferably set at 5.times.10.sup.17 to 2.times.10.sup.18 cm.sup.-2 and 1.5.times.10.sup.18 to 2.6.times.10.sup.18 cm.sup.-2, respectively.

Although annealing processing is performed at a temperature of 1250.degree. C. in the above embodiment, such processing may be performed under another temperature level, preferably within a range of 1200.degree. to 1400.degree. C.

Although the present& invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.