Digital Switching Voltage Regulator

1. Field of the Invention:

The present invention relates to voltage regulators. More specifically, the present invention relates to digital switching voltage regulators.

While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.

2. Description of the Related Art:

Analog and digital switching voltage regulators are known in the art. In analog switching regulators the current shunted by a switch is proportional to the difference between an existing load voltage and a desired load voltage. The current shunting switch in analog regulators is typically a transistor operating in the linear mode. In certain applications the often high power consumption of analog regulators is reduced by "tapping" a power supply at less than the available supply voltage. In this manner the voltage across the transistor switch is reduced thereby reducing power consumption. However, this reduction in the transistor operating point voltage induces a corresponding reduction in the amount of power (V.sub.TAP * I) which may be shunted by the transistor prior to saturation thereof. Hence, the regulation range of the analog regulator is limited in proportion to this reduction in power handling capability.

In contrast, conventional digital regulators are not typically so limited in current or power handling capability. Conventional digital switching regulators effect regulation within adjacent voltage "windows" centered about voltage setpoints sequentially offset from the desired load voltage. These regulators include an array of modules each having a window comparator centered about one of the setpoints. Each module typically includes a power supply (e.g., a current source) and a current shunt switch controlled by the window comparator. The array of modules is then connected in parallel with a load.

This conventional digital approach is generally expensive to implement as each switch requires an associated window comparator. Further, the voltage setpoints about which the window comparators within each module are centered are typically provided by a central amplifier. Hence, failure of this central amplifier results in a complete loss of regulation capability. This risk may be unacceptable in applications such as spacecraft load (bus) voltage regulation which require a high degree of reliability.

An alternative digital switching regulator utilizing a shift register has recently been developed which overcomes the limitations mentioned above in connection with conventional digital switching regulators. Specifically, in an article entitled "10 kW Solar Array Switching Unit Performance Test Results", published in the Proceedings of the 20th Intersociety Energy Conversion Engineering Conference in 1985, Fleck et al. disclosed a `voltage controlled solar array`. The regulator developed by Fleck includes an array of solar panels (current sources) connected to an array of shunt switches. The solar panels and shunt switches are connected in parallel with a load. When turned on, a given shunt switch diverts to ground the current from the solar panel connected thereto. Individual data registers within a shift register are operatively coupled to the shunt switches. A logic one or zero within each of the data registers turns the associated switch on or off, respectively. A comparator monitors the load voltage and compares it with a desired reference voltage to generate a logic signal which is used to control the shift register and hence the shunt switches. Data within the shift register is updated in accordance with the logic signal in response to the application of a clock signal to the shift register. In this manner a relatively constant voltage is maintained across the load despite changes in the impedance or current requirements thereof.

In the regulator developed by Fleck, the array of switches is controlled by a shift register and a single comparator. This implementation is more economical than that of the conventional digital switching regulators which have a comparator associated with each switch.

However, in the regulator of Fleck both the clock signal and the logic signal generated by the comparator are continuously applied to the shift register. As a consequence, at least one bit within the shift register will change with each clock cycle even when the instantaneous bus voltage is substantially identical to the desired bus voltage. In this manner at least one switch changes state with every clock cycle even in the presence of a constant (steady state) bus current draw. This somewhat random switching results in an unpredictable, nonuniform ripple voltage and can increase power dissipation in the shunt switches.

Further, where the ability to accommodate large changes in bus current draw is desired, a number of the regulators developed by Fleck may need to be combined in parallel. However, since one switch within each regulator changes state with each clock pulse, approximately as many switches as the number of regulators combined in parallel changes state with each clock pulse. These essentially independent switch state changes may lead to unpredictable bus voltage transients in such a parallel arrangement of regulators.

In addition, when combined in parallel the regulators developed by Fleck would generally have staggered reference voltages (setpoints) so as not to mutually interfere. These setpoints should be located as close as possible to the setpoint associated with the desired bus voltage so as to minimize bus voltage variation. However, the setpoints also need to be adequately spaced to prevent the ripple voltages from regulators with adjacent reference voltages from interacting and possibly growing to unstable proportions. As mentioned above, the amplitude of the ripple voltage within the regulators of Fleck is not well defined. Hence, in a parallel connection of the regulators developed by Fleck the regulator setpoints may not be able to be positioned sufficiently near the desired bus voltage to reduce bus voltage variations to acceptable levels for certain applications.

Hence, a need in the art exists for a digital switching voltage regulator which provides a regulated voltage having a relatively small, well defined ripple component.

The need in the art for a digital switching voltage regulator which provides a regulated voltage having a relatively small, well defined ripple component is addressed by the improved digital switching voltage regulator of the present invention. The improved regulator of the present invention includes a control circuit for providing a first output voltage and at least one shift pulse when the voltage across a load operatively coupled to the regulator departs from a voltage regulation window by crossing an upper threshold voltage thereof. The control circuit also provides a second output voltage and at least one shift pulse when the load voltage departs from the voltage regulation window by crossing a lower threshold thereof. A bi-directional shift register generates a set of control voltages in response to the output voltage of the control circuit and the shift pulse. Current is provided to the load by an array of switchable current sources in response to the set of control voltages.

FIG. 1 is a block diagram representation of a preferred embodiment of the improved digital voltage regulator of the present invention.

FIG. 2 is a timing diagram which illustrates the steady state operation of the regulator of the present invention in response to a constant bus current I.sub.bus.

FIG. 3 is a timing diagram which illustrates the transient response of a preferred embodiment of the present invention in response to a step change in bus current I.sub.bus.

FIG. 4 is a timing diagram illustrating the response of a parallel connection of the regulators of the present invention to variations in current I.sub.bus drawn the by the bus 20.

FIG. 1 shows a block diagram representation of a preferred embodiment of the improved digital switching regulator 10 of the present invention. The improved regulator 10 is operative to maintain a substantially constant voltage on a bus (signal line) 20 in response to changes in the current (I.sub.bus) drawn by a bus load 21 connected thereto. In particular, a capacitor 22 within the regulator 10 compensates for immediate changes in I.sub.bus by absorbing or supplying a current I.sub.cap. The capacitor current I.sub.cap induces a change in the charge stored on the capacitor 22 and hence leads to a corresponding change in the voltage on the bus 20. The regulator 10 of the present invention senses variations in the voltage on the bus 20 and adjusts the regulator current I.sub.reg to the load 21 and capacitor 22 accordingly. In this manner the voltage across the capacitor 22, and therefore on the bus 20, is held relatively constant notwithstanding variations in I.sub.bus.

Although the present invention will be described in more detail below, the following brief operational description is included to enhance understanding of the remainder of the specification. As shown in FIG. 1, the regulator 10 of the present invention includes a control circuit 25 which is responsive to deviations in the voltage on the bus 20 from a desired voltage regulation range. More specifically, the control circuit 25 includes a window comparator 30 and a controllable pulse generator 40. The comparator 30 compares a portion of the voltage on the bus 20 with a voltage provided by a diode 41. When the difference between this bus voltage sample and the reference voltage exceeds a differential voltage the output voltage of the comparator 30 changes accordingly. Specifically, the comparator 30 raises the lines 32 and 34 to a logic 1 for bus voltages below and above, respectively, the desired bus voltage regulation range.

When the line 32 (34) is raised, a logic 1 (0) is transferred into a bi-directional shift register 50. Following this transfer, a shift pulse generated by the pulse generator 40 is applied to the register 50. Application of this pulse results in transistor switches within a switch array 60 being turned on or off in accordance with data stored in the register 50. When turned on, switches Q1, Q2, Q3 and Q4 shunt current from current sources S1, S2, S3 and S4 included within a current source array 70 away from the bus 20 and load 21. Thus, the current output of the regulator 10 is varied in response to changes in the voltage on the bus 20. In this manner the regulator 10 regulates the voltage on the bus 20 by adjusting the current I.sub.reg such that the voltage across the capacitor 22 remains relatively constant despite changes in I.sub.bus.

As shown in FIG. 1, the voltage drop across a zener diode 41 provides the comparator 30 with a reference voltage. The reference may be provided by a single element or a plurality of same. For example, with a nominal bus voltage of 30 V the diode 41 typically generates a 19.2 V reference voltage. The 19.2 V reference voltage is realized by a serial connection of three 6.4 V temperature compensated reference Zener diodes. Diodes meeting the above requirements may be obtained from a manufacturer such as Motorola under the part number IN4569A.

In the embodiment of FIG. 1 the voltage on the bus 20 is divided by the resistors R1, R2 and R3 and sampled by the comparator 30 via input lines 33 and 35. As the voltage dropped across R2 is equivalent to the voltage difference between the lines 33 and 35, the magnitude of the voltage drop across R2 defines the differential voltage applied to the comparator 30. The magnitude of this differential voltage is determined by the bus voltage and the value of R2 relative to R1 and R3. The value of resistor R1 is chosen such that this differential input voltage is centered at the voltage provided by the reference 41. Changes in the voltage of the bus 20 induce corresponding changes in the voltages on the lines 33 and 35 relative to the reference voltage. In this manner the resistors R1, R2 and R3 are chosen to allow the comparator 30 to sense changes in the bus voltage relative to the voltage generated by the reference 41.

The comparator 30 is utilized to signal departures in the bus voltage from a desired bus voltage regulation window. The window is bounded by upper and lower threshold voltages. In particular, the output voltage of the comparator 30 changes when the bus voltage departs from the regulation window by crossing the upper or lower threshold voltage thereof. Specifically, the comparator 30 raises the line 32 or the line 34 to a logic 1 when the line 33 falls below, or the line 35 rises above, respectively, the reference voltage by the differential threshold voltage of the comparator 30. In the embodiment of FIG. 1 this differential voltage is approximately 100 mV. The value of R2 relative to R1 and R3 determines the degree of bus voltage variation from the desired bus voltage (i.e. the span of the regulation window) which will induce such a 100 mV comparator input voltage. Hence, the resistors R1, R2, and R3 determine the upper and lower threshold voltages of a voltage regulation window monitored by the comparator 30. The comparator 30 may be realized by a variety of commercially available integrated circuit (IC) window comparators. The LM139 comparator manufactured by Fairchild is an example of one such IC comparator.

The controllable pulse generator 40 is operative to pulse the bi-directional shift register 50 in response to actuation by the comparator 30. In particular, the controllable pulse generator 40 includes a conventional CMOS 4001B OR gate 42 and a clocked pulse generator 44. The input of the OR gate 42 is coupled to the outputs of the comparator 30 via the lines 32 and 34. The OR gate 42 provides an enable signal to the clocked generator 44 in response to the presence of a logic 1 on either of the lines 32 or 34. When enabled by the enabling signal from the gate 42, the clocked generator 44 supplies a series of equally spaced pulses to the shift register 50. Those skilled in the art will appreciate that the clocked pulsed generator 44 may be realized with a conventional RC oscillator and a comparator.

In the embodiment of FIG. 1, the bi-directional shift register 50 includes four serially arranged data registers (not shown) which allow control of switches Q1, Q2, Q3, and Q4 included within the switch array 60. The shift register 50 is coupled to the lines 32 and 34 at input ports S1 and S2, respectively. As mentioned above, data is shifted between the registers included within the shift register 50 in response to the application of a logic 1 to line 32 or line 34. More specifically, as the voltage on the bus 20 increases beyond the bounds of a desired bus voltage window, a logic 1 will be applied to the lower line 34 and data will be shifted in the register 50 towards terminal T2. Concurrent with this data shift a logic 1 will be loaded into the register 50 at terminal T1. Similarly, bus voltage decreases of sufficient magnitude relative to a desired bus voltage trigger the comparator 30 apply a logic 1 to the upper line 32 and thereby induce data within the register 50 to be serially shifted towards the terminal T1. Further, a logic 0 is loaded into the register 50 at the terminal T2 as data is shifted toward terminal T1. Hence, data is shifted within the register 50 in response to bus voltage fluctuations which exceed a voltage regulation window. Various commercially available 4 bit bi-directional shift registers such as the CD40194 manufactured by National Semiconductor may be utilized to serve as the register 50.

As shown in FIG. 1, the register 50 may also be addressed by the controllable pulse generator 40 via input port Cl. Pulses received by the register 50 at the port Cl enable the switches Q1, Q2, Q3 and Q4 to access data stored within the register 50. As mentioned above, the pulse generator 40 provides a pulse to the register 50 in response to either of the lines 32 or 34 being raised to a logic 1. In this manner the switch register 50 allows the switches Q1, Q2, Q3 and Q4 to have access to data stored therein, and hence to potentially change state, only after the line 32 or 34 has been raised. The net effect is that the register 50 allows the switches Q1, Q2, Q3 and Q4 to change states from on or off only after the voltage on the bus 20 has departed from the bus voltage regulation window defined by the comparator 30. This selective control of the switch array 60 is in marked contrast to the system developed by Fleck mentioned in the Background of the Invention wherein a pulse train is continuously applied to a shift register irrespective of the instantaneous bus voltage. This causes at least one switch connected to the shift register to change state with every pulse, thereby generating a nonperiodic bus ripple voltage of potentially increased magnitude.

The switches Q1, Q2, Q3 and Q4 included within the switch array 60 are controlled by the shift register 50 and fed by power supplies S1, S2, S3 and S4, respectively. In the embodiment of FIG. 1 the switches Q1, Q2, Q3 and Q4 comprise field effect transistors (FETs). Commercially available FETs such as the IRF 150 FET (40 amp, 100 volt) manufactured by International Rectifier or bipolar transistors of similar voltage and current ratings afford adequate current handling capability and low saturation drop to minimize shunt switch power dissipation. As may be evident upon inspection of FIG. 1, each of the switches Q1, Q2, Q3 and Q4 is controlled by one of the four data registers included within the shift register 50. That is, the presence of a logic 1 (0) within a particular data register induces the switch within the array 60 coupled thereto to be turned on (off). In this manner current from the power supplies S1, S2, S3 and S4 is either shunted to ground by the switches Q1, Q2, Q3 and Q4 or fed to the load 21 in response to data stored within the register 50.

As shown in FIG. 1 the current sources S1, S2, S3 and S4 included within the array 70 are connected to the load 21 through the diodes CR1, CR2, CR3 and CR4. The current sources S1, S2, S3 and S4 are of conventional design and are chosen to provide current sufficient to satisfy the expected variation in I.sub.bus. For example, in spacecraft applications the current source array 70 may be realized by a photovoltaic solar panel array large enough to accommodate the current requirements of devices in communication with the spacecraft bus. In operation, the number of current sources in the array 70 furnishing I.sub.reg at any instant is determined by the number of switches in the switch array 60 turned off. Hence, the current source array 70 provides a controllable source of current for the bus load 21.

The diodes CR1, CR2, CR3 and CR4 prevent the voltage across the switches Q1, Q2, Q3 and Q4 from being impressed upon the load 21 while the switches Q1, Q2, Q3 and Q4 are conducting current. That is, while one of the switches within the array 60 is shunting current from one of the supplies within the array 70, the diode CR1, CR2, CR3 or CR4 connected to the particular switch and supply drops substantially all of the voltage present across the load 21. Conversely, while the load 21 and bus 20 are being provided current by one of the supplies S1, S2, S3 or S4, the voltage drop across the diode CR1, CR2, CR3 or CR4 coupled to this supply is approximately 0.7 volts. In this manner the diodes CR1, CR2, CR3 and CR4 buffer the load 21 from the switch array 60 and current source array 70.

The load 21 includes a resistive load R, a constant current load Z.sub.i and a constant power load Z.sub.p. The loads R, Z.sub.i and Z.sub.p model the three types of loads likely to be connected to the bus 20. The loads R, Z.sub.i and Z.sub.p each behave differently with respect to changes in the voltage on the bus 20. For example, a decrease in bus voltage induces a decrease in the current drawn by the load R, does not affect the current drawn by the load Z.sub.i, and causes an increase in the current drawn by the load Z.sub.p. The bus current I.sub.bus may be altered by the electrical connection or disconnection to the bus 20 of devices having any of the three loading characteristics described above. Although the timing diagrams discussed below are described with reference to changes in the current drawn by the load Z.sub.i, it is understood the regulator 10 of the present invention is disposed to regulate the voltage on the bus 20 equally well with respect to changes in the resistance of the load R or in the power consumption of the load Z.sub.p.

FIG. 2 is a timing diagram which shows the steady state response of the regulator 10 to a constant bus current load. As shown in FIG. 2, the voltage on the bus 20 varies periodically within a desired bus voltage window defined by the upper and lower bus threshold voltages V.sub.max and V.sub.min. The voltages V.sub.usp and V.sub.lsp are the bus voltages at which the comparator 30 is triggered to raise the lines 32 and 34 to a logic 1, respectively. As discussed above, the voltages V.sub.usp and V.sub.lsp can be adjusted with the resistors R1, R2 and R3.

While the regulator 10 is operating in the steady state, three of the four switches Q1, Q2, Q3 and Q4 will typically remain on or off until a change occurs in I.sub.bus. The number of switches in the switch array 60 turned on or off in the steady state depends in the steady state value of the desired, preselected voltage on the bus 20 and on the particular steady state current I.sub.bus. For relatively larger (smaller) steady state bus currents I.sub.bus, the array 60 will include proportionately more switches turned permanently off (on) pending a change in I.sub.bus. Further, the remaining fourth switch in the array 60 (denoted by Qn in FIG. 2) will turn on and off as the bus voltage reaches V.sub.max and V.sub.min, respectively. The maximum frequency of the steady state ripple voltage on the bus 20, and therefore one half of the maximum switching frequency of Qn, is given by the expression:

where,

f.sub.max =maximum ripple voltage frequency

C=capacitance of the capacitor 22

V.sub.max =upper bound of bus voltage window

V.sub.min =lower bound of bus voltage window

Isn=current to the load 21 and capacitor 22 from supply (S1, S2, S3 or S4) coupled to Qn

Resr=equivalent series resistance of the capacitor 22.

As shown in FIG. 2, the OR gate 42 sends a pulse enable signal to the pulse generator 44 in response to the application of a logic 1 to either the upper line 32 or the lower line 34. Data within the register 50 is serially shifted concurrent with the generation of the pulse enable signal. The pulse generator 44 delivers a pulse to the shift register 50 after some time delay (nominally 5 microseconds in the preferred embodiment) after receiving the pulse enable signal. The time delay is built into the pulse generator 44 to allow information within the register 50 to settle after being serially shifted. As is evident from FIG. 2, Qn changes state immediately after the register 50 is pulsed by the generator 44. Accordingly, the current Isn to the load from the supply coupled to Qn either turns on or off depending on the state change of Qn. In short, while in the steady state, the regulator 10 supplies current to the load 21 until the voltage on the bus approaches V.sub.max. This current is then reduced by turning on Qn which allows discharge of the capacitor 22 and results in the voltage on the bus 20 dropping to near V.sub.min. Current is then again increased to the load 21 by turning off Qn. In this manner Qn is switched at a rate necessary to constrain the bus voltage to remain within V.sub.max and V.sub.min, thereby providing a periodic and predictable bus ripple voltage.

As should be obvious from the above, the frequency of the bus ripple voltage is related to the value of the capacitor 22. In a preferred embodiment of the regulator 10 having a nominal bus voltage of 30 V, the capacitor 22 is chosen to be on the order of 3000 mF.

FIG. 3 is a timing diagram which illustrates the transient response of a modified version of the system 10 to a three unit step increase in the current drawn by the load Z.sub.i which induces a three unit step increase in I.sub.bus. The response in FIG. 3 corresponds to a modified version of the system 10 wherein the 4 bit register 50 has been replaced by a 5 bit bi-directional shift register 50'. Additionally a fifth transistor switch Q5, current source S5 and diode CR5 have been added in a parallel connection substantially identical to the respective connections of the elements Q1, Q2, Q3 and Q4; S1, S2, S3 and S4; and CR1, CR2, CR3 and CR4. A three unit step current increase corresponds to the maximum current available from three of the supplies in the current source array 70.

As shown in FIG. 3, the voltage on the bus 20 instantaneously drops below V.sub.lsp following the step increase in I.sub.bus and the associated discharge of current from the capacitor 22 through the equivalent series resistance thereof. This drop in bus voltage causes the line 32 (FIG. 2) to be raised and hence results in a logic 0 being loaded into the register 50'. The presence of a logic 1 on the line 32 concurrently induces the OR gate 42 to impress a pulse enable signal on the pulse generator 44. The pulse generator then provides a first pulse to the register 50' which allows the logic 0 loaded previously to turn off the switch Q1. As shown in FIG. 3, the drain to source voltage of Q1 increases upon being turned off. As the increased current provided to the load 21 by S1 following the turning off of Q1 is insufficient to raise the voltage on the bus 20 above V.sub.lsp, the line 32 and the pulse enable signal remain high which induces an additional logic 0 to be loaded into the register 50' and a second pulse to be applied to the register 50'. As shown in FIG. 3 this process continues until I.sub.reg becomes adequate to raise the bus voltage above V.sub.usp. When the bus voltage exceeds V.sub.usp the line 34 is raised, a logic 1 is loaded into register 50', and Q5 is turned on following pulsing of the register 50' by the generator 44. After Q5 is turned on, the regulator 10 proceeds to operate in the steady state mode illustrated in FIG. 2. In this manner the regulator 10 efficiently returns to steady state operation following relatively large changes in the bus current I.sub.bus.

As is implied by FIG. 3, the frequency of the pulse train provided by the generator 44 is proportional to the rate at which the bus voltage returns to the desired regulation range. It is also seen in FIGS. 2 and 3 that the steady state bus ripple voltage is independent of the frequency of the pulse generator 44. It is therefore a feature of the present invention that the frequency of the pulse generator may be selected to optimize the transient response of the regulator 10 without affecting the steady state bus ripple voltage. In contrast, as mentioned in the Background of the Invention other digital switching regulators utilize a clock which regularly pulses a shift register irrespective the value of an instantaneous bus voltage. Hence, in these regulators the frequency of the steady state bus ripple voltage is essentially equivalent to the clock frequency. This substantially prevents separate optimization of the clock frequency for transient and steady state response.

In certain applications wherein the bus current I.sub.bus is subject to substantial variation, several of the regulators 10 of the present invention may need to be connected in parallel to the load 21. That is, the current sourcing capacity of a single regulator 10 may be inadequate to provide a large bus current I.sub.bus while simultaneously providing the requisite capacitor current I.sub.cap necessary to sufficiently charge the capacitor 22 to the desired bus voltage. As an example of such a parallel connection, FIG. 4 shows the response of a parallel connection of three of the regulators 10 of FIG. 1 to a widely varying bus current I.sub.bus. These three regulators will be referred to as a first, second and third regulator 100, 101 and 102, respectively. As shown in FIG. 4, the voltage regulation windows of the first, second and third parallel connected regulators 100, 101 and 102 are denoted by V.sub.spi -V.sub.lspi where i=1, 2 and 3, respectively. The individual bus voltage regulation windows are offset so as to avoid mutual interference between the first, second and third regulators 100, 101 and 102. As was mentioned previously, the DC offset and span of the regulation windows may be selected by adjusting the resistors R1, R2 and R3 included within each of the regulators 100, 101 and 102. As is evident from FIG. 4, the composite regulation window of the parallel connection of the first, second and third regulators 100, 101 and 102 approximately corresponds to V.sub.uspl -V.sub.lsp4.

Specifically, FIG. 4 shows the variation in voltage on the bus 20 in response to a gradual unit ramp increase in I.sub.bus followed by a five unit step increase in I.sub.bus. Again, in this example the increase in I.sub.bus is due to an increase in the current drawn by the load Z.sub.i. Further, a unit increase in I.sub.bus is equivalent to the current available from a single current source within the current source array 70 (FIG. 1). Also shown in FIG. 4 are the drain to source voltages of transistor switches Q1 through Q12, a high drain to source voltage indicating that the switch is turned off. Switches Q1 through Q4 are included within the first regulator 100, switches Q5 through Q8 are included within the second regulator 101 and switches Q9 through Q12 are included within the third regulator 102.

In the diagram of FIG. 4 I.sub.bus is initially held constant at 3.5 units and the bus voltage varies in a steady state manner between V.sub.uspl and V.sub.lspl. In this initial state Q1 through Q3 are off allowing three units of current to be supplied by sources S1 through S3. The remaining one half unit of I.sub.bus and the requisite I.sub.cap are supplied by S4 when Q4 is periodically turned off. Q5 through Q12 are initially turned on thereby shunting to ground current from the current sources associated therewith. As I.sub.bus is gradually increased to 4.5 units, Q4 is held in the off state and Q5 is intermittently turned off to supply additional current to the bus 20. Hence, the increase in I.sub.bus to 4.5 units has resulted in instantaneous control of the bus voltage being transferred from the first regulator 100 to the second regulator 101.

Upon the bus current draw increasing 5 units to 9.5 units, the bus voltage exhibits a transient response similar to that of FIG. 3. Specifically, switches Q5 through Q9 are sequentially turned off allowing 5 additional units of current to flow to the bus 20. Q10 then toggles between states to supply the remaining portion of I.sub.bus and the I.sub.cap required by the capacitor 22 to constrain the bus voltage to remain between V.sub.usp4 and V.sub.lsp4. Thus, the five unit step increase in I.sub.bus results in control of the ensuing steady state bus voltage passing from the second regulator 101 to the third regulator 102. In this manner preferred embodiments 100, 101 and 102 of the regulator of the present invention may be arranged in parallel to increase the range of current which may be drawn by the bus 20. It is a feature of the present invention that the well defined steady state bus ripple voltages of the regulators 100, 101 and 102 allow the respective regulation windows associated therewith to be offset in close proximity. This allows the magnitude of the composite regulation window (V.sub.uspl -V.sub.lsp4) to be reduced relative to prior regulators, thereby achieving improved voltage regulation.

Thus the present invention has been described with reference to particular embodiments in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof. For example, the control circuit 25 may include electronics other than that included within controllable pulse generator 40 for selectively pulsing the shift register 50. Similarly, the invention is not limited to the particular embodiments of the window comparator 30 or switch array 60 disclosed herein. Those skilled in the art may utilize other circuits for sensing deviations in the bus voltage from a preselected voltage regulation window which may be suitable for a particular embodiment of the present invention. Additionally, shift registers of orders other than four may be substituted for the shift register 50 without departing from the scope of the present invention. It is therefore contemplated by the appended claims to cover any and all such modifications.

Accordingly,