US 4,945,517 AGrant
Dynamic Random Access Memory
Issue Date:1990-07-31
•1 Claims
•4 Drawing Sheets
Abstract
A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.
Metadata
Assignee
- Mitsubishi Denki Kabushiki Kaisha
Inventors
- Hideshi Miyatake
- Masaki Kumanoya
- Hideto Hidaka
- Hiroyuki Yamasaki
- Konishi Yasuhiro
- Yuto Ikeda
Application Information
Application Number:US 1842560
Filing Date:1988-04-21
Priority Date:1987-05-13
Art Unit:233
Classifications
IPC:
G11C 700G11C 800
Field of Search:
365230;233;189;203;189.05;189.01;230.08;230.01;233.5;238.5
Patent Drawings (4 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a dynamic random access memory (referred to hereinafter as dynamic RAM) and particularly to a dynamic RAM capable of performing static operation in columns to fulfill a quick access function.
2. Description of the Prior Art
Most of dynamic RAMs of these days have a quick access function such as a fast page mode or a static column mode in which a cycle time can be decreased to suitably perform high-speed processing required in a memory for image processing or the like. In order to realize such a high-speed mode, a conventional dynamic RAM has columns comprising a static circuit as in a static RAM which does not need to be precharged. In such a conventional dynamic RAM, an input/output (referred to hereinafter as I/O) line for inputting and outputting data is constantly pulled up at a predetermined DC potential through an I/O load. However, if the I/O line is constantly pulled up at the DC potential, the potential on the I/O line can not immediately be lowered because of the existence of the I/O load when data "0" is to be written, and thus it takes time to write data. Therefore, a structure for preventing the above described disadvantage is adopted, in which the I/O load is rendered inactive during a writing cycle so as to be disconnected from a DC power supply (refer to Japanese Patent Laying-Open Gazette No. 60-179993 or IEEE J. Solid-State Circuits, vol. SC-20, pp. 894-902, Oct. 1985).
FIG. 1 is a circuit diagram showing a main part of a conventional dynamic RAM in which the above described structure is adopted. In FIG. 1, a dynamic RAM comprises a sense amplifier 1, a memory cell 2, a write buffer circuit 3, a row decoder 4a, a column decoder 4b, an I/O load 5, a pair of bit lines 6 and 7, a pair of I/O lines 8 and 9, MOS transistors 10 and 11 for switching between the pair of bit lines 6 and 7 and the pair of I/O lines 8 and 9, MOS transistors 12 and 13 constituting the I/O load 5, and a word line 15.
Operation in a writing cycle of the dynamic RAM of FIG. 1 will be described by taking the fast page mode as an example.
As shown in a timing chart of FIG. 2, writing operation is enabled when a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal R/W applied from a CPU are all at a low level.
First, when the row address strobe signal RAS changes to the low level, a row address is selected by the row decoder 4a and a word line 15 corresponding thereto attains a high level. When data appears to a given extent from the memory cell 2 connected to the word line 15 as a potential difference between the bit lines 6 and 7, the sense amplifier 1 is activated whereby one of the potentials of the bit lines 6 and 7 is amplified to a source potential Vcc and the other is set to a ground potential GND. Subsequently, when the column address strobe signal CAS changes to the low level, the column decoder 4b is activated and a selected output Yi of the column decoder 4b attains the high level. As a result, gates of the MOS transistors 10 and 11 are opened, whereby the pair of bit lines 6 and 7 are connected with the pair of I/O lines 8 and 9. Thus, even in the writing cycle, the same operation as in a reading cycle is effected at an early stage of the writing cycle. In this state, data is written forcedly into the memory cell 2. Subsequently, the following operation is performed.
When the write enable signal R/W is turned to the low level, a read/write indicating signal W is turned to the low level in the dynamic RAM. The signal W is commonly applied to gates of the MOS transistors 12 and 13 of the I/O load 5 and to the write buffer circuit 3. Accordingly, when the output of the signal W is turned to the low level, the I/O load 5 is rendered inactive, whereby the pair of I/O lines 8 and 10 are disconnected from the DC source. At the same time, the write buffer circuit 3 is activated. When write data D.sub.in is supplied to the write buffer 3, the write buffer circuit 3 sets one of the I/O lines 8 and 9 to a high level approximate to the source potential Vcc and sets the other to a low level equal to the ground potential GND, dependent on "0" or "1" of the data D.sub.in. Those potential levels are transmitted to the pair of bit lines 6 and 7 through the pair of I/O lines 8 and 9. On that occasion, if the write data is different from the data already stored in the memory cell 2, that is, if data of "1" previously stored in the memory cell 2 is renewed and data of "0" is written therein for example, the potential level of the bit line 6 becomes slightly lower than that of the other bit line 7. As a result, the output level of the sense amplifier 1 is inverted, whereby the bit line 6 is set to the ground potential GND and the other bit line 7 is set to the source potential Vcc. Thus, writing of data into the memory cell 2 is completed.
In the dynamic RAM having the above described structure, one of the I/O lines 8 and 9 is set to the potential approximate to the source potential and the other is set to the ground potential in the data writing cycle, while in the data reading cycle, the output level of the sense amplifier 1 does not need to be inverted and the I/O lines 8 and 9 are set to almost the same potential. Accordingly, if one data writing cycle is completed for example, it is necessary to charge the I/O line of the low level to a predetermined potential (as indicated by V.sub.ct in FIG. 2) so that the dynamic RAM is prepared for the subsequent reading or writing cycle. However, the I/O lines 8 and 9 are connected with a number of pairs of bit lines 6 and 7 and the pair of I/O lines 8 and 9 have a large capacitance load accordingly the I/O line 8 or 9 cannot be instantly charged up to the predetermined potential by the capacity of the I/O load 5. Thus, a little time is required for the I/O line 8 or 9 to attain the predetermined voltage V.sub.ct.
In the fast page mode, a change of column addresses is permitted in a state in which the column address strobe signal CAS is at the high level, whereby a different column address can be selected. When the column address strobe signal CAS is at the high level, the read/write indicating signal W also attains the high level accordingly. As a result, the gates of the MOS transistors 12 and 13 of the I/O load 5 are opened and the I/O line 8 or 9 of the low level is charged. The charging takes a time t.sub.d because of the above described capacity of the I/O load 5.
A different column address is selected with the I/O line 8 or 9 being at a potential lower than V.sub.ct and if the potential on the bit line 6 or 7 corresponding to the newly selected column address is considerably different from the potential on the I/O line 8 or 9 (for example, if the I/O line 8 of the potential lower than V.sub.ct is coupled with the bit line 6 connected to the memory cell 2 in which "1" is stored), the pair of I/O lines 8 and 9 themselves function as a kind of a source because of the large capacitance load of the I/O lines 8 and 9. As a result, although the write data D.sub.in is not at all supplied to the write buffer 3, the output level of the sense amplifier 1 of the bit lines 6 and 7 is inverted. The inversion of the output level of the sense amplifier 1 causes erroneous writing of data in the memory cell 2. In the above described example, the data of "0" is erroneously written in the memory cell 2.
In order to prevent such errors, the column address cannot be changed during the period t.sub.d after the column address strobe signal CAS attains the high level until the potential of the I/O line 8 or 9 rises to the predetermined potential V.sub.ct and it is necessary to wait for a lapse of this period t.sub.d. Accordingly, a delay is caused in timing for permitting a change of the column address. In other words, there is caused a delay in access time of the column address.
In the static column mode, when the write enable signal R/W attains the high level, a change of the column address is permitted, but there is also caused a delay in access time of the column address for the same reason as described above.
Summary of the Invention
In view of the above described prior art, an object of the present invention is to provide a dynamic RAM in which a change of column address is permitted immediately after an end of a writing cycle and accordingly a column address can be accessed rapidly in a shorter period than that in a conventional dynamic RAM.
According to the present invention, a dynamic RAM comprises: a plurality of word lines; a plurality of bit lines intersecting with the word lines; a plurality of memory cells provided in intersections of the word lines and the bit lines; an addressing circuit for selecting a word line and a bit line intersecting a selected memory cell; I/O lines connected with the bit lines for reading and writing data from and into the memory cells; an I/O load connected between the I/O lines and a voltage source; a write buffer for providing the I/O lines with the write voltage for writing data into the memory cells; and a monostable multivibrator responsive to the leading edge of a pulse in a read/write indicating signal, for providing an effective read/write signal pulse having a shorter duration than that of the read/write indicating signal pulse, wherein the effective read/write signal pulse not only causes the I/O load to disconnect the I/O lines from the voltage source but also causes the write buffer to provide the write voltage through the I/O lines to the bit line selected by the addressing circuit and then the addressing circuit is not allowed to change the selection of the memory cells during the duration of the read/write indicating signal pulse.
In the dynamic RAM in accordance with the present invention, charging of the I/O lines is restarted before an end of a writing cycle and accordingly a time margin is allowed for a charging period of the I/O lines. Thus, the I/O lines have been already sufficiently charged at the end of the writing cycle and it becomes possible to change column address immediately after the end of the writing cycle, whereby a quick access function such as a fast page mode or the like can be efficiently performed.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a circuit diagram of a main part of a conventional dynamic RAM.
FIG. 2 is a timing chart for explaining operation of the dynamic RAM of FIG. 1.
FIG. 3 is a circuit diagram of a main part of a dynamic RAM according to an embodiment of the present invention.
FIG. 4 is a timing chart for explaining operation of the dynamic RAM of FIG. 3.
Description of the Preferred Embodiment
FIG. 3 is a circuit diagram showing a main part of a dynamic RAM according to an embodiment of the present invention. The dynamic RAM of FIG. 3 is similar to that of FIG. 1, except that a monostable multivibrator 16 is provided in the dynamic RAM of FIG. 3. In FIG. 3, the same reference characters as in FIG. 1 denote the corresponding portions.
A characteristic feature of this embodiment is as follows. The dynamic RAM is provided with the monostable multivibrator 16 which receives a read/write indicating signal W for indicating reading and writing data from and into the memory cell 2 and outputs an effective read/write signal We having a smaller pulse duration than that of the signal W in response to a down edge of the signal W as a trigger, so that the output signal We of the monostable multivibrator 16 is supplied as a control signal for rendering the I/O load 5 inactive.
Operation in a writing cycle of the dynamic RAM will be described by taking the fast page mode as an example, with reference to the flow chart of FIG. 4.
In the dynamic RAM of FIG. 3, operation including activation of the sense amplifier 1 to amplify the potential difference between the bit lines 6 and 7 and coupling of the pair of bit lines 6 and 7 and the pair of I/O lines 8 and 9 is performed in the same manner as in the case of the conventional dynamic RAM shown in FIG. 1. Therefore, detailed description thereof is omitted.
When the write enable signal R/W from the CPU is turned to the low level, the read/write indicating signal W in the dynamic RAM is turned to the low level in response thereto. At a down edge of the signal W as a trigger, the monostable multivibrator 16 outputs the effective read/write signal We having a smaller pulse duration than that of the read/write indicating signal W. Since the effective read/write signal We is supplied commonly to the gates of the MOS transistors 12 and 13 of the I/O load 5 and to the write buffer 3, the I/O load 5 is rendered inactive only during a period in which the signal We is maintained at the low level. Thus, the pair of I/O lines 8 and 9 are disconnected from the DC source and the write buffer 3 is activated. At that time, if write data D.sub.in is supplied to the write buffer 3, the write buffer 3 sets one of the I/O lines 8 and 9 to a high level near the source potential Vcc and sets the other to a low level equal to the ground potential GND, dependent on "0" or "1" of the data D.sub.in. As a result, writing of the data in the memory cell 2 is completed.
Since a pulse duration P.sub.0 of the effective read/write signal We is shorter than a pulse duration P.sub.1 of the read/write indicating signal W, the signal We is immediately returned to the high level after writing of data is executed. Consequently, the I/O load 5 is activated and the I/O line 8 or 9 starts to be charged (at time t.sub.0 in FIG. 4). Accordingly, when the column address strobe signal CAS attains the high level (at time t.sub.1 in FIG. 4), that is, when a writing cycle is completed, column address can be changed immediately after the end of the writing cycle since the I/O line 8 or 9 is already sufficiently charged at a predetermined potential level V.sub.ct.
Although the fast page mode of the present embodiment was described, the present invention is also applicable to other modes for performing the quick access function, such as a static column mode or a nibble mode.
In addition, although the columns in the present invention were described as being formed by N channel MOS transistors, they may be formed by P channel MOS transistors.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims
What is claimed is:
1. In a dynamic RAM device including: a plurality of word lines (15); a plurality of bit lines (6, 7) intersecting with said word lines; a plurality of memory cells (2) provided in intersections of said word lines and said bit lines; addressing means (4a, 4b) for selecting a word line and a bit line intersecting a selected memory cell; I/O means (8, 9) connected with said bit lines for reading and writing data from and into said memory cells; I/O load means (5) connected between said I/O means and a voltage source; write means (3) for providing said I/O means with write voltage for writing data into said memory cells; and means for rendering said I/O load means active during a write operation of a fast page mode of operation after a time period shorter than a pulse in a read/write indicating signal (W) pulse in a W operation, thereby to permit a change of column address immediately after an end of a writing cycle, comprising: charge restart means for restarting charge of said I/O means before the end of the writing cycle, said charge restart means including monostable multivibrator means (16) responsive to the leading edge of said pulse of said read/write indicating signal (W), for providing an effective read/write signal pulse (We) having a shorter duration than that of the read/write indicating signal pulse (W); said write means operable in response to termination of said shorter duration We pulse to begin application of a write voltage to said I/O means, thereby providing to said I/O means a high voltage by the time a write operation is completed to permit a column address to change immediately upon attainment of a high level by a column address signal at the end of a write cycle.
Patent Citations (10)
Non-Patent Literature (3)
- IEEE J. Sol. St. Circuits: "A 1-Mbit CMOS Dynamic RAM with a Divided Bitline Matrix Architecture", by R. Taylor, vol. SC-20, No. 5, Oct. 1985, pp. 894-902.
- Integrated JFET/IGFET Memory Cell; Penoyer; IBM Tech. Discl. Bull.; vol. 27, No. 6; Nov. 1984.
- IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, S. 929-933.