Semiconductor Device Having Darlington Transistors

FIG. 1(a) is a front view of the first embodiment of the present invention,

FIG. 1(b) is a sectional view of a Darlington transistor shown in FIG. 1(a),

FIG. 2 is an equivalent circuit of a conventional current limit semiconductor device,

FIG. 3 is a graphical representation indicating collector current versus collector-emitter voltages for a description of the current limit effect of the device shown in FIG. 2,

FIG. 4 is a front view of one example of a semiconductor device corresponding to the circuit of FIG. 2,

FIG. 5 is a sectional view showing another example of the conventional semiconductor device corresponding to the circuit of FIG. 2,

FIGS. 6(a) and 6(b) show still another example of the conventional semiconductor device, in which FIG. 6(a) is a sectional view of a diode chip used in the semiconductor device, and FIG. 6(b) is a sectional view of the semiconductor device,

FIG. 7 is an equivalent circuit diagram of the first embodiment of the invention shown in FIG. 1,

FIG. 8 is a sectional view showing a second embodiment of the invention,

FIG. 9 is a sectional view showing a Darlington transistor employed in a third embodiment of the invention,

FIG. 10 is a graphical representation indicating the base-emitter input characteristic of the Darlington transistor shown in FIG. 9,

FIG. 11 is also a graphical representation indicating collector current versus collector-emitter voltage in the embodiment using the Darlington transistor shown in FIG. 9, and

FIG. 12 is an equivalent circuit diagram of a fourth embodiment of the invention.

A first embodiment of this invention is as shown in FIGS. 1(a) and 1(b), in which parts corresponding functionally to those which have been already described with reference to FIGS. 4, 5 and 6 are designated by the same reference numerals or characters.

As shown in FIG. 1(a), an NPN type transistor 1 is secured through a copper plate 3 to a ceramic plate 2 formed on a copper substrate 30. The base electrode 11 and the emitter electrode 12 of the transistor 1 are connected through lead wires 4 to a base terminal conductor 51 and an emitter terminal conductor 52, respectively. Furthermore, according to the invention, an NPN Darlington transistor 8 is secured through a copper plate 3 to the insulating substrate 2. FIG. 1(b) shows the structure of the Darlington transistor 8, which is similar to that of the chip 6 shown in FIG. 6. The structure will be described in more detail. Two P-type layers (regions) 64 are formed in one N-type semiconductor pellet 63, and an N-type layer 65 is formed in each of the P-type layers 64. One of the P-type layers 64 is connected to the N-type layer 65 in the other P-type layer 64 with a conductor 7 laid between openings of an oxide film 66. A base electrode 81 is formed on the other P-type layer 64, and an emitter electrode 82 is formed on the N-type layer 65 in the one P-type layer 64. A collector electrode 83 is formed on the lower surface of the pellet 63.

The base electrode 81 of the Darlington transistor 8 is short-circuited through the copper plate 3 to the collector electrode 83 and is connected through a lead wire 4 to the base terminal conductor 51. The emitter electrode 82 of the Darlington transistor 8 is connected through a lead wire 4 to the emitter terminal conductor 52. Therefore, an equivalent circuit of the semiconductor device thus constructed is as shown in FIG. 7, in which the circuit elements are designated by the same reference numerals as those in FIG. 1. A current I.sub.2 flowing into the base electrode 81 of the Darlington transistor 8 is I.sub.1 /.beta. (where .beta. is the current amplification factor), and the sum of the forward voltages of the two base-emitter junctions is therefore smaller than that provided by I.sub.1. That is, the dynamic resistance is decreased, and the forward voltage variation against the base current variation is also decreased, as a result of which the limit value variation of the collector current I.sub.C is also reduced.

FIG. 8 shows a second embodiment of the invention. In the second embodiment, the Darlington transistor 8 is fixedly mounted on the base terminal conductor 51 to which the base electrode 11 of the transistor 1 is connected. The base terminal conductor 51 is extended out of the module capsule to form an external terminal 53. Owing to this structure, the copper plate 3 provided under the Darlington transistor in FIG. 1 can be eliminated, the area of the module can be decreased, and the number of lead wires 4 can be reduced to three (from five in the first embodiment) in the second embodiment.

FIG. 9 shows a Darlington transistor 8 in a third embodiment of the invention. In this case, an electrode 84 is provided on the base region 64 of the front stage transistor (at the right side of FIG. 9) near the base region 64 of the rear stage transistor (at the left side of FIG. 9). The electrode 84 is connected to the base electrode 81 of the Darlington transistor 8 so that it is equal in potential to the base electrode. The width .beta. of the part of an N-type layer 63 which is located between the base regions 64 of the front and rear transistors, namely, a common collector region is made small. Thus, the P-type layer of the base region 64 of the front stage transistor to which the base electrode 84 is connected, the N-type layer 63 of the common collector region, the P-type layer of the base region 64 of the rear stage transistor, and the N-type layer of the emitter region 65 of the rear stage transistor to which the emitter electrode 82 is connected, provide a PNPN thyristor effect. That is, the Darlington transistor has two transistors arranged vertically and one thyristor arranged horizontally. Its base-emitter input characteristic curve is as indicated by the solid line 9 in FIG. 10. That is, although having a threshold voltage, because of the thyristor effect, the base-emitter voltage V.sub.BE is abruptly decreased due to the flow of a small base current. Accordingly, the output characteristic of the transistor 1 is as indicated by the solid line 33 in FIG. 11; that is, after detection of an overcurrent, the limit value against the collector current I.sub.C is smaller than the over-current detection value, and therefore the transistor 1 can withstand a higher overcurrent than that in the abovedescribed embodiments.

FIG. 12 is an equivalent circuit of a fourth embodiment of the invention. In this embodiment, the main transistor is a two-stage Darlington transistor 25, and a three-stage Darlington transistor 26 is connected between the base and the emitter of the main transistor 25. The current control effect is substantially similar to that of the above-described embodiments.

In FIG. 1(b), the front stage transistor and the output stage transistor of the Darlington transistor are shown equal in size. However, the Darlington transistor may be so designed that the final stage transistor is largest in size, and the transistors of the remaining stages are decreased in size in proportion to the reciprocal of the current amplification factor. This becomes more effective as the number of stages in the Darlington transistor to be inserted becomes larger.

In the semiconductor device of the invention, instead of the series-connected diodes connected between the base and the emitter of a transistor for limiting the collector current of the transistor, the Darlington transistor in the form of a chip, the number of stages of which is larger at least by one than the number of base-emitter junctions of the transistor, is mounted on the substrate on which the transistor is provided. Therefore, the semiconductor device of the invention is compact in structure, and is small in the variation of the current limit value due to the base current variation.