Static Power Conversion Apparatus Using a High Frequency Series Resonant DC Link

This invention pertains generally to the field of static power converters and systems for the control of static power converters.

In the past few years remarkable progress has been made in the development of high power density AC/DC converters using resonant-link schemes which utilize high speed devices such as fast recovery transistors and GTO's. These new converters not only have high power density but also possess very low switching losses because switching of the devices takes place at zero-voltage instants and thus the total system is able to operate at very high frequency compared to conventional DC link transistorized converters. Although these resonant-link converters are intended to operate at high power density, almost all the systems require self commutated switching devices and have some difficulty performing conversion at very high power levels because of the relatively low voltage and current margins that self commutated devices, such as transistors, typically have.

In general, switching schemes for resonant converters can be classified according to their resonant AC-link and resonant DC-link modes. The resonant AC circuits utilize either a parallel resonant circuit (FIG. 1) or a series resonant circuit (FIG. 2). The AC resonant circuit impresses both polarities of AC voltage and current on the link so that the switches of the input and output side converters are required to carry both positive and negative currents as well as block both polarities of voltage. The converter switches must therefore be bi-directional switches which are usually realized by two inverse-parallel transistors or thyristors for the parallel and series resonance circuits, respectively.

DC-link circuits have been developed which realize pulsating DC currents in the link by adding DC offsets to the AC resonant current. The resonant DC-link converters reported in the past have been parallel resonant types, as shown in FIG. 3. See also, U.S. Pat. No. 4,730,242 to Divan, which discloses parallel resonant link converter systems wherein the switching devices are switched at times of zero voltage to minimize switching losses.

A power conversion system in accordance with the present invention utilizes a series resonant DC-link involving a configuration which employs only unidirectional switches. Unlike the DC parallel resonant converters in which switching of the converter switches occurs at zero-crossing instants of voltage, the present invention utilizes switching of the converter switches only at the zero-crossing instants of the link current. Since the current drops below the holding current, the natural turn-off ability of a conventional thyristor is utilized for commutation. Thus, high power thyristors can be utilized with minimal switching loss. Since the link current is unidirectional, only the usual six thyristors are needed per converter bridge.

The present invention provides a power conversion system which utilizes a series resonant DC-link between the AC/DC and DC/AC converters which provides a natural commutation capability and allows for interruptible switching. By using pulse density modulation this circuit enables the realization of low distortion sinusoidal current as well as unity power factor on both the AC/DC and DC/AC side converters.

The invention further provides a power conversion system utilizing a series resonant DC-link which eliminates oscillation in the output through the use of derivative feed-back and damping circuits.

Further objects, features, and advantages of the invention will be apparent from the following detailed description when taken in conjunction with the accompanying drawings.

In the drawings:

FIG. 1 is a schematic circuit diagram of a prior art parallel resonant AC-link power converter.

FIG. 2 is a schematic circuit diagram of a prior art series resonant AC-link power converter.

FIG. 3 is a schematic circuit diagram of a prior art parallel resonant DC-link power converter.

FIG. 4 is a schematic circuit diagram showing a series resonant circuit, with parallel inductance L.sub.d.

FIG. 5 are graphs illustrating the current waveforms in the circuit of FIG. 4.

FIG. 6 is a graph illustrating the source current waveform for the circuit of FIG. 4.

FIG. 7 is a schematic circuit diagram showing an alternate configuration of the series resonant components shown in the circuit of FIG. 4.

FIG. 8 is a graph illustrating the source current waveform for the circuit of FIG. 7.

FIG. 9 is a schematic circuit diagram illustrating a series resonant circuit with a circulating current thyristor.

FIG. 10 are graphs illustrating circuit behavior of the circuit of FIG. 9 without the circulating current thyristor.

FIG. 11 are graphs illustrating the circuit behavior of the circuit of FIG. 9 with the circulating current thyristor.

FIG. 12 are graphs illustrating link current waveforms without regulation of current through the DC bias inductor.

FIG. 13 are graphs illustrating link current waveforms with regulation of current through the DC bias inductor.

FIG. 14 is a schematic circuit diagram of a current control scheme to control current through the DC bias inductor.

FIG. 15 is a schematic circuit diagram of an AC/DC converter in a motoring mode.

FIG. 16 is a schematic circuit diagram of an AC/DC converter in a circulating mode.

FIG. 17 is a schematic circuit diagram of an AC/DC converter in a regenerating mode.

FIG. 18 is a schematic circuit diagram illustrating the formation of a series resonant DC-link power converter.

FIG. 19 is a schematic circuit diagram showing the detailed circuit implementing the series resonant DC-link scheme.

FIG. 20 are graphs illustrating the distribution of current pulses to a three-phase load.

FIG. 21 are graphs illustrating current reference waveforms.

FIG. 22 is a schematic circuit diagram of a current feed-back selection circuit.

FIG. 23 is a current and thyristor selection table.

FIG. 24 is a table illustrating the polarity of current error for each of the operating modes.

FIG. 25 is a schematic circuit diagram of the control circuit for the overall system.

FIG. 26 is a schematic circuit diagram showing a first load circuit.

FIG. 27 is a graph illustrating current waveforms for a first set of load conditions.

FIG. 28 is a graph illustrating current waveforms for a second set of load conditions.

FIG. 29 is a block diagram of the power converter system illustrating the use of a current feed-back loop with a derivative element.

FIG. 30 is a graph illustrating output current without the use of derivative feed-back.

FIG. 31 is a graph illustrating output current with derivative feed-back.

FIG. 32 is a schematic circuit diagram of a single phase damping circuit.

FIG. 33 is a schematic circuit diagram of a three phase R-C damping circuit.

FIG. 34 is a graph illustating the dissipated energy in damping resistor R.sub.p.

FIG. 35 is a graph illustrating output current employing damping circuit only.

FIG. 36 is a graph illustrating output current employing both derivative feed-back and damping circuit.

FIG. 37 is a graph illustrating output current without the use of either a damping circuit or derivative feed-back.

FIG. 38 is a block diagram of another control system for the conversion apparatus.

FIG. 39 is an illustrative graph of motor current utilizing the control system of FIG. 38.

FIG. 40 is an illustrative graph of motor voltage utilizing the control system of FIG. 38.

To illustrate the principles of the present invention, a series resonant circuit 38 is shown in FIG. 4 which can be controlled to function as a DC resonant link. The circuit 38 includes a direct current (DC) voltage source power supply 39, a series resonant capacitor 40 (of capacitance C.sub.o), a series resonant inductor 41 (of inductance L.sub.o), a DC bias current inductor 42 (of inductance L.sub.d), a load thyristor 43, and a load capacitor 44. The capacitor 40 and inductor 41 are the resonant elements selected to resonate at a frequency consistent with the turn off capability of the load thyristor 43 and are relatively small. The DC bias inductor 42 is a larger inductor which is controlled to support the DC bias current. The currents in FIG. 4 are obtained from the following equations: ##EQU1##

Assume the load thyristor 43 shown in FIG. 4 is switched to the conducting state at t=0. If the DC bias inductor 42 and load capacitor 44 are sufficiently large to maintain the current i.sub.d and voltage V.sub.L constant, then the current i.sub.s is easily solved by defining the intial conditions,

where I.sub.d and V.sub.c0 are constants. The solution to these equations is ##EQU2## the current in the link can be written as,

Typical waveforms for the currents i.sub.o, i.sub.d, and i.sub.s are shown in graphs 45, 46, and 47 respectively, in FIG. 5. As long as the voltage E' remains positive, the link current reaches zero and the load thyristor 43 is able to commutate at t=t.sub.1. Unfortunately, however, in an actual circuit with a finite inductor 42 and finite capacitor 44, the current i.sub.d continues to increase if E' is positive and makes the commutation of load thyristor 43 very difficult, as shown by graph 48 in FIG. 6. Because the resonant link current fails to reach zero during any portion of the resonant cycle, it is impossible to turn off the load thyristor 43.

FIG. 7 shows an improved connection in which the DC bias inductor 42 is connected in parallel with the resonant capacitance 40. As the voltage across the inductor 42 changes according to the capacitor voltage V.sub.o, commutation of the thyristor becomes possible because the resonant current has an oscillation which is not growing, as shown by graph 49 in FIG. 8.

In order to prevent overcharging of the resonant capacitor 40 during the zero current intervals, a circulating thyristor 50 and tapped inductor 41 can be utilized as shown in FIG. 9. The thyristor 50 is triggered to circulate the current i.sub.0 whenever i.sub.s becomes zero. This zero current condition is also required to regulate the output current of the inverter for pulse density modulation and will be described below.

FIGS. 10 and 11 show the current i.sub.s and voltage V.sub.L waveforms with and without use of the circulating current thyristor 50, respectively. When a signal to stop firing the load thyristor 43 occurs, a dead zone appears in the source current waveform as shown by graph 50 in FIG. 10. As a result, the average output voltage V.sub.L does not change substantially and a large pulse of current appears when conduction of the load thyristor 43 commences again. Alternatively, for the case with the circulating thyristor 50 present, the current i.sub.s is readily interrupted while the load thyristor 43 triggering signal is set to zero and a current i.sub.crc flows during this period, as shown by graphs 51 and 52 of FIG. 11.

In practice, the circulating thyristor 50 can be fired not only when a stop signal for i.sub.s appears, but can also function as a clipper for i.sub.s and V.sub.L, in which case the resonance of the LC tank becomes quite stable. The tap ratio n (n<1) of the resonant inductance 41, shown in FIG. 9, affects the sensitivity of the clipping ability of the circulating thyristor 50. If n is set to a large value, the overshoot of current i.sub.s and the voltage V.sub.L increase and the resonance tends to become unstable. On the other hand, when n is chosen very small (nearly zero), the current i.sub.s goes to zero rapidly whenever the voltage V.sub.L becomes equal to E and the necessary zero current cannot be attained.

In order to maintain control of the amplitude of the pulses as illustrated by graph 49 in FIG. 8, regulation of the DC link current i.sub.s is required. Graph 53 in FIG. 12 and graph 54 in FIG. 13 illustrate how the link current i.sub.s varies without and with regulation, respectively. In general, the average value of the current pulse is approximately proportional to i.sub.d. When E' is large, i.sub.s increases and i.sub.d also increases, as shown by graphs 53 and 55 in FIG. 12. After i.sub.s reaches zero at t=t.sub.1, the load thyristor 43 turns off and the current i.sub.d charges up the resonant capacitor 40 generally to a larger value than that which existed on the capacitor before the previous pulse. After each subsequent turn on of the load thyristor 43, the current i.sub.d and i.sub.s pulses continue to increase as shown by graphs 53 and 55 in FIG. 12. Hence, current regulation for this type of converter is mandatory.

Regulation of the DC inductor current i.sub.d is accomplished very easily by current feedback as shown in FIG. 14. A circuit 56 includes a three pole switch 57 which may be connected to either a positive voltage source 58, negative voltage source 59, or to a short circuit condition for which the voltage E is equal to zero. After comparing i.sub.d with the current reference I.sub.dref, the source voltage E is adjusted via the switch 57 to make the error small. For example, if the error .epsilon..sub.d =I.sub.dref -I.sub.d is positive, E is switched from V.sub.d to zero or -V.sub.d ; if .epsilon..sub.d is negative, it goes from -V.sub.d to zero or V.sub.d. As the ability to control i.sub.d also depends on E' (=E-V.sub.L), the measured value of V.sub.L is used for this purpose. While the load thyristor 43 is off, the DC bias inductor 42 charges up the resonant capacitor 40 to a negative polarity to prepare for conduction of the load thyristor 43. The current i.sub.s carries the energy from the resonant circuit to the load or AC source depending upon the polarity of V.sub.L and E. When E is negative, energy flows back to the source and when V.sub.L is positive the energy flows to the load.

Thus far, it has been assumed that the source voltages are essentially constant. Since the source voltages are, in fact, alternating, the identity of the most positive and most negative phase must be established before switching of the source side bridge can commence. The selection of the source voltages, utilizing a common three phase bridge, are easily accomplished as shown in FIGS. 15, 16, and 17. When positive, a large positive voltage E' is needed to cause the current i.sub.d to increase. The bridge thyristors 60-65 are triggered as shown in heavy lines in FIG. 15 and supply positive voltage V.sub.d to the resonant current. FIG. 16 shows the zero voltage mode and FIG. 17 shows the negative voltage mode. These modes are used to decrease the current i.sub.d. As i.sub.s is always positive, the configuration of FIG. 17 regenerates back to the AC source.

When the DC series resonant link circuit is used in a three phase front end bridge circuit in conjunction with a three phase inverter circuit as shown in FIG. 18, and in further detail in FIG. 19, the pulses generated in the resonant circuit must be distributed to each inverter phase. The thyristors 66-71 in FIG. 19 function as a distributor to switch or redirect the link current at the instants where the current i.sub.s is equal to zero. Since the circuit is resonant, this instant occurs when nearly zero voltage exists across the thyristor so that the losses in the thyristors are relatively small. Graphs 72, 73, and 74 in FIG. 20 show the pulse density distribution for each phase in the output of the DC/AC side converter.

The distribution of the pulses to each phase as illustrated in FIG. 20 is automatically determined by comparing the current pulses with the instantaneous phase currents. FIG. 21 shows the current references i.sub.1r and i.sub.2r, FIG. 22 shows the corresponding phase currents i.sub.sa, i.sub.sb, and i.sub.sc and the conducting thyristors in the converter. For example, the current references i.sub.1r and i.sub.2r correspond to i.sub.sa and i.sub.sb within the first 60 degrees, at which point thyristors 66, 67, and 71 are triggered. In the next 60 degrees, these currents correspond to -i.sub.sc and -i.sub.sa and thyristors 71, 69, and 67 are triggered and so on. Accordingly, the same reference table is repetitively used and makes the ROM table very small. The currents i.sub.1 and i.sub.2 are detected from a current sensor 79 with sampling switch 80, as shown in FIG. 22, which is operated sychronized to the triggering signal of the DC/AC converter thyristor firing instants.

The DC/AC converter thyristors are triggered to reduce the maximum error of the three phase currents. Errors .epsilon..sub.a, .epsilon..sub.b, .epsilon..sub.c are obtained from .epsilon..sub.1, .epsilon..sub.2 depending upon the chart shown in FIG. 23. FIG. 24 shows the possible combinations of the .epsilon..sub.a, .epsilon..sub.b, and .epsilon..sub.c for i.sub.sa, i.sub.sb, i.sub.sc, respectively.

As the sum of the errors must satisfy the relation

all the three errors clearly cannot have the same polarity. As the output circuit does not have any neutral line, the current pulse should flow into the postive error phase and flow out from the negative error phase. Hence, the triggering principle is

(i) the thyristor in the phase having the larger error out of the two phases of the same polarity is chosen to be triggered;

(ii) the phase corresponding to the error with the opposite polarity error is selected as the other triggering phase.

For example, in FIG. 24, if .epsilon..sub.a and .epsilon..sub.b are positive then .epsilon..sub.c must be negative. This condition can be termed as mode 1. If .epsilon..sub.a is larger than .epsilon..sub.b, the triggering thyristor is selected to be thyristor 66, and the other thyristor becomes thyristor 71. FIG. 25 shows the schematic diagram of the overall control system. The mode matrix and comparison gate of currents are included in the block switching matrix 86. The AC/DC thyristors 66-71 are triggered by applying the chart shown in FIG. 23. The thyristors shown on the chart are triggered when positive V.sub.d is required on the DC side and these patterns are sychronized to the AC input voltage by the timing pulse f.sub.in.

When a negative voltage E=-V.sub.d is required the triggering thyristors in the chart are replaced from top to bottom or bottom to top of the bridge. As explained previously, circulating thyristor 50 is not triggered while E'=E-V.sub.L is less than V.sub.dl (> 0). Current i.sub.d is regulated to a value three times that of i.sub.dref (k.sub.d =3) in order to ensure sufficient gain to control the load current.

FIGS. 27 and 28 show the resulting current waveforms obtained by a computer simulation. A three phase R-L load with back EMF shown generally at 88 in FIG. 26 has been utilized. Graph 89 in FIG. 27 was obtained for the case R=5.OMEGA., L=1.0 mH, E=100 v, .phi.=-10 deg, L.sub.d =5 mH, L.sub.o =79 .mu.H, C.sub.o =0.79 .mu.F, .omega..sub.0 =2.pi..times.20,000 rad/sec. In addition, the actual simulation includes a resistance r.sub.0 =0.05.OMEGA. as part of the DC bias inductor 42 (L.sub.o) to express the lossy component in the resonant circuit. The waveform shown by graph 89 in FIG. 27 appears to be very satisfactory. However, when the resistance R and L are replaced by an induction motor load, shown generally at 94 in FIG. 19, (200 v, 1.5 kw), i.e., R=1.0.OMEGA. and L=2 mH, a high frequency oscillation appears as shown by graph 90 in FIG. 28. This oscillation is clearly caused by interaction of the filter capacitance 95 and motor load inductance 96 as shown in FIG. 19. Since the loop of the oscillation involves two C's and two L's in series, the resonant frequency f.sub.r is ##EQU3## For this case f.sub.r =1250 Hz. This phenomena appears to be a generic problem for any current source converter having output capacitance and is not peculiar to this circuit alone.

The stabilization of the system is difficult by controlling the current i.sub.s only. Even if the system is accurately controlled, the oscillation remains between the capacitor 95 and load inductance 96, as shown in FIG. 19, almost independent from the inverter i.sub.s. Stabilization was, however, accomplished by controlling the motor currents, i.sub.a, i.sub.b, and i.sub.c instead of the output currents i.sub.sa, i.sub.sb, i.sub.sc. FIG. 29 shows the current feedback loop with a derivative element 97. Two loops are needed to obtain i.sub.a, i.sub.b, and i.sub.c. In this case, AC link frequency corresponding to the resonant inductor 41 and resonant capacitor 40 is almost completely filtered by the load capacitances 95. Hence, feedback was easily accomplished without any further filtering. The derivative circuit was implemented by a simple R-C circuit 97 as shown in FIG. 29. The time constant was selected as 50 s and the gain was 2.0. The resulting waveform is shown in FIG. 31 and can be compared to the case without derivative feedback, i.e., K.sub.drv =0 in FIG. 30. The system is completely unstable without feedback as shown in FIG. 30 but the system is stabilized by using derivative feedback, although it still has an oscillation as shown in FIG. 31. The remaining high frequency oscillation over 2 kHz is ripple caused by the discrete current pulses.

In order to further reduce or absorb the high frequency component caused by the current pulses, the damper circuit shown in FIG. 32 has been found to be effective. The damping circuit utilizes a resistance 98 (of resistance r.sub.dmp) and capacitor 99 (of capacitance C.sub.dmp). If the voltage of ripple component is assumed to be E.sub.rpl in the expression of the RMS phasor, the current through the resistor 98 is obtained from ##EQU4## and the dissipated energy P.sub.dss in R.sub.dmp will be ##EQU5## Hence, the resistance R.sub.dmp is selected as ##EQU6## and the maximum dissipation P.sub.dmax can be calculated in the form

Using the resistance R.sub.dmp value as calculated above, the dissipation in the output at fundamental frequencies becomes extremely small. FIG. 34 shows the dissipation P.sub.dss as a function of the time constant .tau..sub.dmp =R.sub.dmp C.sub.dmp and ripple frequency f.sub.rpl when the capacitance C.sub.dmp is assumed constant. For example, if the ripple frequency and capacitance C.sub.dmp are assumed to be 2000 Hz and 1.0.mu.F, respectively, then R.sub.dmp becomes 80 ohms from the condition of the three error signals summing to zero, and the time constant .tau..sub.dmp=R.sub.dmpC.sub.dmp equals 80 microseconds.

If the fundamental frequency is 50 Hz then, from the characteristic for .tau..sub.dmp equal to 80 .mu.s in FIG. 34, the dissipated energy both in ripple frequency and in fundamental frequency are ##EQU7## Hence the fundamental component is negligible and the dominant dissipating energy is the ripple component and very strong selective frequency damping will be performed.

FIGS. 35 and 36 show the results of using damping circuits for the systems whose non-damped responses are shown in FIGS. 30 and 31, respectively. Remarkable improvement is apparent in both cases. In the case of non-derivative feedback (FIG. 36), the system was stabilized and a much smaller ripple in the current was obtained. As shown in FIG. 36, the damping capacitance is almost comparable to the output capacitance, so that the capacitance C's are increased in FIG. 37 while the other parameters are the same as in FIG. 36. Though a better result was obtained in FIG. 37, this waveform still contains a larger ripple than in FIG. 36.

FIG. 38 illustrates another control scheme which utilizes an internal voltage regulator in the ABC frame of reference and an external current regulator in the synchronous DQN reference frame. The choice of the synchronous reference frame for the outer loop is related to the optimized performance of proportional integral regulators with only DC signals. As shown in FIG. 38, phase currents i.sub.a and i.sub.b being supplied to a motor 110 are provided to a control unit 112 which converts to a DQN reference, providing output current values i.sub.qs and i.sub.ds. These values are compared to reference values i*.sub.qs and i*.sub.ds and the difference provided to proportional integral controllers 114 and 115, the outputs of which are converted by a control unit 117 to ABC values. These are compared in the internal loops to measured voltages V.sub.a, V.sub.b and V.sub.c, and the differences are provided to proportional integral controllers 118, 119, and 120, and modulators 122, 123, and 124, the outputs of which are provided to the switching sequence matrix to drive the inverter 126.

This control structure essentially eliminates any resonance frequency in the output waveforms of voltage and current. FIGS. 30 and 40 are illustrative graphs of motor current and voltage with this control system employed. This control scheme is suitable for application with various strategies of speed regulation, such as direct or indirect field orientation control and slip control.

It may be noted that although the systems of the present invention are well suited to the use of force commutated switching devices such as thyristors, self commutated devices such as transistors and GTO's may be utilized if desired.

It is understood that the invention is not limited to the particular embodiments set forth herein as illustrative, but embraces all such modified forms thereof as come within the scope of the following claims.