US 4,942,440 AGrant

High Voltage Semiconductor Devices With Reduced on-Resistance

Issue Date:1990-07-17

•36 Claims

•1 Drawing Sheets

Abstract

A high voltage P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface thereof. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup.+ cathode region, as viewed from above. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. In an exemplary embodiment, a MOSFET is included to alternately connect the further P.sup.+ region to the P.sup.- substrate and to open circuit the further P.sup.+ region. With the further P.sup. + region open circuited, the P-N diode has a low on-resistance when it operates in its current-conducting state. An embodiment structurally similar to the P-N diode comprises a bipolar transistor having an N.sup.+ emitter region extending into a P.sup.+ base region, which corresponds to the P.sup.+ anode region of the diode.

Metadata

Assignee

General Electric Company

Inventors

Bantval J. Baliga
Eric J. Wildi

Application Information

Application Number:US 2432102

Filing Date:1988-09-09

Priority Date:1982-10-25

Art Unit:258

Classifications

IPC:

H01L 2978

Field of Search:

35730723.1;22;35;38;43;41;51;52;53;48431;633;571

Patent Drawings (1 sheets)

Description

The present application is related to commonly-assigned U.S. Pat. No. 394,346, filed July 1, 1982, by M. S. Adler and E. J. Wildi (one of the present inventors), the entirety of which is hereby incorporated by reference.

Background of the Invention

Our invention relates to semiconductor devices capable of supporting high reverse voltages while in a current-blocking state and, more particularly, to such devices having means for reducing the on-resistance (or anode-to-cathode resistance while "on" or conducting) of the devices.

The above-referenced application describes a high voltage P-N diode including a thin N.sup.- (or lightly-doped N-type) layer atop a P.sup.- substrate. An N.sup.+ (or highly-doped N-type) cathode region extends into the N.sup.- epitaxial layer from its upper surface, and a P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. To reduce parasitic currents in the device, an N.sup.+ buried layer exists between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, so as to surround the N.sup.+ cathode region (when viewed from above). In order to avoid the loss of voltage-supporting capability in the N.sup.- epitaxial layer between the N.sup.+ cathode region and the N.sup.+ buried layer, a further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and is interposed between the N.sup.+ cathode region and the P.sup.+ anode region so as to surround the N.sup.+ cathode region and, in turn, be surrounded by the P.sup.+ anode region. The further P.sup.+ region is permanently biased at or near the potential the P.sup.- substrate, whereby the N.sup.- epitaxial layer, between the further P.sup.+ region and the N.sup.+ cathode region, supports reverse voltages in the device. The foregoing P-N diode attains a reasonably low value of on-resistance. It would be desirable, however, to provide a diode having an even lower value of on-resistance.

The above-referenced patent application describes (and claims) a bipolar transistor which is structurally similar to the foregoing P-N diode. The present invention addresses a similar concern about the desirability of reduced on-resistance of a bipolar transistor.

Summary of the Invention

Accordingly, it is an object of our invention to provide a high voltage semiconductor device having a lower value of on-resistance than previously attainable.

A further object of our invention is to provide electronic circuitry for enabling a high voltage semiconductor device to achieve a lower value of on-resistance than previously attainable, which circuitry can be formed in a single integrated circuit along with the high voltage semiconductor device.

In accordance with the illustrated embodiments of our invention, we provide a P-N diode of the type including a P.sup.- substrate with an N.sup.- layer thereon, and further including an N.sup.+ cathode region, a P.sup.+ anode region, an N.sup.+ buried layer, and a further P.sup.+ region. The N.sup.+ cathode region extends into the N.sup.- layer from its upper surface. The P.sup.+ anode region extends into the N.sup.- layer from its upper surface and surrounds the N.sup.+ cathode region (as viewed from above). The N.sup.+ buried layer is situated between the N.sup.- epitaxial layer and the P.sup.- substrate, beneath the P.sup.+ anode region, and surrounds the N.sup.+ cathode region. The further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface, surrounds the N.sup.+ cathode region and, in turn, is surrounded by the P.sup.+ anode region. We provide a bias means for supplying the further P.sup.+ region with a plurality of different bias drives, one at a time, so as to effect different degrees of conductivity in the N.sup.- epitaxial layer, between the N.sup.+ cathode region and the P.sup.+ anode region.

In accordance with a further embodiment of our invention, we provide a bipolar transistor which is structurally similar to the foregoing P-N diode, except that an N.sup.+ emitter region extends into a P region corresponding to the P.sup.+ anode region of the P-N diode. The bipolar transistor has an N.sup.+ collector region corresponding to the N.sup.+ cathode region of the P-N diode.

Brief Description of the Drawings

While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which we regard as our invention, it is believed that the invention will be better understood with reference to the following description, taken in conjunction with the drawings, in which:

FIG. 1 is a schematic view in cross-section of a portion of a P-N diode in accordance with our invention

FIG. 2 is a view of a modified P-N diode incorporating an alternative bias means in accordance with our invention;

FIG. 3 is a detail view of a portion of the P-N diode of FIG. 1; and

FIG. 4 is a view of a modification of the structure of FIG. 3 for implementing a bipolar transistor.

Description of the Preferred Embodiments

FIG. 1 illustrates a portion of a P-N diode 10 to the left of a line of symmetry 12. P-N diode 10 suitably comprises a bulk P.sup.- substrate 14, preferably silicon, with an N.sup.- layer 16 thereon, preferably an epitaxial silicon layer. An N.sup.+ cathode region 18 extends into the N.sup.- layer 16 from the upper surface thereof. A P.sup.+ anode region 20 extends into N.sup.- layer 16 from its upper surface and surrounds N.sup.+ region 18 as viewed from above. N.sup.+ buried layer 22 is situated between N.sup.- layer 16 and P.sup.- substrate 14, beneath P.sup.+ anode region 20 and surrounds N.sup.+ cathode region 18. A further P.sup.+ region 24 extends into N.sup.- layer 16 from its upper surface, surrounds N.sup.+ cathode region 18, and, in turn, is surrounded by P.sup.+ anode region 20. A P.sup.+ isolation region 26 is integrally connected to P.sup.- substrate 14, and surrounds the periphery of N.sup.- layer 16, thereby enabling other semiconductor devices to be formed, along with P-N diode 10, in an integrated circuit.

The presence of N.sup.+ buried layer 22 in P-N diode 10 serves to reduce parasitic currents in diode 10 that otherwise would exist. The presence of P.sup.+ region 24, appropriately biased to a potential approximately equal to or slightly more positive than that of P.sup.- substrate 14 when diode 10 is in a current-blocking state, enables the portion of N.sup.- epitaxial layer 16 between P.sup.+ region 24 and N.sup.+ cathode 18 to support high reverse voltages. This is because, without P.sup.+ region 24 so biased, N.sup.+ buried layer 22 would rise in potential to that of N.sup.+ cathode 18, leaving only the thin region of N.sup.- layer 16 between N.sup.+ buried layer 22 and P.sup.+ anode region 20 to support reverse voltages. Such thin region of N.sup.- layer 16 would likely break down under high reverse voltage.

In accordance with our invention, we provide a bias means 28 for supplying P.sup.+ region 24 with a plurality of different bias drives so as to differently bias P-N junction 32, extant between P.sup.+ region 24 and N.sup.- layer 16. The different biasing conditions of P-N junction 32 serve to effect different degrees of conductivity in the N.sup.- layer 16 between P.sup.+ anode region 20 and N.sup.+ cathode region 18, as will be described more fully hereinbelow.

Bias means 28, in the exemplary embodiment illustrated, comprises a depletion mode (i.e., normally-conducting) P-channel metal-oxide-semiconductor field effect transistor (MOSFET) 34. MOSFET 34, in the absence of any bias voltage on its gate 36, electrically shorts P.sup.+ region 24 to P.sup.+ isolation region 26, which is at the potential of P.sup.- substrate 14. This is because, in such state of MOSFET 34, P-channel 38 of MOSFET 34 provides a high conductivity path between P.sup.+ region 39, which is electrically shorted to P.sup.+ region 24, and P.sup.+ isolation region 26. When gate 36 is biased with a positive voltage in excess of a threshold value so as to deplete P-channel 38 of holes and thereby reduce its conductivity, P.sup.+ region 24 is open circuited, that is, supplied with a bias drive of zero current. This zero current bias drive of P.sup.+ region 24 advantageously results in P-N diode 10 having a lower value of on-resistance than if P.sup.+ region 24 were biased to the potential of P.sup.- substrate 14. This is because, in P-N diode 10, there is a much smaller depletion region extending into N.sup.- layer 16 from P-N junction 32, in contrast to the case where P.sup.+ region 24 is biased to the P.sup.- substrate 14 potential, such as appertains to the P-N diode of the above-referenced application.

Bias means 28 with MOSFET 34 is preferably formed along with P-N diode 10 in a single integrated circuit. However, bias means 28 could be implemented as a separate device. Bias means 28 is an exemplary bias means for P.sup.+ region 24, and could be implemented in many different forms. For example, MOSFET 34 of bias means 28 could be replaced by other switching means, such as a bipolar transistor. Moreover, the bias means for P.sup.+ region 24 could be implemented as bias means 28', which is illustrated in FIG. 2.

FIG. 2 depicts a P-N diode 40, which is identical to P-N diode 10 (FIG. 1) except for the inclusion of a different bias means 28' for the corresponding P.sup.+ region 24', shown to the left of P.sup.+ isolation region 26'. The different bias means 28' includes a resistance means 50 of ohmic value R having a terminal 52 adapted to be connected to a source of voltage (not shown) so as to be biased at a positive voltage, V.sub.s, and a further terminal 54, which is connected to P.sup.+ region 24'. Bias means 28' further includes an enhancement mode or normally-off MOSFET 56. One terminal 58 of MOSFET 56 is electrically shorted, via electrode 60, to P.sup.+ isolation region 26', which is at the potential of P.sup.- substrate 14. Another terminal 62 of MOSFET 56 is electrically shorted, via conductor 68, to P.sup.+ region 24'.

Bias means 28' is effective to produce, via conductor 68, two different bias drives on P.sup.+ region 24'. These two different bias drives can be readily understood by considering voltage pulses 70 and 72, which can be determined by monitoring gate 74 of MOSFET 56 and conductor 68, respectively.

With zero bias voltage on gate 74, the voltage on conductor 68 is equal to the bias voltage V.sub.s on terminal 52, reduced by the IR (or current x resistance) voltage drop across resistance means 50. Consequently, P.sup.+ region 24' is supplied with a bias drive characterized by the voltage on conductor 68 and by a current limited by the combined resistances of the voltage source (not shown) which biases terminal 52 to V.sub.s volts the resistance means 50, and the resistance through P.sup.+ region 24' to a ground or reference level.

With gate 74 of MOSFET 56 biased at a positive voltage, V.sub.s, above a threshold value, an inversion layer is formed in region 76 of MOSFET 56, beneath gate 74. The inversion layer is highly conductive to electrons, and, together with N.sup.+ regions 78 and 80, completes a current path from terminal 58, which is at the potential of P.sup.- substrate 14', to conductor 68, via terminal 62, thereby biasing conductor 68 to the potential of P.sup.- substrate 14'. With conductor 68 so biased, P.sup.+ region 24' is supplied with a bias drive characterized by the P.sup.- substrate 14' potential and by no current (or zero level current), since P-N junction 32', between P.sup.+ region 24' and N.sup.- layer 16' is reverse biased.

When P-N diode 40 is operating in its current-blocking state, P.sup.+ region 24' should be supplied with a bias drive characterized by the potential of P.sup.- substrate 14' and zero current. When P-N diode 40 is operating in its current-conducting state, however, P.sup.+ region 24' should be supplied with a bias drive characterized by being at the potential V.sub.s, as reduced by the IR voltage drop across resistance means 50. With such potential of P.sup.+ region 24' being greater than about one volt above the potential of P.sup.+ anode region 20', at least for silicon devices, P-N junction 32', between P+ region 24' and N.sup.- layer 16', is forward biased, and, in accordance with an important aspect of our invention P.sup.+ region 24' thereby injects holes into N.sup.- layer 16'. Then, in accordance with the principle of quasi-neutrality (as discussed for example, in R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, New York, N.Y.: Wiley & Sons (1977), pages 105, 111 and 112 the concentration of electrons in N.sup.- layer 16' increases to approximately that of the holes injected thereinto by P.sup.+ region 24'. As a result, the resistance of N.sup.- layer 16', between P.sup.+ anode region 20' and N.sup.+ cathode region 18', is reduced, thereby reducing the on-resistance of P-N diode 40 so as to achieve a main objective of our invention.

While resistance means 50 and MOSFET 56 are illustrated in the preferred embodiment in which they are formed along with P-N diode 40 in a single integrated circuit, such devices could alternatively be formed as separate devices. If devices 50 and 56 are formed in a single integrated circuit as illustrated, it is desirable that P.sup.+ isolation region 26' be interposed between P-N diode 40 and such devices. P.sup.+ isolation region 26' could be omitted, however, if the distance of separation between P-N diode 40 and such devices is sufficient to prevent adverse electrical interference therebetween, although this would result in more space consumed in the integrated circuit.

Our invention is also useful in semiconductor devices other than P-N diodes, such as bipolar transistors. To make a bipolar transistor requires a variation of the structure associated with P.sup.+ anode region 20 (FIG. 1), which is illustrated in the detail view of FIG. 3. Appropriate modified structure is shown in FIG. 4, in which P base region 120 corresponds to P.sup.+ anode region 20 of FIG. 3. In FIG. 4, N.sup.+ emitter region 190 extends into P base region 120 from the upper surface of region 120, and surrounds an N.sup.+ collector region (not illustrated) which corresponds to N.sup.+ cathode region 18 of P-N diode 10 (FIG. 1).

In fabricating the devices illustrated herein, each of the regions shown as extending into a device from the upper surface thereof can be formed by either diffusion or ion implantation, and the N.sup.+ buried layers can be formed by either diffusion or ion implantation through the upper surface of the respective P.sup.- substrate prior to the growth of the respective N.sup.- epitaxial layer thereon.

In the best mode we contemplate for practicing our invention, the mathematical product of the thickness and doping concentration of the N.sup.- epitaxial layer of each device described herein is selected in accordance with Reduced Surface Field (or RESURF) Technology in order to maximize the reverse voltage attainable by each device. Details of RESURF Technology may be found, for example, in an article by J. A. Appels and H. M. J. Vaes, "High Voltage Thin Layer Devices (RESURF Devices)", Proceedings of the 1979 IEEE International Electron Device Meeting, pages 238-241, as well as in an article by S. Colak, B. Singer and E. Stupp, "Design of High-Density Power Lateral DMOS Transistors", Proceedings of the 1980 IEEE Power Electronics Specialists Conference, pages 164-167.

In summary, the foregoing describes high voltage semiconductor devices having reduced on-resistance. Suitable semiconductor devices employed to attain such reduced on-resistance can advantageously be formed along with such a high voltage semiconductor device in a single integrated circuit.

While only certain preferred features of our invention have been shown by way of illustration, many modifications and substitutions will occur to those skilled in the art, such as those discussed in the above-referenced patent application. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and substitutions as fall within the true spirit of our invention.

Claims

What is claimed as our invention and desired to be secured by Letters Patent of the United States is:

1. In combination: a semiconductor device comprising a body of semiconductor material including: a substrate of one conductivity type with a layer of opposite conductivity type thereon, and including first and second regions disposed within said layer; said first region being of said opposite conductivity type and more heavily doped than said layer and extending to an upper surface of said body and said second region being of said one conductivity type, extending to said upper surface, being spaced from and surrounding said first region, a third region of said opposite conductivity type buried between said layer and said substrate beneath said second region and spaced from said second region by a portion of said layer, a fourth region of said one conductivity type disposed within said layer, forming a P-N junction therewith, extending to said surface, being spaced from and surrounding said first region and, in turn, being surrounded by and spaced from said second region, and a controllable bias means integrated therein for controllably connecting said fourth region to said substrate and disconnecting said fourth region from said substrate; a first electrode in ohmic contract with said first region; a second electrode in ohmic contact with said second region; a third electrode connected as an output electrode of said controllable bias means; a fourth electrode in ohmic contact with said fourth region; a fifth electrode connected as a control electrode for said controllable bias means; a sixth electrode in ohmic contact with said substrate; said third electrode being ohmically connected to said fourth electrode to enable said controllable bias means to control the potential of said fourth region to establish different degrees of conductivity in said layer between said first region and said second region in response to control signals applied to said fifth electrode.

2. The invention of claim 1 wherein said controllable bias means comprises switching means for controllably connecting said third electrode to said substrate.

3. The invention of claim 1 wherein said controllable bias means comprises switching means for controllably providing an open circuit at said third electrode.

4. The invention of claim 1 wherein said controllable bias means comprises switching means for in a first state connecting said third electrode to said substrate, and, in a second state, disconnecting said third electrode from said substrate.

5. The invention of claim 4 wherein said switching means comprises a MOSFET integrated in said body.

6. The invention of claim 1 wherein said controllable bias means comprises switching means for alternately connecting said third electrode to said substrate and disconnecting said third electrode from said substrate.

7. The invention of claim 1 further comprising a voltage lead adapted for connection to a voltage source and wherein said controllable bias means comprises switching means for controllably connecting said third electrode to said voltage lead.

8. The invention of claim 7 further comprising a resistor integrated in said body and connected in the current path between said third electrode and said voltage lead.

9. The invention of claim 8 wherein said resistor comprises a further region of said one conductivity type extending into said layer from said upper surface.

10. The invention of claim 1 wherein said controllable bias means comprises switching means for connecting a voltage to said third electrode to forward bias said P-N junction to such an extent that said fourth region injects current carriers into said layer.

11. The invention of claim 1 further including a voltage lead adapted for connection to a voltage source and wherein said controllable bias means includes switching means or in a first state connecting said third electrode to said voltage lead, and, in a second state, connecting said third electrode to said substrate.

12. The invention of claim 11 further comprising a resistor integrated in said semiconductor body and connected in the current path between said third electrode and said voltage lead.

13. The invention of claim 12 wherein said resistor comprises a further region of said one conductivity type extending into said layer from said upper surface.

14. The invention of claim 13 wherein said switching means comprises a MOSFET integrated in said body.

15. The invention of claim 1 further including a voltage lead adapted for connection to a voltage source and wherein said controllable bias means includes switching means for alternately connecting said third electrode to said voltage lead and to said substrate.

16. The invention of claim 1 further comprising an isolation region integrally connected to said substrate and surrounding the periphery of said layer.

17. The invention of claim 1 further comprising an additional region of said opposite dopant type extending into said second region from the upper surface thereof and surrounding said first region.

18. The invention of claim 1 wherein said substrate and said second and fourth regions comprise semiconductor material of P-type conductivity and said layer and said first and third regions comprise semiconductor material of N-type conductivity.

19. The invention of claim 18 wherein said substrate, said layer, and said first, second, third and fourth regions each comprise silicon semiconductor material.

20. In a semiconductor RESURF device of the type including a substrate of one conductivity type having a thin layer of opposite conductivity type semiconductor material thereon, said layer including first and second regions therein; said first region being of said opposite conductivity type, more heavily doped than said layer and extending into said layer from the upper surface thereof, and said second region being of said one conductivity type, extending into said layer from said upper surface and spaced from and surrounding said first region, a first electrode in ohmic contact with said first region, a second electrode in ohmic contact with said second region, and a third electrode in ohmic contact with said substrate, the improvement comprising: a third region of said opposite conductivity type buried between said layer and said substrate beneath said second region and in projection on said upper surface encompassing said second region; a fourth region of said one conductivity type extending into said layer from said upper surface and forming a P-N junction therewith, spaced from and encircling said first region and, in turn, being spaced from and encircled by said second region; and controllable bias means integrated in said device and ohmically coupled to said fourth region for adjustably biasing and unbiasing said fourth region relative to said substrate to controllably alter the conductivity of said thin layer between said first and second regions.

21. The device of claim 20, wherein said controllable bias means is adapted to supply to said fourth region, a potential about one volt above the potential of the second region, whereby the junction between the fourth region and the thin layer is forward biased and said fourth region injects carriers into said thin layer to thereby reduce the resistance of said thin layer between said first and second regions of the semiconductor RESURF device.

22. The semiconductor device of claim 1 wherein: said body of semiconductor material further includes: a fifth region of said one type conductivity disposed in said layer and extending to said upper surface and disposed in ohmic contact with said third electrode, and an additional region of said one conductivity type integrally connected to said substrate and extending to said upper surface of said body; said controllable bias means comprises an insulated gate electrode disposed on said layer for controlling the conductivity of a channel connecting said fifth region to said additional region for coupling said third electrode to said substrate in response to the application of an appropriate bias and for decoupling said third electrode from said substrate in response to removal of said bias.

23. The semiconductor device of claim 22 wherein said insulated gate electrode extends over said additional region and in response to said application of said appropriate bias induces a connection between said fifth region and said additional region.

24. The semiconductor device of claim 1 wherein said controllable bias means includes: a fifth region of said one type conductivity disposed within said layer; sixth and seventh regions of said opposite type conductivity disposed within said fifth region in spaced apart relation, said sixth region being coupled to said fourth region and said seventh region being coupled to said substrate; and a gate electrode overlying, and being insulatingly spaced from said fifth, sixth and seventh regions, said gate electrode controlling conduction within said fifth region between said sixth and seventh regions, and in response to a first appropriate applied bias, coupling said fourth region to said substrate and in response to a second appropriate applied bias, decoupling said fourth region from said substrate.

25. The semiconductor device of claim 1 wherein said ohmic connection between said third and fourth electrodes comprises a high conductivity path disposed on said layer.

26. The semiconductor device of claim 1 wherein said ohmic connection between said third and fourth electrodes comprises a metallized track extending from said third electrode to said fourth electrode.

27. A semiconductor device comprising a body of semiconductor material including: a first layer of one type conductivity; a second layer of opposite type conductivity disposed on said first layer; a first region of said opposite type conductivity more heavily doped to said opposite type conductivity than said second layer, disposed within said second layer and extending to an upper surface of said body; a second region of said one type conductivity disposed within said second layer, extending to said upper surface, spaced from and surrounding said first region; a third region of said opposite conductivity type buried between said second layer and said first layer beneath said second region, said third region being spaced from said second region by a portion of said second layer and in projection on said upper surface encompassing said second region; a fourth region of said one conductivity type extending into said second layer from said upper surface and forming a P-N junction therewith, spaced from and encircling said first region and, in turn, being encircled by and spaced from said second region; a first electrode ohmically connected to said first region; a second electrode ohmically connected to said second region; a third electrode ohmically connected to said first layer; a fourth electrode ohmically connected to said fourth region; and an insulated gate disposed on said second layer for controlling the conductivity of a channel in a current path coupling said fourth electrode to said first layer for coupling said fourth electrode to said first layer in response to an appropriate applied bias and for decoupling said fourth electrode from said first layer in response to removal of said appropriate applied bias.

28. The semiconductor device of claim 27 wherein said insulated gate in response to application of said appropriate bias induces a connection between said fourth electrode and a fourth region of one type conductivity connected to said first layer.

29. The semiconductor device of claim 28 wherein said insulated gate disposed on said second layer comprises an insulation layer disposed on said second layer and a gate electrode disposed atop said insulation layer.

30. The semiconductor device of claim 29 further including a fifth region of said one type conductivity disposed within said second layer, said fourth electrode being directly connected to said fifth region, said gate electrode and said insulation layer further overlying said fifth and further regions.

31. The semiconductor device of claim 29 wherein said further region extends through said second layer and is integrally connected to said first layer and said insulated gate is in part disposed over said further region.

32. A semiconductor device comprising a body of semiconductor material including: a first layer of one type conductivity; a second layer of opposite type conductivity disposed on said first layer; a first region of said opposite type conductivity more heavily doped to said opposite type conductivity than said second layer, disposed within said second layer and extending to an upper surface of said body; a second region of said one type conductivity disposed within said second layer, extending to said upper surface and spaced from and surrounding said first region; a third region of said opposite conductivity type buried between said second layer and said first layer beneath said second region, said third region being spaced from said second region by portion of said second layer and in projection on said upper surface encompassing said second region; a fourth region of said one conductivity type extending into said second layer from said upper surface and forming a P-N junction therewith, spaced from and encircling said first region and, in turn, being encircled by and spaced from said second region; an additional region of said one conductivity type integrally connected to said first layer and extending to said upper surface; a fifth region of one type conductivity disposed within said second layer; sixth and seventh regions of opposite type conductivity disposed within said fifth region, said sixth region being coupled to said fourth region and said seventh region being coupled to said first layer via said additional region; and a gate electrode overlying, and being insulatingly spaced from said fifth, sixth and seventh regions, said gate electrode, in response to an appropriate applied bias, coupling said fourth region to said first layer and in response to removal of said bias, decoupling said fourth region from said first layer.

33. The semiconductor device of claim 27 wherein said additional region comprises an isolation region surrounding the periphery of said second layer.

34. The semiconductor device of claim 27 further including a second additional region of said opposite dopant type extending into said second region from the upper surface thereof and encircling said first region.

35. The semiconductor device for claim 27 wherein said second and fourth regions comprise semiconductor material of P-type conductivity and said second layer and said first and third regions comprise semiconductor material of N-type conductivity.

36. A semiconductor device comprising: a substrate of one type conductivity; a layer of opposite type conductivity disposed thereon; a first region of opposite type conductivity disposed within said layer and more heavily doped to said opposite type conductivity than said layer; a second region of said one type conductivity disposed within said layer; a third region of said opposite type conductivity buried between said layer and said substrate beneath said second region and spaced from said second region by said layer; a fourth region of said one type conductivity disposed within said layer, spaced from and surrounding said first region and being surrounded by and spaced from said second region; a bias means integrated in said device and coupled to said fourth region by a current path for supplying said fourth region with bias drives to control the degree of conductivity in said layer between said first region and said second region, said bias means comprising a MOSFET integrated with said substrate of the semiconductor device; a first electrode in ohmic contact with said first region; a second electrode in ohmic contact with said second region; a third electrode in ohmic contact with either the source or the drain region of said MOSFET; and a fourth electrode in ohmic contact with said fourth region; said third and fourth electrodes being ohmically connected by said current path.

Patent Citations (10)

Patent	Date	Inventor
US4086611	1978-04-01	Nishizawa et al.
US4292642	1981-09-01	Appels et al.
US4354121	1982-10-01	Terasawa et al.
US4409606	1983-10-01	Wagenaar et al.
US4422089	1983-12-01	Vaes et al.
US4485392	1984-11-01	Singer
US4494134	1985-01-01	Wildi et al.
JPX53-63987	1978-06-01
JPX53-67368	1978-06-01
JPX56-62372	1981-05-01

Non-Patent Literature (2)

M. Cowan et al., "Combat Lat. PNP . . . , Device", IBM Tech. Discl. Bull., vol. 13 #4, Sep. 1970, pp. 939-940.
R. Hruby et al., "Substrate-Emitter . . . Appl.", IEEE J. S-S Ckts., vol. SC-6 #3, Jun. 1971, pp. 115-119.

Abstract

Description