Integrated Circuit Option Identification Circuit and Method

The present invention relates to integrated logic circuits and, more particularly, to a circuit and method for providing electrical identification of different families of such circuits having identical functionality but different input/output behavior without the need for requiring extensive testing at the manufacturing process level.

Semiconductor manufacturers of standard logic integrated circuits often provide two or more families or versions of circuits having the same logic functions but different input/output characteristics. An example of the foregoing are the 10E and 100E Emitter-Coupled-Logic (ECL) families manufactured by Motorola, Inc. The 10E and 100E family of products provide the same logic functions but have different biasing requirements and output characteristics with temperature. Moreover, each particular logic circuit of each family is produced from the same mask set such that it is impossible to tell which family to which the logic circuit belongs without testing.

Since the functionality of the two families of logic circuits are the same it is necessary to provide some means at the manufacturing and test level to identify to which a family the ECL circuit belongs. This is needed to prevent substitution of an ECL circuit from one family with that of another logic family by mistake.

Accordingly, it is an object of the present invention to provide a method for identifying different families of logic circuits having the same functionality but different input/output characteristics from one another.

It is another object of the invention to provide an integrated circuit option identification circuit.

In accordance with the above and other objects there is provided an identification circuit for use in identifying at least two integrated circuits having the same logic function but different input/output characteristics, each circuit having first and second isolated power supply conductors, which comprises circuitry having an input and an output for unilaterally conducting current between the input and output thereof; and conductive means which is provided only in one of the two circuits and not in the other for coupling the input and output of the circuitry respectively to the first and second power supply conductors wherein current flows in the circuitry as the first power supply conductor is raised to a higher potential with respect to the second power supply conductor during test of the integrated circuits.

The above and other objects, features, and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a standard ECL circuit including the identification circuit of the present invention; and

FIG. 2 is a schematic diagram illustrating a typical input gate of a standard ECL circuit.

Turning now to the Figures there is shown within the dashed box a standard ECL integrated circuit which includes identification circuit 10 of the preferred embodiment. The ECL circuit typically includes an input gate 12 having an output coupled to the output driver stage comprising NPN transistor 14 and an input coupled to terminal 16. FIG. 2 illustrates a conventional input gate 12 which includes emitter coupled NPN transistors 20 and 22. The base of transistor 20 is coupled to input 16 to receive a logic input signal while its emitter is coupled to a current supply 24 and its collector is coupled via resistor 26 to a power supply conductor at which is provided a source of operating potential V.sub.CC. Transistor 22 also has its emitter coupled to current supply 24 and its collector coupled to V.sub.CC via resistor 28 while its base is coupled to a bias potential V.sub.BB at terminal 30. The output of input gate 12 may, for instance, be taken at the collector of transistor 22 and be coupled to the base of transistor 14, the latter having its collector-emitter conduction path coupled between V.sub.CCO and the output of the ECL circuit at terminals 38 and 18 respectively. Hence, in operation, in response to a logic input signal at terminal 16, a logic output signal will be produced at output 18 as transistor 14 is driven between high and low operating states as is well known. Although input gate 12 is shown as having only a single input transistor 20 having its emitter coupled to the emitter of transistor 22 it is understood that any number of input transistors can be provided which would, for example, have their respective collectors and emitters coupled in parallel to the collector and emitter of transistor 20 and their bases coupled to respective input terminals of the ECL circuit in order to provide desired logic circuit functions.

As previously discussed, different logic families can be manufactured having the same logic functionallity but different behavior characteristics. In this case, the logic circuit, as shown in FIG. 1, may be functionally equivalent for each family. Typically, the ECL circuits have first and second isolated power supply conductors 36 and 38 to which equal operating potentials V.sub.CC and V.sub.CCO are supplied during operation of the ECL logic circuit. Generally, the semiconductor manufactured has had problems in determining to which family the ECL circuit belongs after packaging and at the test level prior to shipment of the circuits to customers.

Circuit 10 of the present invention provides a method for identifying two versions of the same logic function ECL circuit from one another. In each version circuit 10 would be formed in the integrated circuit during process of the circuit. Option identification circuit 10 includes at least one diode connected transistor 32 and resistor 34. The latter of which is coupled in series with the collector-emitter conduction path of the transistor. Circuit 10, although being present in each version of the logic family of logic circuits is coupled to power supply conductors 36 and 38 in only one of the versions or logic families. Circuit 10 is coupled to conductors 36 and 38 through a pair of metal mask options 40A connecting resistor 34 to terminal 36 and the collector of transistor 32 to terminal 38. Thus, in the process step of making the integrated circuit metal links are formed on the integrated circuit for operationally connecting circuit 10 between terminals 36 and 38 only for those logic circuits of one logic family and not for those logic circuits of the other logic family.

The identification of the integrated circuit families requires the generation of a predetermined potential at terminal 38 and the sensing of the current flowing through identification circuit 10 both of which may be provided via an external test set featuring voltage generating circuity and current sensing circuity. During the testing phase, terminals 38 and 36 may be coupled to the first and second terminals the test set, respectively. In a first circuit family, wherein metal jumpers 40A are installed, the test set develops a predetermined potential at terminal 38 sufficient to turn on transistor 32 and allow current to flow into the second terminal of the test set permitting the current sensing circuitry to detect the presence of current flow. In a second circuit family without metal jumpers 40A, the application of the predetermined potential at terminal 38 cannot induce current to flow through identification circuit 10 due to the open circuit configuration. The current sensing circuitry of the test set then detects the absence of current flow. Thus, the presence or absence of current flowing through identification circuit 10 as monitored by the test set determines the identification of the first and second IC families.

Hence, circuit 10 provides a method for identifying to which family the ECL circuit belongs during manufacturing test at the wafer die stage as well as at final testing stages. If the voltage level at terminal 38 is raised above the voltage level at terminal 36 by V.sub.BE, current will be unilaterally conducted therebetween which can be detected to indicated which logic family the ECL circuit belongs to. It is noted that during normal operation of the logic circuits that V.sub.CC and V.sub.CCO are at the same potential, typically ground reference.

Although transistor 32 is shown as a collector-base shorted NPN diode, it is realized that any type of diode may be used as, for example, a PN or poly diode.

Hence, what has been described above is a novel option identification circuit and method for identifying different families of logic circuits having the same logic functionallity from one another. By using a metal mask option during wafer processing the circuit is coupled between first and second power supply conductors in only those logic circuits of one family and not in the other. During manufacturer testing one of the power supply conductors is raise to a higher potential than the other to produce unilateral current flow through the identification circuit which is connected therebetween by the metal option.