High Forward Blocking Voltage Protection Circuit

The present invention relates to arrangements for freeing or protecting a semiconductor switch from high forward blocking voltage stresses, often referred to as voltage spikes or voltage transients, which occur when the semiconductor switch changes from a conducting state to a non-conducting or blocking state. More particularly, the present invention relates to a system which protects the semiconductor switch against such voltage stresses or spikes and which provides for utilization of the energy which creates the voltage spikes, thus increasing the efficiency of the system.

In the past, circuits have been provided for freeing or protecting a semiconductor switch from high forward blocking voltage stresses, i.e., voltage spikes or transients, which occur as the switch is turned off. For example, DE-OS No. 3,609,375 discloses an arrangement for freeing or protecting a semiconductor switch from such high forward blocking voltages by providing a capacitor-diode circuit, called a "snubber", to absorb the energy during turn-off of the semiconductor switch by charging the capacitor of the snubber. The diode of this snubber is connected to a current converter transformer, and the capacitor of the snubber is discharged through the current converter transformer and is fed back to a voltage source, e.g. the voltage source driving the load current, by way of a useful impedance.

in arrangements according to DE-OS No. 2,644,715, oscillator circuits are provided for protecting the semiconductor switches. The oscillator circuits are composed of capacitors, inductances and diodes, and although the arrangements according to DE-OS No. 2,644,715 permit utilization of the energy during turn-off of the semiconductor switch, the arrangements require expensive circuitry. Furthmore, the parameters for such circuits are often critical.

U.S. Pat. No. 4,700,083 discloses a semiconductor switch which is equipped with a voltage limiting device including an oscillator circuit. It is also known to protect a semiconductor switch against excess voltage stresses by equipping it with a so-called RCD network (DE-OS No. 3,538,184; Electronic Design News, May 1981, pages 126-130). When using an RCD network the protection is realized by the dissipation of energy in an ohmic resistor.

Hence the present invention provides for protection of a semiconductor switch against forward blocking voltage stresses which occur as the switch is turned-off, by storing the energy which would otherwise cause the voltage stresses, and thereafter utilizing the stored energy to increase the efficiency of the system.

Accordingly, it is an object of the present invention, based on the arrangement according to DE-OS No. 3,609,375, to provide a system which permits discharge and use of the stored energy in a simple manner and which, in particular, is able to operate without additional inductive components. Moreover, a use for such arrangement is disclosed. This is accomplished with respect to the arrangement of the present invention, where a first semiconductor switch is adapted to permit current to flow through useful impedance where a relief circuit including a capacitor is charged as the first semiconductor switch is turned off, and where switch means are provided for discharging the capacitor as the first semiconductor switch is again turned on.

It is a further object of the present invention to provide for the protection of a semiconductor switch against high forward blocking voltages which occur as the switch is turned off, where the semiconductor switch which is to be prottected is part of a DC/DC converter having a primary inductance, and where the energy which is stored to protect the semiconductor switch is discharged when the semiconductor switch is turned on.

It is yet another object of the present invention to provide a system for protection of a semiconductor switch against high forward blocking voltage stresses, and to utilize the energy which is stored to protect the semiconductor switch to increase the efficiency of the system, where a second semiconductor switch is provided and where the first and second semiconductor switches are simultaneously controlled to be conducting.

It is another feature or benfit of the present invention that only a small number of additional components are required. For example, in some systems, depending upon the voltage levels, it is merely necessary to provide an additional semiconductor switch and an additional diode. By utilizing the energy which is stored as the semiconductor switch is protected against forward blocking voltages, in a systems where the circuit is employed as a DC/DC converter, efficiency can be improved considerably in a simple manner. Problems which occur in the prior art in connection with oscillator techniques--resonance turning, stability, delays--are not encountered by the present invention.

The foregoing features and benfits of the present invention, together with other objects and advantages which may be attained by its use, will become apparent upon reading the following detail description of the invention taken in conjunction with the drawings, wherein one embodiment of the invention will now be described.

In the drawings, wherein like reference characters identify corresponding components:

FIG. 1 is a basic circuit diagram for a semiconductor switch equipped with a protective circuit and employed in a DC/DC converter;

FIG. 2 is a basic circuit diagram according to FIG. 1 including details of a control circuit St of FIG. 1 for actuating the semiconductor switch; and

FIGS. 3, 4, and 5 are modifications to the basic circuit diagram according to FIG. 1.

In FIG. 1, a first semiconductor switch T1 is shown connected as a control member in a DC/DC converter. A d.c. voltage source Q provides an input voltage. An input smoothing capacitor CE is connected across the terminals of the voltage source Q. The positive terminal of the voltage source Q is provided to one side of a series combination comprising a diode D1, a power transformer U and the switching path of the first semiconductor switch which, in the present invention, is a field effect transistor T1. More specifically, the positive output of the voltage source is connected to the anode of diode D1, and the cathode of diode D1 is connected to one side of a primary winding of the power transformer. Thus the polarity of the diode D1 is such that when the field effect transistor T1 is in the conducting state, current is able to flow from voltage source Q through the primary winding w1. Power transformer U constitutes in view of transistor T1 a useful impedance which can be connected to a load circuit of a DC/DC converter. Specifically, power transformer U represents an inductance here the main inductance of a blocking converter. The power transformer includes a secondary winding w2 and a smoothing capacitor CG is provided across the secondary winding. A conventional diode D3 is provided in the secondary of the power transformer between the winding w2 and the smoothing capacitor CG. An output voltage UA is obtained across the terminals of the smoothing capacitor CG as is conventional.

Transistor T1 is illustrated as a conventional FET, or field effect transistor, having gate, source and drain electrodes. A relief circuit, --a so-called "snubber" --is provided between the drain electrode of the FET and the positive terminal of the voltage source Q. The relief circuit protects the first semiconductor switch against too high a forward blocking voltage stress during turn-off. The relief circuit comprises the series combination of a diode D2 and a capacitor C1. The diode D2 has its anode connected to the drain of electrode the FET T1, and its cathode connected to one side of the capacitor C1; the other side of the capacitor C1 is connected to the positive terminal of the input voltage source Q. Thus the polarity of the diode D2 is such that with field effect transistor T1 in the blocking or non-conducting state, a current will flow through diode D2 to charge capacitor C1.

The circuit of the present invention includes a second semiconductor switch T2, also illustrated in the preferred embodiment as a field effect transistor having gate, source and drain electrodes as is conventional. The drain electrode is connected to the junction of the diode D2 and the capacitor C1, and the source electrode is connected to the junction of the diode D1 and the primary winding w1 of the load. This circuit arrangement permits the capacitor C1 to discharge through the load.

In the embodiment shown in FIG. 1, the relief circuit is disposed between the drain electrode of FET T1 and the positive terminal of input voltage source Q. It is, of course, contemplated to position the relief circuit between the drain electrode and the negative terminal of the voltage surce Q, in which case, it is merely necessary to slightly modify the circuit as will be understood by those of ordinary skill in the art.

One of such modifications is shown in FIG. 3. Here the relief circuit is disposed between the drain electrode of FET T1 and the negative terminal of input voltage source Q. All other components are arranged as shown in FIG. 1.

In the modification shown in FIG. 4 the drain electrode of FET T1 is connected to the positive terminal of voltage source Q. The source electrode of FET T1 is in series connected via winding w1 and diode D1 to the negative terminal of voltage source Q. The series combination of diode D2 and capacitor C1 as part of the relief circuit is arranged between the source electrode of FET T1 and the negative terminal of voltage source Q. Field effect transistor T2 has its drain electrode connected to the junction of winding w1 with the anode of diode D1 and its source electrode connected to the junction of capacitor C1 with the anode of diode D2.

The embodiment of FIG. 5 is similar to the embodiment of FIG. 4 with the only difference that capacitor C1 is connected to the positive terminal of voltage source Q.

The embodiment of FIGS. 1 and 4 are advantageous in view of minimizing voltage stresses of capacitor C1. The embodiments of FIGS. 2 and 3 are advantageous in view of protecting FET T1 from high voltage stresses. The embodiments of FIGS. 1 or 4 can be for high voltage applications preferably.

The operation of the circuit as illustrated in FIG. 1 will now be explained. If field effect transistor T1 is truned on (i.e., in a conducting state) by means of a control circuit St providing an input to the gate electrode of FET T1, current flows through the diode D1, through the winding w1 on the primary side of power transformer U, and through the switching path of field effect transistor T1. This energizes the primary side of the power transformer. Then, if field effect transistor T1 is opened (i.e., blocked or turned off or non-conducting) by control circuit St, the relative polarity of the voltage across the primary winding w1 changes, and a relief current flows through diode D2 to charge capacitor C1. In this capacitor C1, the so-called "relief energy" is temporarily stored until control circuit St again switches the field effect transistor T1 into the conducting state. At the same time as the change of field effect transistor T1 to the conducting state, field effect transistor T2 is also switched to the conducting state by means of the control circuit St. The voltage UE+UC is then present across primary winding w1, with UE representing the input voltage of source Q and UC representing the voltage across capacitor C1. With field effect transistor T2 in the conducting state, capaitor C1 is able to discharge through transistor T2 and then through the power transformer U until it reaches the voltage level -UDI of diode D1. Thus a useful return energy or back energy feed is relized by simple means, namely, the stored energy is discharged to provide energy to the useful impedance - inductance of power transformer U.

Referring next to FIG. 2, the control circuit St is illustrated in greater detail in FIG. 2. The control circuit St, which is illustrated in broken lines within the circuit of FIG. 2, is suitlable to actuate the two field effect transistors T1 and T2. A clock pulse generator TG controls a pulse width modulator PBM to provide turn-on pulses for field effect transistor T1 in a conventional manner. The output pulses from the clock pulse generator TG are varied in width as a function of the magnitude of output voltage UA. The control circuit St includes an auxiliary transformer UH which has primary and secondary windings, h1 and h2, as is conventional. The primary winding h1 is connected between the output of pulse width modulator PBM and the gate terminal of field effect transistor T1. The secondary winding h2 of auxiliary transformer UH is connected in the emitter-base circuit of a push-pull driver stage composed of complementary bipolar transistors T3 and T4. The complementary bipolar transistors have their emitters connected together and their bases connected together. The output signal of the push-pull driver stage controls field transistor T2. Thus, field effect transistor T2 receives its turn-on and blocking pulses in synchronism with the turn-on and blocking pulses received by field effect transistor T1. Opposed, anode-to-anode connected Zener diodes Z1 and Z2, positioned with their respective cathodes between the gate of field effect transistor T2 and the base of the driver stage transistors, contitutes a protective circuit. To supply the push-pull driver stage with current, an auxiliary voltage UG is required across the collectors of the complementary transistors of the driver stage, and this auxiliary voltage may likewise by obtained from input direct voltage source Q. The push-pull driver stage may be equipped with a conventional anti-saturation device.

The foregoing is a complete description of a preferred embodiment of the present invention. Many changes may be made without departing from the spirit and scope of the present invention. The invention, therefore, should be limited only by the scope of the following claims.

The present disclosure relates to the subject matter disclosed in Federal Republic of Germany Patent Application No. P 37 41 221.3, filed December 5th, 1987, the entire disclosure of wihch is hereby incorporated by reference.