Comparator Having Variable Width Comparisons

The present invention relates to a logical equals comparator circuit for comparing binary quantities to determine whether or not they are equal.

An equals comparator is usually constructed by utilizing an exclusive OR circuit applied to the operands at each bit position, and then applying the output of the latter circuit to a NOR circuit to provide an active high output. It is often necessary to ignore a certain number of least significant bits in effecting such comparisons. For example, the significance of two binary quantities may be such that they are equal if a given number of the most significant bits are equal because the remaining bits are in the noise level or otherwise unmeasurable. In such circumstances a normal comparator may indicate inequality for two equal quantities. Thus, it would be necessary to tailor the comparator to the number of significant figures of each of the quantities. Should, however, the accuracy of the quantities for some reason change then either bits having no significance would be compared or not all of the significant bits would be compared. In implementing such a comparator into MOS semiconductor technology one would not be able to change the comparator physically.

Accordingly, it is an object of the present invention to provide a method of changing the number of bits that a comparator compares without having to redesign the comparator. It is a further object of the present invention to provide a comparator that allows any number of least significant bits to be ignored.

According to the invention there is provided a method of comparing two binary quantities, which includes comparing corresponding bits of each of the binary quantities and generating comparison signals to indicate equality and inequality of corresponding bits of the quantities. The comparison signals are transferred to a transfer line with the signals being arranged in order on the transfer line from the signal corresponding to the most significant bit to that corresponding to the least significant bit. A selected number of the comparison signals are coupled in order of priority from that corresponding to the most significant bits to that corresponding to the least significant bits, to an output EQUALS line in response to a plurality of decode signals.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic circuit diagram of a four bit equals comparator using two different gate types;

FIG. 1A is a legend showing the usual schematic representations of the symbols shown in FIG. 1;

FIG. 2 is a schematic circuit diagram of an alternative four bit equals comparator using only a single type of gate;

FIG. 3 is a legend explaining some of the symbols used in the drawings;

FIG. 4 is a circuit diagram of a four bit equals comparator which eliminates the use of logic gates;

FIG. 5 is a circuit diagram of yet another four bit equals comparator variant which eliminates not only the use of logic gates but also the need for four decode lines; and

FIG. 6 is a circuit diagram of an 8 bit equals comparator.

In the different Figures generally like reference numbers refer to like circuit elements which function identically.

Referring to FIG. 1 there is shown a 4 bit equals comparator having 4 exclusive OR (XOR) gates 10, 12, 14 and 18 having as input pairs bits [X(0),Y(0)], [X(1),Y(1)], [X(2),Y(2)], and [X(3),Y(3)], respectively. The outputs of the latter XOR circuits 10, 12, 14, and 18 are coupled to a transfer line 19 at transfer points 20, 22, 24 and 26, respectively. As shown in FIG. 1A, at each transfer point there is coupled a field effect transistor 43 from transfer line 19 to ground. The gate C of transistor 43 is connected to an output of a corresponding XOR circuit. The relationship of the representation of transistor 43 to the usual symbol 45 for a field effect transistor is shown in FIG. 1A.

To the transfer line 19 there is also connected through a depletion mode transistor 28 a precharging voltage source Vcc. Four decode lines A, A.sub.-- B, and B.sub.-- are used as inputs to a NOR circuit 32 and to a NAND circuit 34. A comparator output EQUALS signal 30 is coupled to line 19 after transfer point 20 corresponding to the exclusive OR circuit for the most significant bits [X(0),Y(0)].

Each XOR circuit provides a low output when its two input bits are equal and a high output when they are not equal. The high output turns on an associated one of the transistors 43 and grounds line 19. If it is transfer point 20 which grounds line 19 which is normally held high at voltage Vcc by transistor 28 and the Vcc voltage source (not shown) then EQUALS line 30 goes low. Thus unequal binary numbers result in a low output while a high output results for equal binary numbers.

Four decode lines A, A.sub.-- B, and B.sub.-- are provided to control the operation of all XOR circuits 12, 14, and 18 except that for the most significant bit pairs [X(0),Y(0)]. The output of NOR circuit 32 is (A.sub.-- +B.sub.--).sub.-- which is equivalent to A.B and that of the NAND circuit 34 is (A.sub.--.B.sub.--).sub.-- which is equivalent to A+B. Thus, XOR circuit is disabled if NOR circuit 32 provides a high output to control input 16 corresponding to A.B being true. XOR circuit 14 is gated off if A applied to control input 36 is a logic one (or true). XOR circuit 18 is disabaled by NAND circuit 34 applying a logic one output to control input 38 whenever A+B is true. It can be readily confirmed that if both A and B are high then all three least significant bits are disabled. If A is one and B is zero the two least significant bits (i.e. XOR circuits 14 and 18) are disabled. If A is set to zero and B to one then only XOR circuit 18 is disabled (corresponding to one least significant bit) while if both A and B are set to zero then no XOR circuits are disabled and all bits are compared.

A variant of the four bit comparator of FIG. 1 is shown in FIG. 2 which utilizes 3 NAND gates 16, 28 and 30 rather than the NOR gate of FIG. 1 and uses field effect transistors 40, 42, and 44 between adjacent transfer points 20, 22, 24 and 26. Each transfer point consists of two series connected transistors 52 and 54 as seen in FIG. 3. As in FIG. 1, transistor 54 is gated on by an associated XOR output while transistor 52 is gated on every positive half cycle of clock signal DCLK. Proximate each transfer point 20, 22, 24, and 26 there is a precharging transistor 32, 34, 36, and 38 which, as shown in FIG. 3, each consists of a transistor 58 coupled to Vcc and gated on by a clock signal PCLK which is non-overlapping with DCLK. A transistor 46 whose gate is coupled to the clock signal DCLK controls the passage of the signal on a transfer line 21 to an output EQUALS line 48.

The portion of transfer line 21 between transistors 40 and 46, 42 and 40, 44 and 42 and below 44 as seen in FIG. 2 are isolated from EQUALS line 48 and from each other portion until one or both of its isolating transistors is turned on. Thus, for example, the effect of the voltage on that portion of transfer line 21 between transistors 42 and 44 would not be felt on EQUALS line 48 unless all of transistors 42, 40, and 46 were turned on. The logic created by the arrangement of the coupling of NAND gates 16, 28 and 30 to lines A, A.sub.-- B, and B is such that if A=1 and B=1 then only XOR circuit 10 operating on transfer point 20 is coupled to EQUALS line 48 when transistor 46 is gated on by a DCLK signal. If A=1 and B=0 then both transfer points 20 and 22 are coupled through transistor 46 to EQUALS line 48. If A=0 and B=1 then both transistors 40 and 42 will be turned on coupling transfer points 20, 22 and 24 to EQUALS line 48 through transistor 46. Finally, if both A and B are zero then all of transistors 40, 42, and 44 will be on. Accordingly, by simply selecting values of A and B one can determine the number of bit pairs that are used to determine equality of any pair of 4 bit binary quantities. It will be appreciated that after every positive half cycle of DCLK which turns on transistors 52 and 46, any drop in voltage on transfer line 21 is restored by precharge transistors 32, 34, 36 and 38 which are gated on by PCLK thereby coupling Vcc to that portion of transfer line 21.

An equivalent circuit to that of FIG. 2 is shown in FIG. 4 which rather than logic circuits utilizes instead transistors 60, 62, 64, 66, 68, and 70 to open circuit paths between transfer points 20, 22, 24 and 26. The logic arrangement is the same as for that of FIG. 2.

A circuit which functions the same as those of FIGS. 2 and 4 but eliminates the need for true and inverse decode lines is shown in FIG. 5. In this case the arrangement of transistors 84, 86, 88, and 90 produces the logic equivalent of FIGS. 2 and 4.

Although only 4 bit comparators have been disclosed in FIGS. 1 to 5, the same technique can be extended to any number of bits. Referring to FIG. 6 there is shown an 8 bit comparator. In this case, however, an additional decode line C is required since an 8 bit comparator is really two 4 bit comparators in series. In this case XOR circuits 102, 104, 106, 108, 110, 112, 114, and 116 couple to respective transfer points 118, 120, 122, 124, 126, 128, 130, and 132. Transistors 134, 136, 138, 140, 141, 142, 144, 146, 148, 150, 152, and 154 control circuit paths between the latter mentioned transfer points as shown in FIG. 6. Precharge transistors 156, 158, 160, 162, 164, 166, 168, and 170 restore the voltage on portions of transfer line 119 proximate corresponding transfer points.

Whereas the logic arrangement of FIG. 5 was A+B, A, and B for the transistors between pairs of transfer points 20 and 22, 22 and 24, and 24 and 26, respectively, the logic arrangement of the circuit of FIG. 6 is C+A+B, C+A, C+B, C, A+B, A, and B for the transistors between respective transfer points 118 and 120, 120 and 122, 122 and 124, 124 and 126, 126 and 128, 128 and 130, and 130 and 132. Thus, if C=1 only the first 4 most significant bits can be selected by values of A and B while if C=0 then all of the first 4 bits are selected and only bits of the last 4 bits may be selected depending on the values of A and B. Again transistor 172 gated by DCLK controls passage of the voltage level to EQUALS line 174.

In a similar way two 8 bit comparators can combine to produce a 16 bit comparator, four 8 bit comparators can make a 32 bit comparator and so on. Thus, in general N decode lines will produce a 2.sup.N bit comparator and any number of bits can be made by simply designing a comparator for the next higher power of 2 and then deleting the unnecessary most significant bits.

While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is, therefore, contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.