US 4,929,852 AGrant
TTL to CMOS Input Buffer Circuit
Issue Date:1990-05-29
•11 Claims
•4 Drawing Sheets
Abstract
A TTL to CMOS buffer circuit includes a first buffer receiving a TTL input and a second buffer providing a CMOS output. The first buffer has a first power input connected to Vcc, a second power input connected through a resistor to Vcc, and a third power input connected to Vss. The second buffer has a first power input connected to Vcc, a second power input connected through a resistor to Vss, and a third power input connected to Vss. In the first buffer, two PMOS transistors and three NMOS transistors are serially connected by their current electrodes between the second and the third power input, in that sequence; the second power input is connected to the P channel transistor end of the series and the third power input is connected to the N channel end of the series. In the second buffer, two PMOS transistors and one NMOS transistor is serially connected by their current electrodes in that sequence between the first and the second power inputs; the first power input is connected to the P channel transistor end of the series, and the second power input is connected to the N channel end of the series. The first buffer's first power input is connected to the gate of an NMOS transistor in that buffer, and the second buffer's third power input is connected to the gate of a PMOS transistor in that buffer.
Metadata
Assignee
- Samsung Semiconductor & Telecommunications Co.
Inventor
- Myung H. Bae
Application Information
Application Number:US 225848&
Filing Date:1988-07-29
Priority Date:1987-08-01
Art Unit:254
Classifications
IPC:
H03K 19094
Field of Search:
307447;448;451;475;290;446;296.1
Patent Drawings (4 sheets)
Description
Background and Field of the Invention
This invention relates to a buffer circuit receiving a TTL input and providing a C-MOS output. Ideally, the stand-by current when the buffer does not operate should be minimal; the difference in circuit speed between that based on a high input and that based on a low input should be minimal, as circuit speed does not overly depend on the input value; the difference in circuit speed between that with one Vcc level and that with a different Vcc level should be minimal; the set-up time and the hold time of address and of data should be stable and easy to control; and the margin of respective high and low input voltage levels should be adequate. Traditional buffer circuits in the prior art are less than ideal and there exists much room for improvement.
Summary of the Invention
A TTL to CMOS input buffer is provided including a first buffer part receiving the TTL input and a second buffer part receiving a signal from the first buffer part and providing a CMOS output. The first buffer part includes a buffer having three power supply inputs; the first power input is connected to a source Vcc; the second power input is connected through a resistor to a source Vcc; and the third power input is connected to a ground source Vss. The second buffer part includes a buffer having three power supply inputs; the first power input is connected to a source Vcc; the second power input is connected through a resistor to a ground source Vss; and the third power input is connected to a ground source Vss.
Brief Description of the Drawings
FIG. 1 illustrates a block diagram of the present invention.
FIG. 2 illustrates the electrical circuit diagram of the invention of FIG. 1.
FIG. 3 illustrates a block diagram of a traditional buffer of the prior art.
FIG. 4 illustrates the electrical circuit diagram of the traditional buffer of FIG. 3.
FIG. 5A defines the speed of a buffer circuit when the TTL input changes from high to low, which is used as a basis of comparison of the present invention with the traditional buffer of the prior art.
FIG. 5B defines the speed of a buffer circuit when the TTL input changes from low to high, which is used as a basis of comparison of the present invention with the traditional buffer of the prior art.
FIG. 6A illustrates a graph of the buffer's speed (both for the present invention and for the prior art) as the voltage of a low TTL input signal is increased, for separate Vcc levels.
FIG. 6B illustrates a graph of the buffer's speed (both for the present invention and for the prior art) as the voltage of a high TTL input signal is decreased, for separate Vcc levels.
Detailed Description
A traditional buffer circuit in the prior art is shown in FIG. 3 in a block diagram. The buffer circuit includes a first buffer part 100 receiving TTL input signal and a second buffer part 200 providing a C-MOS output signal. The first buffer part includes a buffer 10 and two power supplies 20 and 30 separately connected to buffer 10. The second buffer part includes a buffer 40 and two power supplies 50 and 60 separately connected to buffer 40. And buffer 10 of the first buffer part supplies a signal as input to the second buffer part. An electrical circuit diagram of such a traditional buffer circuit is shown in FIG. 4.
A block diagram of the present invention is shown in FIG. 1. A first buffer part 1000 receives a TTL input signal and is connected to a second buffer part 2000 which provides the output of the present invention. The first buffer part includes a buffer 150, a first power supply 200, a second power supply 300, and a third power supply 450; the first and second power supplies are connected to one side of the buffer 150 and the third power supply is connected to an opposing side of buffer 150. The second buffer part includes a buffer 500 which receives the output from buffer 150 within the first buffer part, a first power supply 600, a second power supply 700, and a third power supply 800; the first power supply is connected to one side of buffer 500 and the second and third buffer supplies are connected to an opposing side of buffer 500.
As indicated in FIG. 2, the first power supplies 200 and 600 respectively supplies Vcc from an external source; the third power supplies 450 and 800 respectively supplies ground source Vss from an external source; the second power supply 300 supplies a voltage dropped from an external source Vcc by Vcc through resistor RVcc; the second power supply 700 supplies a voltage offset by .DELTA. Vss through resistor RVcc from an external ground source Vss.
In the first buffer part 1000, the current electrodes of five transistors TR1, TR2, TR3, TR4, and TR5 are connected in series and in that sequence. TR1 and TR2 are P channel MOS transistors and TR3, TR4, and TR5 are N channel MOS transistors. Power supply 300 is connected to a current electrode of TR1 opposing that connected to TR2, and power supply 450 is connected to the source electrode of TR5 whose other current electrode is connected to TR4. The gate electrode of TR2, TR4, and TR5 are connected to the TTL input. Power supply 200 is connected to the gate electrode of TR3. Also within the first buffer part 1000 is an N channel MOS transistor TR6 whose gate electrode is connected to the gate electrode of TR1; the source and gate electrodes of TR6 are connected to the source electrode of TR5; and the drain electrode of TR6 is connected to the point of serial connection between TR2 and TR3. First buffer part 1000 provides an output from the drain electrode of TR6 to the second buffer part 2000.
In the second buffer part 2000, the current electrodes of three transistors TR7, TR8, and TR9 are connected in series and in that sequence. TR7 and TR8 are P channel MOS transistors and TR9 is an N channel MOS transistor. The gate electrodes of TR7 and TR8 are connected to the drain electrode of TR6 within first buffer part 1000. The first power supply 600 is connected to a current electrode of TR7 opposite that connected to TR8, and the second power supply 700 is connected to the source electrode of TR9 whose drain is connected to TR8. Also within the second buffer part 2000 is another N channel MOS transistor TR10 whose gate and source electrodes are connected to the gate electrode of TR7 and also to the third power supply 800, and whose drain electrode is connected to the point of serial connection between the current electrodes of TR8 and TR9. The second buffer part 2000 provides output signal X from the point of serial connection between TR8 and TR9.
At node A, the voltage is Vcc minus that dropped through resistor RVcc. Node B represents the point of connection between TR1 and TR2; node C represents the point of connection between TR2 and TR3; node D represents the point of connection between TR3 and TR4; node E represents the point of connection between TR4 and TR5; node F represents the point of connection between TR7 and TR8; node G represents the point of connection between the current electrodes of TR8 and TR9; node H represents the point of connection between TR9 and second power supply 700.
During circuit operation, when the TTL input is in stand-by state at (2.4 V, node A has the voltage Vcc-.DELTA. Vcc. TR1 causes the voltage at node B to become equal to that at node A, because the absolute value of the difference in voltage between that at its gate (Vss) and that at node A (Vcc-.DELTA. Vcc) is greater than the absolute value of its threshold voltage of about 1.0 V.
TR2 in an on state causes the voltage at node C to become equal to that at node B, because the absolute value of the difference in voltage between that at its gate (2.4 V) and that at node B (Vcc-.DELTA. Vcc-(2.4 V) is greater than the absolute value of its threshold voltage. TR5 in an on state causes the voltage at node E to become equal to that supplied by power supply 450 (ground source Vss), because the difference in voltage between that at its gate (2.4 V) and Vss is greater than its threshold voltage of about 0.8 volts. TR4 in an on state causes the voltage at node D to become equal to that at node E (Vss if TR5 is on), because the difference in voltage between that at its gate (2.4 V) and that at node E, (2.4 V-Vss, is greater than its threshold value. TR3 causes the voltage at node C to become equal to that at node D (Vss if TR5 and TR4 are on), because the difference in voltage between that at its gate and that at node D is Vcc-Vss, a value greater than the threshold voltage of TR3.
Consequently, a constant current always flows from power supply 300 (through resistor RVcc from external source Vcc) to node C through resistor, TR1, and TR2. Similarly, a constant current flows from node C to power supply 450 (ground source Vss) through TR3, TR4, and TR5. The voltage at node C is determined by the amount of current flow into and out of node C.
In the stand-by state, node C has a constant voltage almost the same as ground source Vss, because the current flow from node C to power supply 450 is greater than the current flow from power supply 300 to node C. TR10 is always off as its gate is grounded through power supply 800 supplying ground Vss. TR7 is always on and causes the voltage at node F to become equal to that supplied by power supply 600 (Vcc), because the absolute value of the difference in voltage between that at its gate and that of power supply 600, Vcc-Vss, is greater than the threshold voltage of TR7. TR8 is always on and causes the voltage at node G to become equal to that at node F (Vcc if TR7 is on), because the voltage at node C is almost the same as ground source Vss and because the absolute value of the difference in voltage between that at its gate and that at node F is greater than the absolute value of the threshold voltage of TR8. Output signal X is taken from node G. TR9 is off because the voltage at node C is almost near ground source Vss and because the voltage at node H is Vss+.DELTA. Vss; the absolute value of the difference in voltage between that at the gate of TR9 and that at node H is less than TR9's threshold voltage.
When the voltage of the TTL input is changed from V.sub.IH (input high voltage=(2.4 V) to V.sub.IL (input low voltage=0.8 V), the current flow from power supply 300 to node C increases because the absolute value of the difference in voltage between that at the gate of TR2 and that at node D increases.
When the difference in voltage between that at the gate of TR5 and power supply 450 (ground source Vss) and between that at the gate of TR4 and that at node E decreases respectively, the amount of current flow from node C to power supply 450 (ground source Vss) decreases. When V.sub.IL reaches 0.8 V, TR4 and TR5 are nearly off and the voltage at node C becomes high at Vcc-.DELTA. Vcc.
When the voltage at node C becomes high, TR8 is turned off because the absolute value of the difference in voltage between that at node C and that at node F is smaller than the absolute value of the threshold voltage of TR8; TR9 is turned on because the absolute value of the difference in voltage between that at its gate and that at node H is greater than its threshold value. When TR9 is turned on, the voltage at node G becomes equal to that supplied from power supply 700 (Vss+.DELTA. Vss) and is provided as output signal X in a low state.
When TTL input voltage increases from V.sub.IL (0.8 V) to V.sub.IH (2.4 V), the amount of current flow into node C through TR2 decreases and the amount of current flow out of node C to power supply 450 (ground source Vss) through TR4 and TR5 increases. The voltage at node C becomes low, turning off TR9, turning on TR8, and making the output signal X become high at Vcc.
The invention as described above minimizes the amount of stand-by current, minimizes the change in speed with respect to the change in TTL input voltage, minimizes the change in speed with respect to changes in the power supply (external source Vcc), and provides a wide-range margin for the input voltage.
With regard to minimizing the stand-by current, when Vcc=6 V and at a low temperature of -10.degree. C., much current flows. But at that condition, when the TTL input is 2 V, the subject invention as shown in FIG. 2 yields a current flow of 0.18 mA, whereas the optimized traditional circuit shown in FIG. 3 yields a current flow of 0.37 mA. Thus, the improvement provided by this invention is represented by a reduction in current by about 50%. In this invention, the current flow into the buffer circuit through TR1 is reduced because resistor RVcc reduces the voltage supplied to TR1 from Vcc to Vcc-.DELTA. Vcc. Thus, the amount of stand-by current is reduced.
With regard to minimizing the change in speed relative to the change in TTL input voltage, the effect is shown in FIGS. 5 and 6. The speed referred to is based on respective time periods t.sub.L (TTL input going from high to low) and t.sub.H (TTL input going from low to high) required from the time the TTL input has reached its changed level for the output signal (X and S) to reach the middle of its transition to a different level.
Table 1 below illustrates a comparison of t.sub.I , t.sub.h , and [t.sub.h -t.sub.L ] between a traditional circuit and the subject invention, with V.sub.IH =(2.4 V and V.sub.IL =0.8 V at the specified conditions.
As indicated by Table 1, the TTL to CMOS buffer of the present invention reduces the difference between t.sub.H and t.sub.L, when the input varies from V.sub.IH and V.sub.IL. Additionally, as shown in table 1, for the traditional circuit, the difference between the slowest t.sub.L and the slowest t.sub.H is 0.9 ns, whereas that difference for the subject invention is much smaller, 0.2 ns.
The set-up time and hold time of the buffer are made m re stable by a reduction in the difference between t.sub.H and t.sub.L, because a difference between t.sub.H and t.sub.L is reflected in a difference between the set-up time and the hold time. The small difference between t.sub.H and t.sub.L can also be noted in FIG. 5.
In the embodiment shown in FIG. 2, when the input voltage changes from V.sub.IH (2.4 V) to V.sub.IL (0.8 V), because the difference in voltage between that at the gate and at the source of TR4 and R5 becomes almost or exactly the same as their threshold voltage, they are both turned off. Thus, the voltage at node C is high, as no current flows from node C to ground source Vss in power supply 450. The high voltage at node C turns off TR8, and turns on TR9, thereby causing output signal X (voltage at node G) to become low as node G is thus connected to ground source Vss.
When TTL input changes from V.sub.IL (0.8 V) to V.sub.IH (2.4 V), the current flow into node C through TR1 and TR2 (which are continuously on) is reduced, and TR3, TR4, and TR5 are turned on to increase current flow from node C to ground source Vss through power supply 450. In that circumstance, it takes a long time for the voltage at node C to change from high to low and for output signal X at node G to go high. Thus, a difference between t.sub.L and t.sub.H exists, as input varies between V.sub.IH and V.sub.IL. In the present invention, that difference is reduced by a reduction in the amount of current flow from node C to ground source Vss in power supply 450 by including a resistor RVcc within power supply 300 which then supplies Vcc through resistor RVcc. That difference is also reduced by more rapidly causing output signal X to change to high through more quickly turning off TR9 when the voltage at node C goes low; that is made possible by the inclusion of a resistor RVss in power supply 700 which then supplies ground source Vss through resistor RVss to node H which would have a voltage Vss+.DELTA. Vss.
The size of TR4 and TR5 are enlarged to prevent t.sub.H, when Vcc=6 V/-10.degree. C., from becoming too large (circuit too slow); t.sub.H is very slow when Vcc=6 V/-10.degree. C. Because of that enlargement, when Vcc=4 V/100.degree. C., t.sub.H is less than t.sub.L (circuit being faster).
For illustrating the subject invention's minimizing the variation in speed relative to a change in Vcc or other external voltage supply, Tables 2A and 2B are presented below. Table 2A illustrates the case for V.sub.IH =2.4 V constant and V.sub.IL takes on several values as the power source supplying Vcc is changed. Table 2B illustrates the case for V.sub.IL =0.8 V constant and V.sub.IH takes on several values as the power source supplying Vcc is changed. The results for both a traditional buffer and for the present invention are shown in Tables 2A and 2B for comparison.
As shown above in tables 2A and 2B, the values of t.sub.L and t.sub.h are reduced by the present invention. Variations in t.sub.L and t.sub.H due to changes in the level of external power source Vcc affects the buffer circuit's operational speed when the TTL input is a control signal, and affects the set-up time and hold time of the buffer circuit when the TTL input signal is an address or is data.
The present invention stabilizes the buffer circuit's overall operational speed, and also stabilizes the set-up time and hold time of address and of data with respect to changes in power supply source Vcc, because of the reduction in the circuit's change in speed due to changes in source Vcc. The buffer circuit's operational speed is stabilized with respect to changes in Vcc, because resistor RVcc is used in power supply 300 to connect source Vcc to the buffer circuit and because resistor RVss is used in power supply 700 to connect external ground source Vss to the buffer circuit.
To discuss circuit conditions when there is a change in Vcc, the following designations are used. For a high Vcc, VccH represents Vcc high; .DELTA. VccH represents the voltage across resistor RVcc; and .DELTA. VssH represents the voltage across resistor RVss when TR9 is turned on. For a lower Vcc, VccL represents Vcc; .DELTA. VccL represents the voltage across resistor RVcc; and .DELTA. VssL represents the voltage across resistor RVss when TR9 is turned on.
With reference to FIG. 2, the voltage at node A when Vcc=VccH is VccH-.DELTA. VccH; and the voltage at node A when Vcc=VccL is VccL-.DELTA. VccL. The change in voltage at node A, when Vcc takes on respective different values (VccH and VccL) is computed by taking the difference between (VccH-.DELTA. VccH) and (VccL-.DELTA. VccL): ##EQU1## That result indicates that the change in voltage at node A, when Vcc takes on respective different values of VccH and VccL, is smaller in value (by .DELTA. VccH-.DELTA. VccL) than the variation in external source Vcc.
When TR9 is turned on and where Vcc=VccH, the difference in voltage between the gate and source of TR9 is VccH-.DELTA. VssH and is designated as V.sub.G51. When TR9 is turned on and where Vcc=VccL, the difference in voltage between the gate and source of TR9 is VccL-.DELTA. VccL and is designated V.sub.G52. The difference between V.sub.G51 and V.sub.G52 is computed as follows:
That difference is less than VccH-VccL, the variation in the source Vcc. Thus, the incorporation of resistors RVcc and RVss in the present invention has reduced the impact of changes in the source Vcc.
FIGS. 6A and 6B illustrate the wide-range of input margin obtained by the present invention for the TTL input voltage. With reference to FIG. 6A, when Vcc=4 V/100.degree. C. and as V.sub.IL increases, t of both a traditional circuit and of the present invention increase, and both increase in a progressively faster rate. But t.sub.L in a traditional circuit eventually exceeds and increases toward infinity at a faster rate than that of the present invention. The bigger is t.sub.L, the slower is the circuit. When V.sub.IL exceeds a given point, t.sub.L would become so high that the buffer circuit would not be able to receive properly a low TTL input voltage. As is shown in FIG. 6A, the traditional circuit would reach that point earlier than would the present invention. Consequently, the present invention would operate to receive a wider range of low input voltage Vil, and thus has a wider V.sub.IL margin.
With reference to FIG. 6B, when Vcc=6 V/-10.degree. C. and as V.sub.IH decreases, t.sub.H of both a traditional circuit and of the present invention increase, and both increase in a progressively faster rate. But t.sub.H in a traditional circuit eventually increases at a faster rate than that of the present invention towards infinity. When V.sub.IH gets to be less than a given point, t.sub.H would become so high that the buffer circuit would not be able to receive properly a high input TTL voltage. As is shown in FIG. 6B, a traditional buffer circuit would reach that point sooner than would the present invention. Consequently, the present invention would operate to receive a wider range of high input voltage V.sub.IH, and thus has a wider V.sub.IH margin.
In accordance with the invention as described above, when numerous TTL input buffers are used, as in a memory circuit, the stand-by current for all such buffers are reduced; when the TTL input is an address or is data, the set-up time and hold time are stabilized by minimizing the difference between t.sub.H and t.sub.L and by minimizing variations in t.sub.H and t.sub.L relative to changes in source Vcc; the reduction in the variations in t.sub.H and t.sub.L due to changes in source Vcc also stabilizes the buffer circuit's operational speed when the TTL input is a control signal; a wider margin of voltage variation is acceptable as a high input signal (2.4 V and lower voltages) and as a low input signal (0.8 V and higher voltages) than that which is accepted by a traditional buffer circuit.
Claims
I claim:
1. A TTL to CMOS input buffer comprising: a first buffer receiving a TTL input signal and a second buffer receiving an input from said first buffer and providing a CMOS output signal; said first buffer having first, second, and third power supply inputs; said first power input of said first buffer is connected to a source Vcc; said second power input of said first buffer is connected through a resistor to a source Vcc; and said third power input of said first buffer is connected to a source Vss; and said second buffer having a first, second, and third power supply inputs; said first power input of said second buffer is connected to a source Vcc; said second power input of said second buffer is connected through a resistor to a source Vss; and said third power input of said second buffer is connected to a source Vss.
2. A TTL to CMOS input buffer as recited in claim 1, wherein: said first buffer includes a plurality of transistors of which the current electrodes are serially connected between said second power input and said third power input of said first buffer; a control electrode of one of said serially connected plurality of transistors in said first buffer is connected to said first power input of said first buffer; said second buffer includes a plurality of transistors of which the current electrodes are serially connected between said first power input and said second power input of said second buffer; a control electrode of said plurality of serially connected transistors in said second buffer is connected to said third power input of said second buffer.
3. A TTL to CMOS input buffer as recited in claim 2, wherein: said plurality of serially connected transistors in said first buffer includes first and second P channel MOS transistors and first, second, and third N channel MOS transistors; said plurality of serially connected transistors in said second buffer includes first and second P channel MOS transistors and a first N channel MOS transistor.
4. A TTL to CMOS input buffer as recited in claim 3, wherein in said first buffer: said first P channel MOS transistor has its source connected to said first power input and its drain connected to the source of said second P channel MOS transistor; said second P channel transistor has its drain connected to the drain of said first N channel transistor; said first N channel transistor has its source connected to the drain of said second N channel transistor; said second N channel transistor has its source connected to the drain of said third N channel transistor; and said third N channel has its source connected to said third power input.
5. A TTL to CMOS input buffer as recited in claim 4, wherein in said second buffer: said first P channel MOS transistor has its source connected to said first power input and its drain connected to the source of said second P channel MOS transistor; said second P channel MOS transistor has its drain connected to the drain of said first N channel MOS transistor; said first N channel MOS transistor has its source connected to said second power input.
6. A TTL to CMOS input buffer as recited in claim 5, wherein: said first buffer further includes a fourth N channel MOS transistor of which the drain is connected to a point of connection between the drain of said second P channel transistor of said first buffer and the drain of said first N channel MOS transistor of said first buffer, and of which the source is connected to said third power input of said first buffer.
7. A TTL to CMOS input buffer as recited in claim 6, wherein: said second buffer further includes a second N channel MOS transistor of which the drain is connected to a point of connection between the drain of said second P channel MOS transistor of said second buffer and the drain of said first N channel MOS transistor of said second buffer, and of which the source is connected to said third power input of said second buffer.
8. A TTL to CMOS input buffer as recited in claim 7, wherein: said signal supplied from said first buffer to said second buffer is taken from a point of connection in said first buffer between the drain of said second P channel MOS transistor, the drain of said first N channel transistor, and the drain of said fourth N channel MOS transistor; and said output signal provided by said second buffer is taken from a point of connection in said second buffer between the drain of said second P channel MOS transistor, the drain of said first N channel MOS transistor, and the drain of said second N channel MOS transistor.
9. A TTL to CMOS input buffer as recited in claim 8, wherein in said first buffer; the gate of said first P channel MOS transistor, and the gate and the source of said fourth N channel MOS transistor are also connected to said third power input; the gate of said second P channel MOS transistor, the gate of said second N channel MOS transistor and the gate of said third N channel MOS transistor are all connected to said TTL input; and the gate of said first N channel MOS transistor is connected to said first power input.
10. A TTL to CMOS input buffer as recited in claim 8, wherein in said second buffer; the gate of said first P channel MOS transistor, the gate of said second N channel MOS transistor, and the source of said second N channel MOS transistor are all connected to said third power input; and the gate of said second P channel MOS transistor and the gate of said first N channel MOS transistor both receive said signal supplied from said first buffer.
11. A TTL to CMOS input buffer as recited in claim 9, wherein in said second buffer: the gate of said first P channel MOS transistor, the gate of said second N channel MOS transistor, and the source of said second N channel MOS transistor are all connected to said third power input; and the gate of said second P channel MOS transistor and the gate of said first N channel MOS transistor both receive said signal supplied from said first buffer.
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