Overvoltage Suppressing Circuit for Semiconductor Device

1. Field of the Invention

The present invention relates to an overvoltage suppressing circuit for a semiconductor device which is adapted to suppress an overvoltage of a semiconductor switching device used for a power converter or the like.

2. Description of the Related Art

FIG. 7 is a circuit diagram of a chopper circuit having an overvoltage suppressing circuit of a semiconductor device disclosed in "Voltage Clamp Circuit for a Power MOSFET PWM Inverter" IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS Vol. IA-23 No. 5 SEPTEMBER/OCTOBER 1987, pp. 911-920. In the drawing, the chopper circuit comprises a DC power source 1; a transistor 2; a parasitic capacitance 3 between the main circuit terminals of the transistor 2; a reflux diode 4 inserted between the emitter of the transistor 2 and the negative pole of the DC power source 1; a load device 5 connected in parallel with the reflux diode 4; and an overvoltage suppressing circuit 6 for the transistor 2 including an overvoltage suppressing capacitor 61, an oscillation suppressing diode 62, and a discharging resistor 63 for the overvoltage suppressing capacitor 61.

The overvoltage suppressing capacitor 61 and the oscillation suppressing diode 62 are connected in series between the collector and emitter of the transistor 2, while the discharging resistor 63 is connected between the negative pole of the DC power source 1 and a connecting point between the overvoltage suppressing capacitor 61 and the oscillation suppressing diode 62.

In the drawing, reference numeral 7 denotes an inductance of the wiring.

A description will now be given of the operation with reference to a waveform diagram shown in FIG. 8. The transistor 2 being energized is turned off at time T.sub.0.

A voltage V.sub.CE between the main circuit terminals of the transistor 2 rises from time T.sub.0 and reaches a terminal voltage V.sub.D of the DC power source at time T.sub.1. After time T.sub.1, the current i.sub.c of the transistor 2 decreases gradually from a collector DC current Ic. The inductance 7 of the wiring tries to maintain a current i.sub.D flowing from the DC current source 1 at a constant level. Since the current i.sub.D of the DC power source 1 is branched at a Connection point P.sub.1 into the current i.sub.C flowing to the transistor 2 and a current i.sub.S flowing to the overvoltage suppressing circuit 6, the following relationship exists among the currents i.sub.D, i.sub.C and i.sub.S :

Accordingly, if the current i.sub.D is assumed to be fixed during the period from the time T.sub.1 to the time T.sub.2, as shown in FIG. 8, the current i.sub.S flowing into the overvoltage suppressing circuit 6 increases in accordance with Formula (1) with a decrease in the current flowing through the transistor 2.

The period from time T.sub.2 to time T.sub.3 is a period in which energy accumulated in the inductance 7 of the wiring is absorbed by the capacitor 61. In addition, when the current i.sub.S is reduced to 0 at time T.sub.3, a current flows through the diode 62 in the opposite direction since the diode 62 does not have ideal characteristics, so that the current flowing through the diode 62 is suddenly cut off at time T.sub.4 when the, internal carriers disappear.

For this reason, the current which has been flowing through the diode 62 commutes to the parasitic capacitance 3 of the transistor 2.

After time T.sub.4, since the diode 62 is off, the voltage V.sub.CE of the transistor 2 undergoes damped oscillation, from a maximum voltage V.sub.P of the overvoltage suppressing capacitor 61, due to the parasitic capacitance 3, the inductance 7 of the wiring, and the component of resistance contained in the wiring. In addition, the energy charged in the overvoltage suppressing capacitor 61 from the inductance 7 of the wiring during the period from time T.sub.2 to T.sub.3 is discharged through the discharging resistor 63. Accordingly, a current i.sub.R flowing through the discharging resistor 63 declines after time T.sub.4, as shown in FIG. 8.

Since the conventional overvoltage suppressing circuit for a semiconductor device is arranged as described above, there has been a problem that, due to the phenomenon in which the current passing through the transistor 2 changes suddenly to cause voltage oscillation in the transistor 2 when the diode 62 is turned off so that the electromagnetic noise generated by the apparatus becomes large.

Accordingly, it is an object of the present invention to provide an overvoltage suppressing circuit of a semiconductor device which is capable of suppressing the overvoltage of a semiconductor switching device and which is capable of reducing the electromagnetic noise to a low level.

To this end, an overvoltage suppressing circuit for a semiconductor device in accordance with the present invention comprises a serial circuit connected in parallel with a semiconductor device and including an overvoltage suppressing capacitor, an oscillation suppressing diode, and impedance regulating means connected in series each other, the oscillation suppressing diode being turned off due to the switching operation of the semiconductor device, the impedance regulating means being operable to change into a state of high impedance for suppressing a reverse current flowing into the oscillation suppressing diode when the oscillation suppressing diode is turned off; and discharging means connected between a DC power source and the overvoltage suppressing capacitor for discharging to a DC power source a charge accumulated in the overvoltage suppressing capacitor when the oscillation suppressing diode is off.

FIG. 1 is a circuit diagram of a chopper circuit having an overvoltage suppressing circuit for a semiconductor device in accordance with a first embodiment of the present invention;

FIG. 2 is a timing chart illustrating the operation of the first embodiment;

FIG. 3 is a B-H characteristic diagram of a saturable reactor used in the first embodiment;

FIG. 4 is a circuit diagram illustrating an overvoltage suppressing circuit in accordance with a second embodiment;

FIG. 5 is a circuit diagram illustrating a chopper circuit having an overvoltage suppressing circuit in accordance with a third embodiment;

FIG. 6 is a circuit diagram illustrating an overvoltage suppressing circuit in accordance with a fourth embodiment;

FIG. 7 is a circuit diagram illustrating a chopper circuit having a conventional overvoltage suppressing circuit; and

FIG. 8 is a timing chart illustrating the operation of the circuit shown in FIG. 7.

Referring now to the accompanying drawings, a description will be given of the embodiments of the present invention.

In FIG. 1, the collector of a transistor 2 used as a semiconductor switching device is connected to the positive pole of a DC power source 1, while a reflux diode 4 is connected between the emitter of the transistor 2 and the negative pole of the DC power source 1. A load device 5 is connected in parallel with this reflux diode 4. The transistor 2 has a parasitic capacitance 3 between main circuit terminals A and B thereof, i.e., between the collector and the emitter, and a serial circuit comprising a saturable reactor 64 and a first capacitor 65 for saturating the saturable reactor 64 is connected between the collector and the emitter of the transistor 2. In addition, a serial circuit comprising a second capacitor 61 for overvoltage suppressing and an oscillation suppressing diode 62 is connected to the first capacitor 65 in parallel therewith. A point of connection between the second capacitor 61 and the oscillation suppressing diode 62 is connected to the negative pole of the DC power source 1 via a discharging resistor 63. An overvoltage suppressing circuit 6 for the transistor 2 is formed by the second capacitor 61, the oscillation suppressing diode 62, the discharging resistor 63, the saturable reactor 64, and the first capacitor 65. In addition, the wiring connecting the DC power source 1, the transistor 2, and the load device 5 has an inductance 7. It should be noted that the saturable reactor 64 should be selected which has characteristics of moving smoothly from a non-saturated area to a saturated area and that V.sub.L denotes a terminal voltage of the saturable reactor 64 in FIG. 1.

A description will now be given of the operation with reference to FIGS. 2 and 3. FIG. 2 illustrates the waveforms of a voltage or current in various parts when the transistor 2 is turned off. FIG. 3 illustrates the B-H characteristics of the saturable reactor 64 and points of operation at the respective times shown in FIG. 2.

The transistor 2 remains on until the time T.sub.0 shown in FIG. 2, and is turned off after the time T.sub.0. Due to this turning off operation, a voltage V.sub.CE between the main circuit terminals A and B of the transistor 2 rises after the time T.sub.0.

At the time T.sub.0, the voltage of the first capacitor 65 is 0 V, while the saturable reactor 64 is unsaturated at this time T.sub.0, if it is assumed that an exciting current is very small at the time of non-saturation as shown in FIG. 3.

After the time T.sub.0, the same voltage as the voltage V.sub.CE between the main circuit terminals of the transistor 2 is applied to the saturable reactor 64. The saturable reactor 64 becomes saturated at time T.sub.0A by a time integral of this voltage.

After the saturable reactor 64 has become saturated at the time T.sub.0A, electrically speaking, the situation is the same as that in which no saturable reactor 64 is provided. The voltage V.sub.CE between the main circuit terminals of the transistor 2 reaches the terminal voltage V.sub.D of the DC power source 1 at the time T.sub.1 while the capacitor 65 is being charged, as shown in FIG. 2.

Although, after the time T.sub.1, the current i.sub.C of the transistor 2 decreases from a collector DC current I.sub.C of the transistor 2, since the inductance 7 of the wiring attempts to maintain the current i.sub.D, which has been flowing from the DC power source 1, at a constant level, the reduced amount of the current i.sub.C flowing through the transistor 2 flows to the overvoltage suppressing circuit 6.

In addition, from the time T.sub.2 when the current i.sub.C flowing through the transistor 2 becomes zero, the energy accumulated in the inductance 7 of the wiring is absorbed by the first and second capacitors 65 and 61 of the overvoltage suppressing circuit 6.

At the time T.sub.3 when the current i.sub.D from the DC power source 1 and the current i.sub.S of the overvoltage suppressing circuit 6 are reduced to zero, the saturable reactor 64 enters an unsaturated region, as shown in FIG. 3, and the impedance thereof becomes high. Accordingly, no large current in the reverse direction flows to the oscillation suppressing diode 62, and an excessive amount of carriers accumulated in the P-N ]unction disappear.

As a result, since the oscillation suppressing diode 62 is off when the saturable reactor 64 enters a saturated region at the time T.sub.4, most of the energy of the inductance 7 of the wiring accumulated in the second capacitor 61 passes through the discharging resistor 63 and the saturable reactor 64 as the discharging current i.sub.R, as shown in FIG. 2, and is discharged into the DC power source 1 without undergoing oscillation.

Meanwhile, at the time T.sub.4, a remaining amount of the energy of the inductance 7 of the wiring accumulated in the first capacitor 65 passes through the saturable reactor 64 and the load device 5 or the reflux diode 4 and is discharged into the DC power source 1 without undergoing oscillation.

At the time T.sub.5 when the discharging of the first and second capacitors 65 and 61 is completed, the saturable reactor 64 has the same point of operation as that at the time T.sub.0, as shown in FIGS. 2 and 3.

Thus, in accordance with this embodiment, when the oscillation suppressing diode 62 in the overvoltage suppressing circuit 6 is turned off, a reverse current is suppressed by the saturable reactor 64, and this saturable reactor 64 is saturated via the first capacitor 65 when the voltage V.sub.CE between the main circuit terminals A and B of the transistor 2 rises. Accordingly, an Overvoltage and voltage oscillation occurring at the time of the switching of the transistor 2 can be suppressed. In addition, the level of magnetic noise generated can be reduced.

Although, in the above-described embodiment, the saturable reactor 64 is inserted between the main circuit terminal A of the transistor 2 and a point P.sub.2 of connection between the first and second capacitors 65 and 61, it is possible to obtain a similar effect if the saturable reactor 64 is inserted between the main circuit terminal B of the transistor 2 and a point P.sub.3 of connection between the first capacitor 65 and the oscillation suppressing diode 62 as shown in FIG. 4.

Furthermore, although the case has been described in which one end of the semiconductor switching device, i.e., the collector of the transistor 2, is connected to the positive pole of the DC power source 1, the present invention can also be applied to a case in which one end of the transistor 2 is connected to the negative pole of the DC power source 1, as shown in FIG. 5, and it is possible to obtain an advantage similar to that of the abovedescribed embodiment. In addition, in this case as well, the saturable reactor 64 may be connected to one end B of the transistor 2 and the point P.sub.3 of connection between the first and second capacitors 65 and 61, as shown in FIG. 6.

Moreover, although in the foregoing embodiments an example has described of the case in which the present invention is applied to a chopper circuit, an advantage similar to those of the foregoing embodiments can be obtained when applied to an inverter circuit or the like.

In addition, although in the foregoing embodiments, an example has been illustrated of the case in which the transistor 2 is used as a semiconductor switching device, a similar advantage can be obtained when a MOSFET, a BiMOS device, an IGBT (insulated-gate bipolar transistor) or a similar semiconductor switching device is used.